| blob | 6b850670de1df9da01b043dac83dea9c3afa550d |
1 /*
2 * MPC8315E RDB Device Tree Source
3 *
4 * Copyright 2007 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
12 /dts-v1/;
14 / {
15 compatible = "fsl,mpc8315erdb";
16 #address-cells = <1>;
17 #size-cells = <1>;
19 aliases {
20 ethernet0 = &enet0;
21 ethernet1 = &enet1;
22 serial0 = &serial0;
23 serial1 = &serial1;
24 pci0 = &pci0;
25 };
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
31 PowerPC,8315@0 {
32 device_type = "cpu";
33 reg = <0x0>;
34 d-cache-line-size = <32>;
35 i-cache-line-size = <32>;
36 d-cache-size = <16384>;
37 i-cache-size = <16384>;
38 timebase-frequency = <0>; // from bootloader
39 bus-frequency = <0>; // from bootloader
40 clock-frequency = <0>; // from bootloader
41 };
42 };
44 memory {
45 device_type = "memory";
46 reg = <0x00000000 0x08000000>; // 128MB at 0
47 };
49 localbus@e0005000 {
50 #address-cells = <2>;
51 #size-cells = <1>;
52 compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
53 reg = <0xe0005000 0x1000>;
54 interrupts = <77 0x8>;
55 interrupt-parent = <&ipic>;
57 // CS0 and CS1 are swapped when
58 // booting from nand, but the
59 // addresses are the same.
60 ranges = <0x0 0x0 0xfe000000 0x00800000
61 0x1 0x0 0xe0600000 0x00002000
62 0x2 0x0 0xf0000000 0x00020000
63 0x3 0x0 0xfa000000 0x00008000>;
65 flash@0,0 {
66 #address-cells = <1>;
67 #size-cells = <1>;
68 compatible = "cfi-flash";
69 reg = <0x0 0x0 0x800000>;
70 bank-width = <2>;
71 device-width = <1>;
72 };
74 nand@1,0 {
75 #address-cells = <1>;
76 #size-cells = <1>;
77 compatible = "fsl,mpc8315-fcm-nand",
78 "fsl,elbc-fcm-nand";
79 reg = <0x1 0x0 0x2000>;
81 u-boot@0 {
82 reg = <0x0 0x100000>;
83 read-only;
84 };
86 kernel@100000 {
87 reg = <0x100000 0x300000>;
88 };
89 fs@400000 {
90 reg = <0x400000 0x1c00000>;
91 };
92 };
93 };
95 immr@e0000000 {
96 #address-cells = <1>;
97 #size-cells = <1>;
98 device_type = "soc";
99 compatible = "fsl,mpc8315-immr", "simple-bus";
100 ranges = <0 0xe0000000 0x00100000>;
101 reg = <0xe0000000 0x00000200>;
102 bus-frequency = <0>;
104 wdt@200 {
105 device_type = "watchdog";
106 compatible = "mpc83xx_wdt";
107 reg = <0x200 0x100>;
108 };
110 i2c@3000 {
111 #address-cells = <1>;
112 #size-cells = <0>;
113 cell-index = <0>;
114 compatible = "fsl-i2c";
115 reg = <0x3000 0x100>;
116 interrupts = <14 0x8>;
117 interrupt-parent = <&ipic>;
118 dfsrr;
119 rtc@68 {
120 device_type = "rtc";
121 compatible = "dallas,ds1339";
122 reg = <0x68>;
123 };
125 mcu_pio: mcu@a {
126 #gpio-cells = <2>;
127 compatible = "fsl,mc9s08qg8-mpc8315erdb",
128 "fsl,mcu-mpc8349emitx";
129 reg = <0x0a>;
130 gpio-controller;
131 };
132 };
134 spi@7000 {
135 cell-index = <0>;
136 compatible = "fsl,spi";
137 reg = <0x7000 0x1000>;
138 interrupts = <16 0x8>;
139 interrupt-parent = <&ipic>;
140 mode = "cpu";
141 };
143 dma@82a8 {
144 #address-cells = <1>;
145 #size-cells = <1>;
146 compatible = "fsl,mpc8315-dma", "fsl,elo-dma";
147 reg = <0x82a8 4>;
148 ranges = <0 0x8100 0x1a8>;
149 interrupt-parent = <&ipic>;
150 interrupts = <71 8>;
151 cell-index = <0>;
152 dma-channel@0 {
153 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
154 reg = <0 0x80>;
155 cell-index = <0>;
156 interrupt-parent = <&ipic>;
157 interrupts = <71 8>;
158 };
159 dma-channel@80 {
160 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
161 reg = <0x80 0x80>;
162 cell-index = <1>;
163 interrupt-parent = <&ipic>;
164 interrupts = <71 8>;
165 };
166 dma-channel@100 {
167 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
168 reg = <0x100 0x80>;
169 cell-index = <2>;
170 interrupt-parent = <&ipic>;
171 interrupts = <71 8>;
172 };
173 dma-channel@180 {
174 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
175 reg = <0x180 0x28>;
176 cell-index = <3>;
177 interrupt-parent = <&ipic>;
178 interrupts = <71 8>;
179 };
180 };
182 usb@23000 {
183 compatible = "fsl-usb2-dr";
184 reg = <0x23000 0x1000>;
185 #address-cells = <1>;
186 #size-cells = <0>;
187 interrupt-parent = <&ipic>;
188 interrupts = <38 0x8>;
189 phy_type = "utmi";
190 };
192 mdio@24520 {
193 #address-cells = <1>;
194 #size-cells = <0>;
195 compatible = "fsl,gianfar-mdio";
196 reg = <0x24520 0x20>;
197 phy0: ethernet-phy@0 {
198 interrupt-parent = <&ipic>;
199 interrupts = <20 0x8>;
200 reg = <0x0>;
201 device_type = "ethernet-phy";
202 };
203 phy1: ethernet-phy@1 {
204 interrupt-parent = <&ipic>;
205 interrupts = <19 0x8>;
206 reg = <0x1>;
207 device_type = "ethernet-phy";
208 };
209 };
211 enet0: ethernet@24000 {
212 cell-index = <0>;
213 device_type = "network";
214 model = "eTSEC";
215 compatible = "gianfar";
216 reg = <0x24000 0x1000>;
217 local-mac-address = [ 00 00 00 00 00 00 ];
218 interrupts = <32 0x8 33 0x8 34 0x8>;
219 interrupt-parent = <&ipic>;
220 phy-handle = < &phy0 >;
221 };
223 enet1: ethernet@25000 {
224 cell-index = <1>;
225 device_type = "network";
226 model = "eTSEC";
227 compatible = "gianfar";
228 reg = <0x25000 0x1000>;
229 local-mac-address = [ 00 00 00 00 00 00 ];
230 interrupts = <35 0x8 36 0x8 37 0x8>;
231 interrupt-parent = <&ipic>;
232 phy-handle = < &phy1 >;
233 };
235 serial0: serial@4500 {
236 cell-index = <0>;
237 device_type = "serial";
238 compatible = "ns16550";
239 reg = <0x4500 0x100>;
240 clock-frequency = <0>;
241 interrupts = <9 0x8>;
242 interrupt-parent = <&ipic>;
243 };
245 serial1: serial@4600 {
246 cell-index = <1>;
247 device_type = "serial";
248 compatible = "ns16550";
249 reg = <0x4600 0x100>;
250 clock-frequency = <0>;
251 interrupts = <10 0x8>;
252 interrupt-parent = <&ipic>;
253 };
255 crypto@30000 {
256 compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
257 "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
258 "fsl,sec2.0";
259 reg = <0x30000 0x10000>;
260 interrupts = <11 0x8>;
261 interrupt-parent = <&ipic>;
262 fsl,num-channels = <4>;
263 fsl,channel-fifo-len = <24>;
264 fsl,exec-units-mask = <0x97c>;
265 fsl,descriptor-types-mask = <0x3ab0abf>;
266 };
268 sata@18000 {
269 compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
270 reg = <0x18000 0x1000>;
271 cell-index = <1>;
272 interrupts = <44 0x8>;
273 interrupt-parent = <&ipic>;
274 };
276 sata@19000 {
277 compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
278 reg = <0x19000 0x1000>;
279 cell-index = <2>;
280 interrupts = <45 0x8>;
281 interrupt-parent = <&ipic>;
282 };
284 /* IPIC
285 * interrupts cell = <intr #, sense>
286 * sense values match linux IORESOURCE_IRQ_* defines:
287 * sense == 8: Level, low assertion
288 * sense == 2: Edge, high-to-low change
289 */
290 ipic: interrupt-controller@700 {
291 interrupt-controller;
292 #address-cells = <0>;
293 #interrupt-cells = <2>;
294 reg = <0x700 0x100>;
295 device_type = "ipic";
296 };
297 };
299 pci0: pci@e0008500 {
300 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
301 interrupt-map = <
302 /* IDSEL 0x0E -mini PCI */
303 0x7000 0x0 0x0 0x1 &ipic 18 0x8
304 0x7000 0x0 0x0 0x2 &ipic 18 0x8
305 0x7000 0x0 0x0 0x3 &ipic 18 0x8
306 0x7000 0x0 0x0 0x4 &ipic 18 0x8
308 /* IDSEL 0x0F -mini PCI */
309 0x7800 0x0 0x0 0x1 &ipic 17 0x8
310 0x7800 0x0 0x0 0x2 &ipic 17 0x8
311 0x7800 0x0 0x0 0x3 &ipic 17 0x8
312 0x7800 0x0 0x0 0x4 &ipic 17 0x8
314 /* IDSEL 0x10 - PCI slot */
315 0x8000 0x0 0x0 0x1 &ipic 48 0x8
316 0x8000 0x0 0x0 0x2 &ipic 17 0x8
317 0x8000 0x0 0x0 0x3 &ipic 48 0x8
318 0x8000 0x0 0x0 0x4 &ipic 17 0x8>;
319 interrupt-parent = <&ipic>;
320 interrupts = <66 0x8>;
321 bus-range = <0x0 0x0>;
322 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
323 0x42000000 0 0x80000000 0x80000000 0 0x10000000
324 0x01000000 0 0x00000000 0xe0300000 0 0x00100000>;
325 clock-frequency = <66666666>;
326 #interrupt-cells = <1>;
327 #size-cells = <2>;
328 #address-cells = <3>;
329 reg = <0xe0008500 0x100 /* internal registers */
330 0xe0008300 0x8>; /* config space access registers */
331 compatible = "fsl,mpc8349-pci";
332 device_type = "pci";
333 };
334 };