| blob | d76441ec5dc72f1599ced341d2356062538da9b5 |
1 /*
2 * TQM 8541 Device Tree Source
3 *
4 * Copyright 2008 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
12 /dts-v1/;
14 / {
15 model = "tqc,tqm8541";
16 compatible = "tqc,tqm8541";
17 #address-cells = <1>;
18 #size-cells = <1>;
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 serial0 = &serial0;
24 serial1 = &serial1;
25 pci0 = &pci0;
26 };
28 cpus {
29 #address-cells = <1>;
30 #size-cells = <0>;
32 PowerPC,8541@0 {
33 device_type = "cpu";
34 reg = <0>;
35 d-cache-line-size = <32>;
36 i-cache-line-size = <32>;
37 d-cache-size = <32768>;
38 i-cache-size = <32768>;
39 timebase-frequency = <0>;
40 bus-frequency = <0>;
41 clock-frequency = <0>;
42 next-level-cache = <&L2>;
43 };
44 };
46 memory {
47 device_type = "memory";
48 reg = <0x00000000 0x10000000>;
49 };
51 soc@e0000000 {
52 #address-cells = <1>;
53 #size-cells = <1>;
54 device_type = "soc";
55 ranges = <0x0 0xe0000000 0x100000>;
56 reg = <0xe0000000 0x200>;
57 bus-frequency = <0>;
58 compatible = "fsl,mpc8541-immr", "simple-bus";
60 memory-controller@2000 {
61 compatible = "fsl,8540-memory-controller";
62 reg = <0x2000 0x1000>;
63 interrupt-parent = <&mpic>;
64 interrupts = <18 2>;
65 };
67 L2: l2-cache-controller@20000 {
68 compatible = "fsl,8540-l2-cache-controller";
69 reg = <0x20000 0x1000>;
70 cache-line-size = <32>;
71 cache-size = <0x40000>; // L2, 256K
72 interrupt-parent = <&mpic>;
73 interrupts = <16 2>;
74 };
76 i2c@3000 {
77 #address-cells = <1>;
78 #size-cells = <0>;
79 cell-index = <0>;
80 compatible = "fsl-i2c";
81 reg = <0x3000 0x100>;
82 interrupts = <43 2>;
83 interrupt-parent = <&mpic>;
84 dfsrr;
86 rtc@68 {
87 compatible = "dallas,ds1337";
88 reg = <0x68>;
89 };
90 };
92 dma@21300 {
93 #address-cells = <1>;
94 #size-cells = <1>;
95 compatible = "fsl,mpc8541-dma", "fsl,eloplus-dma";
96 reg = <0x21300 0x4>;
97 ranges = <0x0 0x21100 0x200>;
98 cell-index = <0>;
99 dma-channel@0 {
100 compatible = "fsl,mpc8541-dma-channel",
101 "fsl,eloplus-dma-channel";
102 reg = <0x0 0x80>;
103 cell-index = <0>;
104 interrupt-parent = <&mpic>;
105 interrupts = <20 2>;
106 };
107 dma-channel@80 {
108 compatible = "fsl,mpc8541-dma-channel",
109 "fsl,eloplus-dma-channel";
110 reg = <0x80 0x80>;
111 cell-index = <1>;
112 interrupt-parent = <&mpic>;
113 interrupts = <21 2>;
114 };
115 dma-channel@100 {
116 compatible = "fsl,mpc8541-dma-channel",
117 "fsl,eloplus-dma-channel";
118 reg = <0x100 0x80>;
119 cell-index = <2>;
120 interrupt-parent = <&mpic>;
121 interrupts = <22 2>;
122 };
123 dma-channel@180 {
124 compatible = "fsl,mpc8541-dma-channel",
125 "fsl,eloplus-dma-channel";
126 reg = <0x180 0x80>;
127 cell-index = <3>;
128 interrupt-parent = <&mpic>;
129 interrupts = <23 2>;
130 };
131 };
133 mdio@24520 {
134 #address-cells = <1>;
135 #size-cells = <0>;
136 compatible = "fsl,gianfar-mdio";
137 reg = <0x24520 0x20>;
139 phy1: ethernet-phy@1 {
140 interrupt-parent = <&mpic>;
141 interrupts = <8 1>;
142 reg = <1>;
143 device_type = "ethernet-phy";
144 };
145 phy2: ethernet-phy@2 {
146 interrupt-parent = <&mpic>;
147 interrupts = <8 1>;
148 reg = <2>;
149 device_type = "ethernet-phy";
150 };
151 phy3: ethernet-phy@3 {
152 interrupt-parent = <&mpic>;
153 interrupts = <8 1>;
154 reg = <3>;
155 device_type = "ethernet-phy";
156 };
157 };
159 enet0: ethernet@24000 {
160 cell-index = <0>;
161 device_type = "network";
162 model = "TSEC";
163 compatible = "gianfar";
164 reg = <0x24000 0x1000>;
165 local-mac-address = [ 00 00 00 00 00 00 ];
166 interrupts = <29 2 30 2 34 2>;
167 interrupt-parent = <&mpic>;
168 phy-handle = <&phy2>;
169 };
171 enet1: ethernet@25000 {
172 cell-index = <1>;
173 device_type = "network";
174 model = "TSEC";
175 compatible = "gianfar";
176 reg = <0x25000 0x1000>;
177 local-mac-address = [ 00 00 00 00 00 00 ];
178 interrupts = <35 2 36 2 40 2>;
179 interrupt-parent = <&mpic>;
180 phy-handle = <&phy1>;
181 };
183 serial0: serial@4500 {
184 cell-index = <0>;
185 device_type = "serial";
186 compatible = "ns16550";
187 reg = <0x4500 0x100>; // reg base, size
188 clock-frequency = <0>; // should we fill in in uboot?
189 interrupts = <42 2>;
190 interrupt-parent = <&mpic>;
191 };
193 serial1: serial@4600 {
194 cell-index = <1>;
195 device_type = "serial";
196 compatible = "ns16550";
197 reg = <0x4600 0x100>; // reg base, size
198 clock-frequency = <0>; // should we fill in in uboot?
199 interrupts = <42 2>;
200 interrupt-parent = <&mpic>;
201 };
203 crypto@30000 {
204 compatible = "fsl,sec2.0";
205 reg = <0x30000 0x10000>;
206 interrupts = <45 2>;
207 interrupt-parent = <&mpic>;
208 fsl,num-channels = <4>;
209 fsl,channel-fifo-len = <24>;
210 fsl,exec-units-mask = <0x7e>;
211 fsl,descriptor-types-mask = <0x01010ebf>;
212 };
214 mpic: pic@40000 {
215 interrupt-controller;
216 #address-cells = <0>;
217 #interrupt-cells = <2>;
218 reg = <0x40000 0x40000>;
219 device_type = "open-pic";
220 compatible = "chrp,open-pic";
221 };
223 cpm@919c0 {
224 #address-cells = <1>;
225 #size-cells = <1>;
226 compatible = "fsl,mpc8541-cpm", "fsl,cpm2", "simple-bus";
227 reg = <0x919c0 0x30>;
228 ranges;
230 muram@80000 {
231 #address-cells = <1>;
232 #size-cells = <1>;
233 ranges = <0 0x80000 0x10000>;
235 data@0 {
236 compatible = "fsl,cpm-muram-data";
237 reg = <0 0x2000 0x9000 0x1000>;
238 };
239 };
241 brg@919f0 {
242 compatible = "fsl,mpc8541-brg",
243 "fsl,cpm2-brg",
244 "fsl,cpm-brg";
245 reg = <0x919f0 0x10 0x915f0 0x10>;
246 clock-frequency = <0>;
247 };
249 cpmpic: pic@90c00 {
250 interrupt-controller;
251 #address-cells = <0>;
252 #interrupt-cells = <2>;
253 interrupts = <46 2>;
254 interrupt-parent = <&mpic>;
255 reg = <0x90c00 0x80>;
256 compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic";
257 };
258 };
259 };
261 pci0: pci@e0008000 {
262 cell-index = <0>;
263 #interrupt-cells = <1>;
264 #size-cells = <2>;
265 #address-cells = <3>;
266 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
267 device_type = "pci";
268 reg = <0xe0008000 0x1000>;
269 clock-frequency = <66666666>;
270 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
271 interrupt-map = <
272 /* IDSEL 28 */
273 0xe000 0 0 1 &mpic 2 1
274 0xe000 0 0 2 &mpic 3 1>;
276 interrupt-parent = <&mpic>;
277 interrupts = <24 2>;
278 bus-range = <0 0>;
279 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
280 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>;
281 };
282 };