| blob | 58ee4185454b233f32f3bca4195303d7ddd5e20f |
1 /*
2 * TQM8548 Device Tree Source
3 *
4 * Copyright 2006 Freescale Semiconductor Inc.
5 * Copyright 2008 Wolfgang Grandegger <wg@denx.de>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
13 /dts-v1/;
15 / {
16 model = "tqc,tqm8548";
17 compatible = "tqc,tqm8548";
18 #address-cells = <1>;
19 #size-cells = <1>;
21 aliases {
22 ethernet0 = &enet0;
23 ethernet1 = &enet1;
24 ethernet2 = &enet2;
25 ethernet3 = &enet3;
27 serial0 = &serial0;
28 serial1 = &serial1;
29 pci0 = &pci0;
30 pci1 = &pci1;
31 };
33 cpus {
34 #address-cells = <1>;
35 #size-cells = <0>;
37 PowerPC,8548@0 {
38 device_type = "cpu";
39 reg = <0>;
40 d-cache-line-size = <32>; // 32 bytes
41 i-cache-line-size = <32>; // 32 bytes
42 d-cache-size = <0x8000>; // L1, 32K
43 i-cache-size = <0x8000>; // L1, 32K
44 next-level-cache = <&L2>;
45 };
46 };
48 memory {
49 device_type = "memory";
50 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
51 };
53 soc@e0000000 {
54 #address-cells = <1>;
55 #size-cells = <1>;
56 device_type = "soc";
57 ranges = <0x0 0xe0000000 0x100000>;
58 reg = <0xe0000000 0x1000>; // CCSRBAR
59 bus-frequency = <0>;
60 compatible = "fsl,mpc8548-immr", "simple-bus";
62 memory-controller@2000 {
63 compatible = "fsl,mpc8548-memory-controller";
64 reg = <0x2000 0x1000>;
65 interrupt-parent = <&mpic>;
66 interrupts = <18 2>;
67 };
69 L2: l2-cache-controller@20000 {
70 compatible = "fsl,mpc8548-l2-cache-controller";
71 reg = <0x20000 0x1000>;
72 cache-line-size = <32>; // 32 bytes
73 cache-size = <0x80000>; // L2, 512K
74 interrupt-parent = <&mpic>;
75 interrupts = <16 2>;
76 };
78 i2c@3000 {
79 #address-cells = <1>;
80 #size-cells = <0>;
81 cell-index = <0>;
82 compatible = "fsl-i2c";
83 reg = <0x3000 0x100>;
84 interrupts = <43 2>;
85 interrupt-parent = <&mpic>;
86 dfsrr;
88 rtc@68 {
89 compatible = "dallas,ds1337";
90 reg = <0x68>;
91 };
92 };
94 i2c@3100 {
95 #address-cells = <1>;
96 #size-cells = <0>;
97 cell-index = <1>;
98 compatible = "fsl-i2c";
99 reg = <0x3100 0x100>;
100 interrupts = <43 2>;
101 interrupt-parent = <&mpic>;
102 dfsrr;
103 };
105 dma@21300 {
106 #address-cells = <1>;
107 #size-cells = <1>;
108 compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
109 reg = <0x21300 0x4>;
110 ranges = <0x0 0x21100 0x200>;
111 cell-index = <0>;
112 dma-channel@0 {
113 compatible = "fsl,mpc8548-dma-channel",
114 "fsl,eloplus-dma-channel";
115 reg = <0x0 0x80>;
116 cell-index = <0>;
117 interrupt-parent = <&mpic>;
118 interrupts = <20 2>;
119 };
120 dma-channel@80 {
121 compatible = "fsl,mpc8548-dma-channel",
122 "fsl,eloplus-dma-channel";
123 reg = <0x80 0x80>;
124 cell-index = <1>;
125 interrupt-parent = <&mpic>;
126 interrupts = <21 2>;
127 };
128 dma-channel@100 {
129 compatible = "fsl,mpc8548-dma-channel",
130 "fsl,eloplus-dma-channel";
131 reg = <0x100 0x80>;
132 cell-index = <2>;
133 interrupt-parent = <&mpic>;
134 interrupts = <22 2>;
135 };
136 dma-channel@180 {
137 compatible = "fsl,mpc8548-dma-channel",
138 "fsl,eloplus-dma-channel";
139 reg = <0x180 0x80>;
140 cell-index = <3>;
141 interrupt-parent = <&mpic>;
142 interrupts = <23 2>;
143 };
144 };
146 mdio@24520 {
147 #address-cells = <1>;
148 #size-cells = <0>;
149 compatible = "fsl,gianfar-mdio";
150 reg = <0x24520 0x20>;
152 phy1: ethernet-phy@0 {
153 interrupt-parent = <&mpic>;
154 interrupts = <8 1>;
155 reg = <1>;
156 device_type = "ethernet-phy";
157 };
158 phy2: ethernet-phy@1 {
159 interrupt-parent = <&mpic>;
160 interrupts = <8 1>;
161 reg = <2>;
162 device_type = "ethernet-phy";
163 };
164 phy3: ethernet-phy@3 {
165 interrupt-parent = <&mpic>;
166 interrupts = <8 1>;
167 reg = <3>;
168 device_type = "ethernet-phy";
169 };
170 phy4: ethernet-phy@4 {
171 interrupt-parent = <&mpic>;
172 interrupts = <8 1>;
173 reg = <4>;
174 device_type = "ethernet-phy";
175 };
176 phy5: ethernet-phy@5 {
177 interrupt-parent = <&mpic>;
178 interrupts = <8 1>;
179 reg = <5>;
180 device_type = "ethernet-phy";
181 };
182 };
184 enet0: ethernet@24000 {
185 cell-index = <0>;
186 device_type = "network";
187 model = "eTSEC";
188 compatible = "gianfar";
189 reg = <0x24000 0x1000>;
190 local-mac-address = [ 00 00 00 00 00 00 ];
191 interrupts = <29 2 30 2 34 2>;
192 interrupt-parent = <&mpic>;
193 phy-handle = <&phy2>;
194 };
196 enet1: ethernet@25000 {
197 cell-index = <1>;
198 device_type = "network";
199 model = "eTSEC";
200 compatible = "gianfar";
201 reg = <0x25000 0x1000>;
202 local-mac-address = [ 00 00 00 00 00 00 ];
203 interrupts = <35 2 36 2 40 2>;
204 interrupt-parent = <&mpic>;
205 phy-handle = <&phy1>;
206 };
208 enet2: ethernet@26000 {
209 cell-index = <2>;
210 device_type = "network";
211 model = "eTSEC";
212 compatible = "gianfar";
213 reg = <0x26000 0x1000>;
214 local-mac-address = [ 00 00 00 00 00 00 ];
215 interrupts = <31 2 32 2 33 2>;
216 interrupt-parent = <&mpic>;
217 phy-handle = <&phy3>;
218 };
220 enet3: ethernet@27000 {
221 cell-index = <3>;
222 device_type = "network";
223 model = "eTSEC";
224 compatible = "gianfar";
225 reg = <0x27000 0x1000>;
226 local-mac-address = [ 00 00 00 00 00 00 ];
227 interrupts = <37 2 38 2 39 2>;
228 interrupt-parent = <&mpic>;
229 phy-handle = <&phy4>;
230 };
232 serial0: serial@4500 {
233 cell-index = <0>;
234 device_type = "serial";
235 compatible = "ns16550";
236 reg = <0x4500 0x100>; // reg base, size
237 clock-frequency = <0>; // should we fill in in uboot?
238 current-speed = <115200>;
239 interrupts = <42 2>;
240 interrupt-parent = <&mpic>;
241 };
243 serial1: serial@4600 {
244 cell-index = <1>;
245 device_type = "serial";
246 compatible = "ns16550";
247 reg = <0x4600 0x100>; // reg base, size
248 clock-frequency = <0>; // should we fill in in uboot?
249 current-speed = <115200>;
250 interrupts = <42 2>;
251 interrupt-parent = <&mpic>;
252 };
254 global-utilities@e0000 { // global utilities reg
255 compatible = "fsl,mpc8548-guts";
256 reg = <0xe0000 0x1000>;
257 fsl,has-rstcr;
258 };
260 mpic: pic@40000 {
261 interrupt-controller;
262 #address-cells = <0>;
263 #interrupt-cells = <2>;
264 reg = <0x40000 0x40000>;
265 compatible = "chrp,open-pic";
266 device_type = "open-pic";
267 };
268 };
270 localbus@e0005000 {
271 compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus",
272 "simple-bus";
273 #address-cells = <2>;
274 #size-cells = <1>;
275 reg = <0xe0005000 0x100>; // BRx, ORx, etc.
277 ranges = <
278 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1
279 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0
280 2 0x0 0xe3000000 0x00008000 // CAN (2 x i82527)
281 3 0x0 0xe3010000 0x00008000 // NAND FLASH
283 >;
285 flash@1,0 {
286 #address-cells = <1>;
287 #size-cells = <1>;
288 compatible = "cfi-flash";
289 reg = <1 0x0 0x8000000>;
290 bank-width = <4>;
291 device-width = <1>;
293 partition@0 {
294 label = "kernel";
295 reg = <0x00000000 0x00200000>;
296 };
297 partition@200000 {
298 label = "root";
299 reg = <0x00200000 0x00300000>;
300 };
301 partition@500000 {
302 label = "user";
303 reg = <0x00500000 0x07a00000>;
304 };
305 partition@7f00000 {
306 label = "env1";
307 reg = <0x07f00000 0x00040000>;
308 };
309 partition@7f40000 {
310 label = "env2";
311 reg = <0x07f40000 0x00040000>;
312 };
313 partition@7f80000 {
314 label = "u-boot";
315 reg = <0x07f80000 0x00080000>;
316 read-only;
317 };
318 };
320 /* Note: CAN support needs be enabled in U-Boot */
321 can0@2,0 {
322 compatible = "intel,82527"; // Bosch CC770
323 reg = <2 0x0 0x100>;
324 interrupts = <4 0>;
325 interrupt-parent = <&mpic>;
326 };
328 can1@2,100 {
329 compatible = "intel,82527"; // Bosch CC770
330 reg = <2 0x100 0x100>;
331 interrupts = <4 0>;
332 interrupt-parent = <&mpic>;
333 };
335 /* Note: NAND support needs to be enabled in U-Boot */
336 upm@3,0 {
337 #address-cells = <0>;
338 #size-cells = <0>;
339 compatible = "fsl,upm-nand";
340 reg = <3 0x0 0x800>;
341 fsl,upm-addr-offset = <0x10>;
342 fsl,upm-cmd-offset = <0x08>;
343 chip-delay = <25>; // in micro-seconds
345 nand@0 {
346 #address-cells = <1>;
347 #size-cells = <1>;
349 partition@0 {
350 label = "fs";
351 reg = <0x00000000 0x01000000>;
352 };
353 };
354 };
355 };
357 pci0: pci@e0008000 {
358 cell-index = <0>;
359 #interrupt-cells = <1>;
360 #size-cells = <2>;
361 #address-cells = <3>;
362 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
363 device_type = "pci";
364 reg = <0xe0008000 0x1000>;
365 clock-frequency = <33333333>;
366 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
367 interrupt-map = <
368 /* IDSEL 28 */
369 0xe000 0 0 1 &mpic 2 1
370 0xe000 0 0 2 &mpic 3 1>;
372 interrupt-parent = <&mpic>;
373 interrupts = <24 2>;
374 bus-range = <0 0>;
375 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
376 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>;
377 };
379 pci1: pcie@e000a000 {
380 cell-index = <2>;
381 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
382 interrupt-map = <
383 /* IDSEL 0x0 (PEX) */
384 0x00000 0 0 1 &mpic 0 1
385 0x00000 0 0 2 &mpic 1 1
386 0x00000 0 0 3 &mpic 2 1
387 0x00000 0 0 4 &mpic 3 1>;
389 interrupt-parent = <&mpic>;
390 interrupts = <26 2>;
391 bus-range = <0 0xff>;
392 ranges = <0x02000000 0 0xc0000000 0xc0000000 0 0x20000000
393 0x01000000 0 0x00000000 0xef000000 0 0x08000000>;
394 clock-frequency = <33333333>;
395 #interrupt-cells = <1>;
396 #size-cells = <2>;
397 #address-cells = <3>;
398 reg = <0xe000a000 0x1000>;
399 compatible = "fsl,mpc8548-pcie";
400 device_type = "pci";
401 pcie@0 {
402 reg = <0 0 0 0 0>;
403 #size-cells = <2>;
404 #address-cells = <3>;
405 device_type = "pci";
406 ranges = <0x02000000 0 0xc0000000 0x02000000 0
407 0xc0000000 0 0x20000000
408 0x01000000 0 0x00000000 0x01000000 0
409 0x00000000 0 0x08000000>;
410 };
411 };
412 };