4 * Copyright (C) 2006 Yoshinori Sato
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
13 #include <linux/serial_sci.h>
18 /* interrupt sources */
19 IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, IRQ6
, IRQ7
,
20 PINT0
, PINT1
, PINT2
, PINT3
, PINT4
, PINT5
, PINT6
, PINT7
,
22 DMAC0_DEI
, DMAC0_HEI
, DMAC1_DEI
, DMAC1_HEI
,
23 DMAC2_DEI
, DMAC2_HEI
, DMAC3_DEI
, DMAC3_HEI
,
24 DMAC4_DEI
, DMAC4_HEI
, DMAC5_DEI
, DMAC5_HEI
,
25 DMAC6_DEI
, DMAC6_HEI
, DMAC7_DEI
, DMAC7_HEI
,
27 MTU2_TGI0A
, MTU2_TGI0B
, MTU2_TGI0C
, MTU2_TGI0D
,
28 MTU2_TCI0V
, MTU2_TGI0E
, MTU2_TGI0F
,
29 MTU2_TGI1A
, MTU2_TGI1B
, MTU2_TCI1V
, MTU2_TCI1U
,
30 MTU2_TGI2A
, MTU2_TGI2B
, MTU2_TCI2V
, MTU2_TCI2U
,
31 MTU2_TGI3A
, MTU2_TGI3B
, MTU2_TGI3C
, MTU2_TGI3D
, MTU2_TCI3V
,
32 MTU2_TGI4A
, MTU2_TGI4B
, MTU2_TGI4C
, MTU2_TGI4D
, MTU2_TCI4V
,
33 MTU2_TGI5U
, MTU2_TGI5V
, MTU2_TGI5W
,
35 MTU2S_TGI3A
, MTU2S_TGI3B
, MTU2S_TGI3C
, MTU2S_TGI3D
, MTU2S_TCI3V
,
36 MTU2S_TGI4A
, MTU2S_TGI4B
, MTU2S_TGI4C
, MTU2S_TGI4D
, MTU2S_TCI4V
,
37 MTU2S_TGI5U
, MTU2S_TGI5V
, MTU2S_TGI5W
,
39 IIC3_STPI
, IIC3_NAKI
, IIC3_RXI
, IIC3_TXI
, IIC3_TEI
,
40 SCIF0_BRI
, SCIF0_ERI
, SCIF0_RXI
, SCIF0_TXI
,
41 SCIF1_BRI
, SCIF1_ERI
, SCIF1_RXI
, SCIF1_TXI
,
42 SCIF2_BRI
, SCIF2_ERI
, SCIF2_RXI
, SCIF2_TXI
,
43 SCIF3_BRI
, SCIF3_ERI
, SCIF3_RXI
, SCIF3_TXI
,
45 /* interrupt groups */
46 PINT
, DMAC0
, DMAC1
, DMAC2
, DMAC3
, DMAC4
, DMAC5
, DMAC6
, DMAC7
,
47 MTU0_ABCD
, MTU0_VEF
, MTU1_AB
, MTU1_VU
, MTU2_AB
, MTU2_VU
,
48 MTU3_ABCD
, MTU4_ABCD
, MTU5
, POE2_12
, MTU3S_ABCD
, MTU4S_ABCD
, MTU5S
,
49 IIC3
, SCIF0
, SCIF1
, SCIF2
, SCIF3
,
52 static struct intc_vect vectors
[] __initdata
= {
53 INTC_IRQ(IRQ0
, 64), INTC_IRQ(IRQ1
, 65),
54 INTC_IRQ(IRQ2
, 66), INTC_IRQ(IRQ3
, 67),
55 INTC_IRQ(IRQ4
, 68), INTC_IRQ(IRQ5
, 69),
56 INTC_IRQ(IRQ6
, 70), INTC_IRQ(IRQ7
, 71),
57 INTC_IRQ(PINT0
, 80), INTC_IRQ(PINT1
, 81),
58 INTC_IRQ(PINT2
, 82), INTC_IRQ(PINT3
, 83),
59 INTC_IRQ(PINT4
, 84), INTC_IRQ(PINT5
, 85),
60 INTC_IRQ(PINT6
, 86), INTC_IRQ(PINT7
, 87),
61 INTC_IRQ(ADC_ADI0
, 92), INTC_IRQ(ADC_ADI1
, 96),
62 INTC_IRQ(DMAC0_DEI
, 108), INTC_IRQ(DMAC0_HEI
, 109),
63 INTC_IRQ(DMAC1_DEI
, 112), INTC_IRQ(DMAC1_HEI
, 113),
64 INTC_IRQ(DMAC2_DEI
, 116), INTC_IRQ(DMAC2_HEI
, 117),
65 INTC_IRQ(DMAC3_DEI
, 120), INTC_IRQ(DMAC3_HEI
, 121),
66 INTC_IRQ(DMAC4_DEI
, 124), INTC_IRQ(DMAC4_HEI
, 125),
67 INTC_IRQ(DMAC5_DEI
, 128), INTC_IRQ(DMAC5_HEI
, 129),
68 INTC_IRQ(DMAC6_DEI
, 132), INTC_IRQ(DMAC6_HEI
, 133),
69 INTC_IRQ(DMAC7_DEI
, 136), INTC_IRQ(DMAC7_HEI
, 137),
70 INTC_IRQ(CMT0
, 140), INTC_IRQ(CMT1
, 144),
71 INTC_IRQ(BSC
, 148), INTC_IRQ(WDT
, 152),
72 INTC_IRQ(MTU2_TGI0A
, 156), INTC_IRQ(MTU2_TGI0B
, 157),
73 INTC_IRQ(MTU2_TGI0C
, 158), INTC_IRQ(MTU2_TGI0D
, 159),
74 INTC_IRQ(MTU2_TCI0V
, 160),
75 INTC_IRQ(MTU2_TGI0E
, 161), INTC_IRQ(MTU2_TGI0F
, 162),
76 INTC_IRQ(MTU2_TGI1A
, 164), INTC_IRQ(MTU2_TGI1B
, 165),
77 INTC_IRQ(MTU2_TCI1V
, 168), INTC_IRQ(MTU2_TCI1U
, 169),
78 INTC_IRQ(MTU2_TGI2A
, 172), INTC_IRQ(MTU2_TGI2B
, 173),
79 INTC_IRQ(MTU2_TCI2V
, 176), INTC_IRQ(MTU2_TCI2U
, 177),
80 INTC_IRQ(MTU2_TGI3A
, 180), INTC_IRQ(MTU2_TGI3B
, 181),
81 INTC_IRQ(MTU2_TGI3C
, 182), INTC_IRQ(MTU2_TGI3D
, 183),
82 INTC_IRQ(MTU2_TCI3V
, 184),
83 INTC_IRQ(MTU2_TGI4A
, 188), INTC_IRQ(MTU2_TGI4B
, 189),
84 INTC_IRQ(MTU2_TGI4C
, 190), INTC_IRQ(MTU2_TGI4D
, 191),
85 INTC_IRQ(MTU2_TCI4V
, 192),
86 INTC_IRQ(MTU2_TGI5U
, 196), INTC_IRQ(MTU2_TGI5V
, 197),
87 INTC_IRQ(MTU2_TGI5W
, 198),
88 INTC_IRQ(POE2_OEI1
, 200), INTC_IRQ(POE2_OEI2
, 201),
89 INTC_IRQ(MTU2S_TGI3A
, 204), INTC_IRQ(MTU2S_TGI3B
, 205),
90 INTC_IRQ(MTU2S_TGI3C
, 206), INTC_IRQ(MTU2S_TGI3D
, 207),
91 INTC_IRQ(MTU2S_TCI3V
, 208),
92 INTC_IRQ(MTU2S_TGI4A
, 212), INTC_IRQ(MTU2S_TGI4B
, 213),
93 INTC_IRQ(MTU2S_TGI4C
, 214), INTC_IRQ(MTU2S_TGI4D
, 215),
94 INTC_IRQ(MTU2S_TCI4V
, 216),
95 INTC_IRQ(MTU2S_TGI5U
, 220), INTC_IRQ(MTU2S_TGI5V
, 221),
96 INTC_IRQ(MTU2S_TGI5W
, 222),
97 INTC_IRQ(POE2_OEI3
, 224),
98 INTC_IRQ(IIC3_STPI
, 228), INTC_IRQ(IIC3_NAKI
, 229),
99 INTC_IRQ(IIC3_RXI
, 230), INTC_IRQ(IIC3_TXI
, 231),
100 INTC_IRQ(IIC3_TEI
, 232),
101 INTC_IRQ(SCIF0_BRI
, 240), INTC_IRQ(SCIF0_ERI
, 241),
102 INTC_IRQ(SCIF0_RXI
, 242), INTC_IRQ(SCIF0_TXI
, 243),
103 INTC_IRQ(SCIF1_BRI
, 244), INTC_IRQ(SCIF1_ERI
, 245),
104 INTC_IRQ(SCIF1_RXI
, 246), INTC_IRQ(SCIF1_TXI
, 247),
105 INTC_IRQ(SCIF2_BRI
, 248), INTC_IRQ(SCIF2_ERI
, 249),
106 INTC_IRQ(SCIF2_RXI
, 250), INTC_IRQ(SCIF2_TXI
, 251),
107 INTC_IRQ(SCIF3_BRI
, 252), INTC_IRQ(SCIF3_ERI
, 253),
108 INTC_IRQ(SCIF3_RXI
, 254), INTC_IRQ(SCIF3_TXI
, 255),
111 static struct intc_group groups
[] __initdata
= {
112 INTC_GROUP(PINT
, PINT0
, PINT1
, PINT2
, PINT3
,
113 PINT4
, PINT5
, PINT6
, PINT7
),
114 INTC_GROUP(DMAC0
, DMAC0_DEI
, DMAC0_HEI
),
115 INTC_GROUP(DMAC1
, DMAC1_DEI
, DMAC1_HEI
),
116 INTC_GROUP(DMAC2
, DMAC2_DEI
, DMAC2_HEI
),
117 INTC_GROUP(DMAC3
, DMAC3_DEI
, DMAC3_HEI
),
118 INTC_GROUP(DMAC4
, DMAC4_DEI
, DMAC4_HEI
),
119 INTC_GROUP(DMAC5
, DMAC5_DEI
, DMAC5_HEI
),
120 INTC_GROUP(DMAC6
, DMAC6_DEI
, DMAC6_HEI
),
121 INTC_GROUP(DMAC7
, DMAC7_DEI
, DMAC7_HEI
),
122 INTC_GROUP(MTU0_ABCD
, MTU2_TGI0A
, MTU2_TGI0B
, MTU2_TGI0C
, MTU2_TGI0D
),
123 INTC_GROUP(MTU0_VEF
, MTU2_TCI0V
, MTU2_TGI0E
, MTU2_TGI0F
),
124 INTC_GROUP(MTU1_AB
, MTU2_TGI1A
, MTU2_TGI1B
),
125 INTC_GROUP(MTU1_VU
, MTU2_TCI1V
, MTU2_TCI1U
),
126 INTC_GROUP(MTU2_AB
, MTU2_TGI2A
, MTU2_TGI2B
),
127 INTC_GROUP(MTU2_VU
, MTU2_TCI2V
, MTU2_TCI2U
),
128 INTC_GROUP(MTU3_ABCD
, MTU2_TGI3A
, MTU2_TGI3B
, MTU2_TGI3C
, MTU2_TGI3D
),
129 INTC_GROUP(MTU4_ABCD
, MTU2_TGI4A
, MTU2_TGI4B
, MTU2_TGI4C
, MTU2_TGI4D
),
130 INTC_GROUP(MTU5
, MTU2_TGI5U
, MTU2_TGI5V
, MTU2_TGI5W
),
131 INTC_GROUP(POE2_12
, POE2_OEI1
, POE2_OEI2
),
132 INTC_GROUP(MTU3S_ABCD
, MTU2S_TGI3A
, MTU2S_TGI3B
,
133 MTU2S_TGI3C
, MTU2S_TGI3D
),
134 INTC_GROUP(MTU4S_ABCD
, MTU2S_TGI4A
, MTU2S_TGI4B
,
135 MTU2S_TGI4C
, MTU2S_TGI4D
),
136 INTC_GROUP(MTU5S
, MTU2S_TGI5U
, MTU2S_TGI5V
, MTU2S_TGI5W
),
137 INTC_GROUP(IIC3
, IIC3_STPI
, IIC3_NAKI
, IIC3_RXI
, IIC3_TXI
, IIC3_TEI
),
138 INTC_GROUP(SCIF0
, SCIF0_BRI
, SCIF0_ERI
, SCIF0_RXI
, SCIF0_TXI
),
139 INTC_GROUP(SCIF1
, SCIF1_BRI
, SCIF1_ERI
, SCIF1_RXI
, SCIF1_TXI
),
140 INTC_GROUP(SCIF2
, SCIF2_BRI
, SCIF2_ERI
, SCIF2_RXI
, SCIF2_TXI
),
141 INTC_GROUP(SCIF3
, SCIF3_BRI
, SCIF3_ERI
, SCIF3_RXI
, SCIF3_TXI
),
144 static struct intc_prio_reg prio_registers
[] __initdata
= {
145 { 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0
, IRQ1
, IRQ2
, IRQ3
} },
146 { 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4
, IRQ5
, IRQ6
, IRQ7
} },
147 { 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT
, 0, ADC_ADI0
, ADC_ADI1
} },
148 { 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0
, DMAC1
, DMAC2
, DMAC3
} },
149 { 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4
, DMAC5
, DMAC6
, DMAC7
} },
150 { 0xfffe0c04, 0, 16, 4, /* IPR08 */ { CMT0
, CMT1
, BSC
, WDT
} },
151 { 0xfffe0c06, 0, 16, 4, /* IPR09 */ { MTU0_ABCD
, MTU0_VEF
,
152 MTU1_AB
, MTU1_VU
} },
153 { 0xfffe0c08, 0, 16, 4, /* IPR10 */ { MTU2_AB
, MTU2_VU
,
154 MTU3_ABCD
, MTU2_TCI3V
} },
155 { 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { MTU4_ABCD
, MTU2_TCI4V
,
157 { 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { MTU3S_ABCD
, MTU2S_TCI3V
,
158 MTU4S_ABCD
, MTU2S_TCI4V
} },
159 { 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { MTU5S
, POE2_OEI3
, IIC3
, 0 } },
160 { 0xfffe0c10, 0, 16, 4, /* IPR14 */ { SCIF0
, SCIF1
, SCIF2
, SCIF3
} },
163 static struct intc_mask_reg mask_registers
[] __initdata
= {
164 { 0xfffe0808, 0, 16, /* PINTER */
165 { 0, 0, 0, 0, 0, 0, 0, 0,
166 PINT7
, PINT6
, PINT5
, PINT4
, PINT3
, PINT2
, PINT1
, PINT0
} },
169 static DECLARE_INTC_DESC(intc_desc
, "sh7206", vectors
, groups
,
170 mask_registers
, prio_registers
, NULL
);
172 static struct plat_sci_port sci_platform_data
[] = {
174 .mapbase
= 0xfffe8000,
175 .flags
= UPF_BOOT_AUTOCONF
,
177 .irqs
= { 241, 242, 243, 240 },
179 .mapbase
= 0xfffe8800,
180 .flags
= UPF_BOOT_AUTOCONF
,
182 .irqs
= { 245, 246, 247, 244 },
184 .mapbase
= 0xfffe9000,
185 .flags
= UPF_BOOT_AUTOCONF
,
187 .irqs
= { 249, 250, 251, 248 },
189 .mapbase
= 0xfffe9800,
190 .flags
= UPF_BOOT_AUTOCONF
,
192 .irqs
= { 253, 254, 255, 252 },
198 static struct platform_device sci_device
= {
202 .platform_data
= sci_platform_data
,
206 static struct platform_device
*sh7206_devices
[] __initdata
= {
210 static int __init
sh7206_devices_setup(void)
212 return platform_add_devices(sh7206_devices
,
213 ARRAY_SIZE(sh7206_devices
));
215 __initcall(sh7206_devices_setup
);
217 void __init
plat_irq_setup(void)
219 register_intc_controller(&intc_desc
);