| blob | 7aaf88a3b7aabb7a8a7268d435eda8aa78bd7671 |
1 /*
2 * linux/arch/arm/mm/proc-v7.S
3 *
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This is the "shell" of the ARMv7 processor support.
11 */
12 #include <linux/init.h>
13 #include <linux/linkage.h>
14 #include <asm/assembler.h>
15 #include <asm/asm-offsets.h>
16 #include <asm/hwcap.h>
17 #include <asm/pgtable-hwdef.h>
18 #include <asm/pgtable.h>
20 #include "proc-macros.S"
22 #define TTB_S (1 << 1)
23 #define TTB_RGN_NC (0 << 3)
24 #define TTB_RGN_OC_WBWA (1 << 3)
25 #define TTB_RGN_OC_WT (2 << 3)
26 #define TTB_RGN_OC_WB (3 << 3)
27 #define TTB_NOS (1 << 5)
28 #define TTB_IRGN_NC ((0 << 0) | (0 << 6))
29 #define TTB_IRGN_WBWA ((0 << 0) | (1 << 6))
30 #define TTB_IRGN_WT ((1 << 0) | (0 << 6))
31 #define TTB_IRGN_WB ((1 << 0) | (1 << 6))
33 #ifndef CONFIG_SMP
34 /* PTWs cacheable, inner WB not shareable, outer WB not shareable */
35 #define TTB_FLAGS TTB_IRGN_WB|TTB_RGN_OC_WB
36 #define PMD_FLAGS PMD_SECT_WB
37 #else
38 /* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
39 #define TTB_FLAGS TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
40 #define PMD_FLAGS PMD_SECT_WBWA|PMD_SECT_S
41 #endif
43 ENTRY(cpu_v7_proc_init)
44 mov pc, lr
45 ENDPROC(cpu_v7_proc_init)
47 ENTRY(cpu_v7_proc_fin)
48 stmfd sp!, {lr}
49 cpsid if @ disable interrupts
50 bl v7_flush_kern_cache_all
51 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
52 bic r0, r0, #0x1000 @ ...i............
53 bic r0, r0, #0x0006 @ .............ca.
54 mcr p15, 0, r0, c1, c0, 0 @ disable caches
55 ldmfd sp!, {pc}
56 ENDPROC(cpu_v7_proc_fin)
58 /*
59 * cpu_v7_reset(loc)
60 *
61 * Perform a soft reset of the system. Put the CPU into the
62 * same state as it would be if it had been reset, and branch
63 * to what would be the reset vector.
64 *
65 * - loc - location to jump to for soft reset
66 */
67 .align 5
68 ENTRY(cpu_v7_reset)
69 mov pc, r0
70 ENDPROC(cpu_v7_reset)
72 /*
73 * cpu_v7_do_idle()
74 *
75 * Idle the processor (eg, wait for interrupt).
76 *
77 * IRQs are already disabled.
78 */
79 ENTRY(cpu_v7_do_idle)
80 dsb @ WFI may enter a low-power mode
81 wfi
82 mov pc, lr
83 ENDPROC(cpu_v7_do_idle)
85 ENTRY(cpu_v7_dcache_clean_area)
86 #ifndef TLB_CAN_READ_FROM_L1_CACHE
87 dcache_line_size r2, r3
88 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
89 add r0, r0, r2
90 subs r1, r1, r2
91 bhi 1b
92 dsb
93 #endif
94 mov pc, lr
95 ENDPROC(cpu_v7_dcache_clean_area)
97 /*
98 * cpu_v7_switch_mm(pgd_phys, tsk)
99 *
100 * Set the translation table base pointer to be pgd_phys
101 *
102 * - pgd_phys - physical address of new TTB
103 *
104 * It is assumed that:
105 * - we are not using split page tables
106 */
107 ENTRY(cpu_v7_switch_mm)
108 #ifdef CONFIG_MMU
109 mov r2, #0
110 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
111 orr r0, r0, #TTB_FLAGS
112 #ifdef CONFIG_ARM_ERRATA_430973
113 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
114 #endif
115 mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID
116 isb
117 1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
118 isb
119 mcr p15, 0, r1, c13, c0, 1 @ set context ID
120 isb
121 #endif
122 mov pc, lr
123 ENDPROC(cpu_v7_switch_mm)
125 /*
126 * cpu_v7_set_pte_ext(ptep, pte)
127 *
128 * Set a level 2 translation table entry.
129 *
130 * - ptep - pointer to level 2 translation table entry
131 * (hardware version is stored at -1024 bytes)
132 * - pte - PTE value to store
133 * - ext - value for extended PTE bits
134 */
135 ENTRY(cpu_v7_set_pte_ext)
136 #ifdef CONFIG_MMU
137 ARM( str r1, [r0], #-2048 ) @ linux version
138 THUMB( str r1, [r0] ) @ linux version
139 THUMB( sub r0, r0, #2048 )
141 bic r3, r1, #0x000003f0
142 bic r3, r3, #PTE_TYPE_MASK
143 orr r3, r3, r2
144 orr r3, r3, #PTE_EXT_AP0 | 2
146 tst r1, #1 << 4
147 orrne r3, r3, #PTE_EXT_TEX(1)
149 tst r1, #L_PTE_WRITE
150 tstne r1, #L_PTE_DIRTY
151 orreq r3, r3, #PTE_EXT_APX
153 tst r1, #L_PTE_USER
154 orrne r3, r3, #PTE_EXT_AP1
155 tstne r3, #PTE_EXT_APX
156 bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
158 tst r1, #L_PTE_EXEC
159 orreq r3, r3, #PTE_EXT_XN
161 tst r1, #L_PTE_YOUNG
162 tstne r1, #L_PTE_PRESENT
163 moveq r3, #0
165 str r3, [r0]
166 mcr p15, 0, r0, c7, c10, 1 @ flush_pte
167 #endif
168 mov pc, lr
169 ENDPROC(cpu_v7_set_pte_ext)
171 cpu_v7_name:
172 .ascii "ARMv7 Processor"
173 .align
175 __INIT
177 /*
178 * __v7_setup
179 *
180 * Initialise TLB, Caches, and MMU state ready to switch the MMU
181 * on. Return in r0 the new CP15 C1 control register setting.
182 *
183 * We automatically detect if we have a Harvard cache, and use the
184 * Harvard cache control instructions insead of the unified cache
185 * control instructions.
186 *
187 * This should be able to cover all ARMv7 cores.
188 *
189 * It is assumed that:
190 * - cache type register is implemented
191 */
192 __v7_setup:
193 #ifdef CONFIG_SMP
194 mrc p15, 0, r0, c1, c0, 1
195 tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
196 orreq r0, r0, #(1 << 6) | (1 << 0) @ Enable SMP/nAMP mode and
197 mcreq p15, 0, r0, c1, c0, 1 @ TLB ops broadcasting
198 #endif
199 adr r12, __v7_setup_stack @ the local stack
200 stmia r12, {r0-r5, r7, r9, r11, lr}
201 bl v7_flush_dcache_all
202 ldmia r12, {r0-r5, r7, r9, r11, lr}
204 mrc p15, 0, r0, c0, c0, 0 @ read main ID register
205 and r10, r0, #0xff000000 @ ARM?
206 teq r10, #0x41000000
207 bne 2f
208 and r5, r0, #0x00f00000 @ variant
209 and r6, r0, #0x0000000f @ revision
210 orr r0, r6, r5, lsr #20-4 @ combine variant and revision
212 #ifdef CONFIG_ARM_ERRATA_430973
213 teq r5, #0x00100000 @ only present in r1p*
214 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
215 orreq r10, r10, #(1 << 6) @ set IBE to 1
216 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
217 #endif
218 #ifdef CONFIG_ARM_ERRATA_458693
219 teq r0, #0x20 @ only present in r2p0
220 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
221 orreq r10, r10, #(1 << 5) @ set L1NEON to 1
222 orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
223 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
224 #endif
225 #ifdef CONFIG_ARM_ERRATA_460075
226 teq r0, #0x20 @ only present in r2p0
227 mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
228 tsteq r10, #1 << 22
229 orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
230 mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
231 #endif
233 2: mov r10, #0
234 #ifdef HARVARD_CACHE
235 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
236 #endif
237 dsb
238 #ifdef CONFIG_MMU
239 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
240 mcr p15, 0, r10, c2, c0, 2 @ TTB control register
241 orr r4, r4, #TTB_FLAGS
242 mcr p15, 0, r4, c2, c0, 1 @ load TTB1
243 mov r10, #0x1f @ domains 0, 1 = manager
244 mcr p15, 0, r10, c3, c0, 0 @ load domain access register
245 /*
246 * Memory region attributes with SCTLR.TRE=1
247 *
248 * n = TEX[0],C,B
249 * TR = PRRR[2n+1:2n] - memory type
250 * IR = NMRR[2n+1:2n] - inner cacheable property
251 * OR = NMRR[2n+17:2n+16] - outer cacheable property
252 *
253 * n TR IR OR
254 * UNCACHED 000 00
255 * BUFFERABLE 001 10 00 00
256 * WRITETHROUGH 010 10 10 10
257 * WRITEBACK 011 10 11 11
258 * reserved 110
259 * WRITEALLOC 111 10 01 01
260 * DEV_SHARED 100 01
261 * DEV_NONSHARED 100 01
262 * DEV_WC 001 10
263 * DEV_CACHED 011 10
264 *
265 * Other attributes:
266 *
267 * DS0 = PRRR[16] = 0 - device shareable property
268 * DS1 = PRRR[17] = 1 - device shareable property
269 * NS0 = PRRR[18] = 0 - normal shareable property
270 * NS1 = PRRR[19] = 1 - normal shareable property
271 * NOS = PRRR[24+n] = 1 - not outer shareable
272 */
273 ldr r5, =0xff0a81a8 @ PRRR
274 ldr r6, =0x40e040e0 @ NMRR
275 mcr p15, 0, r5, c10, c2, 0 @ write PRRR
276 mcr p15, 0, r6, c10, c2, 1 @ write NMRR
277 #endif
278 adr r5, v7_crval
279 ldmia r5, {r5, r6}
280 #ifdef CONFIG_CPU_ENDIAN_BE8
281 orr r6, r6, #1 << 25 @ big-endian page tables
282 #endif
283 mrc p15, 0, r0, c1, c0, 0 @ read control register
284 bic r0, r0, r5 @ clear bits them
285 orr r0, r0, r6 @ set them
286 THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
287 mov pc, lr @ return to head.S:__ret
288 ENDPROC(__v7_setup)
290 /* AT
291 * TFR EV X F I D LR S
292 * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
293 * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
294 * 1 0 110 0011 1100 .111 1101 < we want
295 */
296 .type v7_crval, #object
297 v7_crval:
298 crval clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c
300 __v7_setup_stack:
301 .space 4 * 11 @ 11 registers
303 .type v7_processor_functions, #object
304 ENTRY(v7_processor_functions)
305 .word v7_early_abort
306 .word v7_pabort
307 .word cpu_v7_proc_init
308 .word cpu_v7_proc_fin
309 .word cpu_v7_reset
310 .word cpu_v7_do_idle
311 .word cpu_v7_dcache_clean_area
312 .word cpu_v7_switch_mm
313 .word cpu_v7_set_pte_ext
314 .size v7_processor_functions, . - v7_processor_functions
316 .type cpu_arch_name, #object
317 cpu_arch_name:
318 .asciz "armv7"
319 .size cpu_arch_name, . - cpu_arch_name
321 .type cpu_elf_name, #object
322 cpu_elf_name:
323 .asciz "v7"
324 .size cpu_elf_name, . - cpu_elf_name
325 .align
327 .section ".proc.info.init", #alloc, #execinstr
329 /*
330 * Match any ARMv7 processor core.
331 */
332 .type __v7_proc_info, #object
333 __v7_proc_info:
334 .long 0x000f0000 @ Required ID value
335 .long 0x000f0000 @ Mask for ID
336 .long PMD_TYPE_SECT | \
337 PMD_SECT_AP_WRITE | \
338 PMD_SECT_AP_READ | \
339 PMD_FLAGS
340 .long PMD_TYPE_SECT | \
341 PMD_SECT_XN | \
342 PMD_SECT_AP_WRITE | \
343 PMD_SECT_AP_READ
344 b __v7_setup
345 .long cpu_arch_name
346 .long cpu_elf_name
347 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
348 .long cpu_v7_name
349 .long v7_processor_functions
350 .long v7wbi_tlb_fns
351 .long v6_user_fns
352 .long v7_cache_fns
353 .size __v7_proc_info, . - __v7_proc_info