drivers/gpu/drm/sun4i/sun4i_tcon.c

   1 /*
   2  * Copyright (C) 2015 Free Electrons
   3  * Copyright (C) 2015 NextThing Co
   4  *
   5  * Maxime Ripard <maxime.ripard@free-electrons.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  */
  12
  13 #include <drm/drmP.h>
  14 #include <drm/drm_atomic_helper.h>
  15 #include <drm/drm_crtc.h>
  16 #include <drm/drm_crtc_helper.h>
  17 #include <drm/drm_encoder.h>
  18 #include <drm/drm_modes.h>
  19 #include <drm/drm_of.h>
  20
  21 #include <uapi/drm/drm_mode.h>
  22
  23 #include <linux/component.h>
  24 #include <linux/ioport.h>
  25 #include <linux/of_address.h>
  26 #include <linux/of_device.h>
  27 #include <linux/of_irq.h>
  28 #include <linux/regmap.h>
  29 #include <linux/reset.h>
  30
  31 #include "sun4i_crtc.h"
  32 #include "sun4i_dotclock.h"
  33 #include "sun4i_drv.h"
  34 #include "sun4i_lvds.h"
  35 #include "sun4i_rgb.h"
  36 #include "sun4i_tcon.h"
  37 #include "sunxi_engine.h"
  38
  39 static struct drm_connector *sun4i_tcon_get_connector(const struct drm_encoder *encoder)
  40 {
  41         struct drm_connector *connector;
  42         struct drm_connector_list_iter iter;
  43
  44         drm_connector_list_iter_begin(encoder->dev, &iter);
  45         drm_for_each_connector_iter(connector, &iter)
  46                 if (connector->encoder == encoder) {
  47                         drm_connector_list_iter_end(&iter);
  48                         return connector;
  49                 }
  50         drm_connector_list_iter_end(&iter);
  51
  52         return NULL;
  53 }
  54
  55 static int sun4i_tcon_get_pixel_depth(const struct drm_encoder *encoder)
  56 {
  57         struct drm_connector *connector;
  58         struct drm_display_info *info;
  59
  60         connector = sun4i_tcon_get_connector(encoder);
  61         if (!connector)
  62                 return -EINVAL;
  63
  64         info = &connector->display_info;
  65         if (info->num_bus_formats != 1)
  66                 return -EINVAL;
  67
  68         switch (info->bus_formats[0]) {
  69         case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
  70                 return 18;
  71
  72         case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
  73         case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
  74                 return 24;
  75         }
  76
  77         return -EINVAL;
  78 }
  79
  80 static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel,
  81                                           bool enabled)
  82 {
  83         struct clk *clk;
  84
  85         switch (channel) {
  86         case 0:
  87                 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
  88                                    SUN4I_TCON0_CTL_TCON_ENABLE,
  89                                    enabled ? SUN4I_TCON0_CTL_TCON_ENABLE : 0);
  90                 clk = tcon->dclk;
  91                 break;
  92         case 1:
  93                 WARN_ON(!tcon->quirks->has_channel_1);
  94                 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
  95                                    SUN4I_TCON1_CTL_TCON_ENABLE,
  96                                    enabled ? SUN4I_TCON1_CTL_TCON_ENABLE : 0);
  97                 clk = tcon->sclk1;
  98                 break;
  99         default:
 100                 DRM_WARN("Unknown channel... doing nothing\n");
 101                 return;
 102         }
 103
 104         if (enabled)
 105                 clk_prepare_enable(clk);
 106         else
 107                 clk_disable_unprepare(clk);
 108 }
 109
 110 static void sun4i_tcon_lvds_set_status(struct sun4i_tcon *tcon,
 111                                        const struct drm_encoder *encoder,
 112                                        bool enabled)
 113 {
 114         if (enabled) {
 115                 u8 val;
 116
 117                 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG,
 118                                    SUN4I_TCON0_LVDS_IF_EN,
 119                                    SUN4I_TCON0_LVDS_IF_EN);
 120
 121                 /*
 122                  * As their name suggest, these values only apply to the A31
 123                  * and later SoCs. We'll have to rework this when merging
 124                  * support for the older SoCs.
 125                  */
 126                 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
 127                              SUN6I_TCON0_LVDS_ANA0_C(2) |
 128                              SUN6I_TCON0_LVDS_ANA0_V(3) |
 129                              SUN6I_TCON0_LVDS_ANA0_PD(2) |
 130                              SUN6I_TCON0_LVDS_ANA0_EN_LDO);
 131                 udelay(2);
 132
 133                 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
 134                                    SUN6I_TCON0_LVDS_ANA0_EN_MB,
 135                                    SUN6I_TCON0_LVDS_ANA0_EN_MB);
 136                 udelay(2);
 137
 138                 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
 139                                    SUN6I_TCON0_LVDS_ANA0_EN_DRVC,
 140                                    SUN6I_TCON0_LVDS_ANA0_EN_DRVC);
 141
 142                 if (sun4i_tcon_get_pixel_depth(encoder) == 18)
 143                         val = 7;
 144                 else
 145                         val = 0xf;
 146
 147                 regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
 148                                   SUN6I_TCON0_LVDS_ANA0_EN_DRVD(0xf),
 149                                   SUN6I_TCON0_LVDS_ANA0_EN_DRVD(val));
 150         } else {
 151                 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG,
 152                                    SUN4I_TCON0_LVDS_IF_EN, 0);
 153         }
 154 }
 155
 156 void sun4i_tcon_set_status(struct sun4i_tcon *tcon,
 157                            const struct drm_encoder *encoder,
 158                            bool enabled)
 159 {
 160         bool is_lvds = false;
 161         int channel;
 162
 163         switch (encoder->encoder_type) {
 164         case DRM_MODE_ENCODER_LVDS:
 165                 is_lvds = true;
 166                 /* Fallthrough */
 167         case DRM_MODE_ENCODER_NONE:
 168                 channel = 0;
 169                 break;
 170         case DRM_MODE_ENCODER_TMDS:
 171         case DRM_MODE_ENCODER_TVDAC:
 172                 channel = 1;
 173                 break;
 174         default:
 175                 DRM_DEBUG_DRIVER("Unknown encoder type, doing nothing...\n");
 176                 return;
 177         }
 178
 179         if (is_lvds && !enabled)
 180                 sun4i_tcon_lvds_set_status(tcon, encoder, false);
 181
 182         regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
 183                            SUN4I_TCON_GCTL_TCON_ENABLE,
 184                            enabled ? SUN4I_TCON_GCTL_TCON_ENABLE : 0);
 185
 186         if (is_lvds && enabled)
 187                 sun4i_tcon_lvds_set_status(tcon, encoder, true);
 188
 189         sun4i_tcon_channel_set_status(tcon, channel, enabled);
 190 }
 191
 192 void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable)
 193 {
 194         u32 mask, val = 0;
 195
 196         DRM_DEBUG_DRIVER("%sabling VBLANK interrupt\n", enable ? "En" : "Dis");
 197
 198         mask = SUN4I_TCON_GINT0_VBLANK_ENABLE(0) |
 199                SUN4I_TCON_GINT0_VBLANK_ENABLE(1);
 200
 201         if (enable)
 202                 val = mask;
 203
 204         regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG, mask, val);
 205 }
 206 EXPORT_SYMBOL(sun4i_tcon_enable_vblank);
 207
 208 /*
 209  * This function is a helper for TCON output muxing. The TCON output
 210  * muxing control register in earlier SoCs (without the TCON TOP block)
 211  * are located in TCON0. This helper returns a pointer to TCON0's
 212  * sun4i_tcon structure, or NULL if not found.
 213  */
 214 static struct sun4i_tcon *sun4i_get_tcon0(struct drm_device *drm)
 215 {
 216         struct sun4i_drv *drv = drm->dev_private;
 217         struct sun4i_tcon *tcon;
 218
 219         list_for_each_entry(tcon, &drv->tcon_list, list)
 220                 if (tcon->id == 0)
 221                         return tcon;
 222
 223         dev_warn(drm->dev,
 224                  "TCON0 not found, display output muxing may not work\n");
 225
 226         return NULL;
 227 }
 228
 229 void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel,
 230                         const struct drm_encoder *encoder)
 231 {
 232         int ret = -ENOTSUPP;
 233
 234         if (tcon->quirks->set_mux)
 235                 ret = tcon->quirks->set_mux(tcon, encoder);
 236
 237         DRM_DEBUG_DRIVER("Muxing encoder %s to CRTC %s: %d\n",
 238                          encoder->name, encoder->crtc->name, ret);
 239 }
 240
 241 static int sun4i_tcon_get_clk_delay(const struct drm_display_mode *mode,
 242                                     int channel)
 243 {
 244         int delay = mode->vtotal - mode->vdisplay;
 245
 246         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 247                 delay /= 2;
 248
 249         if (channel == 1)
 250                 delay -= 2;
 251
 252         delay = min(delay, 30);
 253
 254         DRM_DEBUG_DRIVER("TCON %d clock delay %u\n", channel, delay);
 255
 256         return delay;
 257 }
 258
 259 static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon,
 260                                         const struct drm_display_mode *mode)
 261 {
 262         /* Configure the dot clock */
 263         clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
 264
 265         /* Set the resolution */
 266         regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
 267                      SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) |
 268                      SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
 269 }
 270
 271 static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon,
 272                                       const struct drm_encoder *encoder,
 273                                       const struct drm_display_mode *mode)
 274 {
 275         unsigned int bp;
 276         u8 clk_delay;
 277         u32 reg, val = 0;
 278
 279         tcon->dclk_min_div = 7;
 280         tcon->dclk_max_div = 7;
 281         sun4i_tcon0_mode_set_common(tcon, mode);
 282
 283         /* Adjust clock delay */
 284         clk_delay = sun4i_tcon_get_clk_delay(mode, 0);
 285         regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
 286                            SUN4I_TCON0_CTL_CLK_DELAY_MASK,
 287                            SUN4I_TCON0_CTL_CLK_DELAY(clk_delay));
 288
 289         /*
 290          * This is called a backporch in the register documentation,
 291          * but it really is the back porch + hsync
 292          */
 293         bp = mode->crtc_htotal - mode->crtc_hsync_start;
 294         DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
 295                          mode->crtc_htotal, bp);
 296
 297         /* Set horizontal display timings */
 298         regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG,
 299                      SUN4I_TCON0_BASIC1_H_TOTAL(mode->htotal) |
 300                      SUN4I_TCON0_BASIC1_H_BACKPORCH(bp));
 301
 302         /*
 303          * This is called a backporch in the register documentation,
 304          * but it really is the back porch + hsync
 305          */
 306         bp = mode->crtc_vtotal - mode->crtc_vsync_start;
 307         DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
 308                          mode->crtc_vtotal, bp);
 309
 310         /* Set vertical display timings */
 311         regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG,
 312                      SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) |
 313                      SUN4I_TCON0_BASIC2_V_BACKPORCH(bp));
 314
 315         reg = SUN4I_TCON0_LVDS_IF_CLK_SEL_TCON0 |
 316                 SUN4I_TCON0_LVDS_IF_DATA_POL_NORMAL |
 317                 SUN4I_TCON0_LVDS_IF_CLK_POL_NORMAL;
 318         if (sun4i_tcon_get_pixel_depth(encoder) == 24)
 319                 reg |= SUN4I_TCON0_LVDS_IF_BITWIDTH_24BITS;
 320         else
 321                 reg |= SUN4I_TCON0_LVDS_IF_BITWIDTH_18BITS;
 322
 323         regmap_write(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, reg);
 324
 325         /* Setup the polarity of the various signals */
 326         if (!(mode->flags & DRM_MODE_FLAG_PHSYNC))
 327                 val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE;
 328
 329         if (!(mode->flags & DRM_MODE_FLAG_PVSYNC))
 330                 val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;
 331
 332         regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val);
 333
 334         /* Map output pins to channel 0 */
 335         regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
 336                            SUN4I_TCON_GCTL_IOMAP_MASK,
 337                            SUN4I_TCON_GCTL_IOMAP_TCON0);
 338 }
 339
 340 static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
 341                                      const struct drm_display_mode *mode)
 342 {
 343         unsigned int bp, hsync, vsync;
 344         u8 clk_delay;
 345         u32 val = 0;
 346
 347         tcon->dclk_min_div = 6;
 348         tcon->dclk_max_div = 127;
 349         sun4i_tcon0_mode_set_common(tcon, mode);
 350
 351         /* Adjust clock delay */
 352         clk_delay = sun4i_tcon_get_clk_delay(mode, 0);
 353         regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
 354                            SUN4I_TCON0_CTL_CLK_DELAY_MASK,
 355                            SUN4I_TCON0_CTL_CLK_DELAY(clk_delay));
 356
 357         /*
 358          * This is called a backporch in the register documentation,
 359          * but it really is the back porch + hsync
 360          */
 361         bp = mode->crtc_htotal - mode->crtc_hsync_start;
 362         DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
 363                          mode->crtc_htotal, bp);
 364
 365         /* Set horizontal display timings */
 366         regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG,
 367                      SUN4I_TCON0_BASIC1_H_TOTAL(mode->crtc_htotal) |
 368                      SUN4I_TCON0_BASIC1_H_BACKPORCH(bp));
 369
 370         /*
 371          * This is called a backporch in the register documentation,
 372          * but it really is the back porch + hsync
 373          */
 374         bp = mode->crtc_vtotal - mode->crtc_vsync_start;
 375         DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
 376                          mode->crtc_vtotal, bp);
 377
 378         /* Set vertical display timings */
 379         regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG,
 380                      SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) |
 381                      SUN4I_TCON0_BASIC2_V_BACKPORCH(bp));
 382
 383         /* Set Hsync and Vsync length */
 384         hsync = mode->crtc_hsync_end - mode->crtc_hsync_start;
 385         vsync = mode->crtc_vsync_end - mode->crtc_vsync_start;
 386         DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync, vsync);
 387         regmap_write(tcon->regs, SUN4I_TCON0_BASIC3_REG,
 388                      SUN4I_TCON0_BASIC3_V_SYNC(vsync) |
 389                      SUN4I_TCON0_BASIC3_H_SYNC(hsync));
 390
 391         /* Setup the polarity of the various signals */
 392         if (!(mode->flags & DRM_MODE_FLAG_PHSYNC))
 393                 val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE;
 394
 395         if (!(mode->flags & DRM_MODE_FLAG_PVSYNC))
 396                 val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;
 397
 398         regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG,
 399                            SUN4I_TCON0_IO_POL_HSYNC_POSITIVE | SUN4I_TCON0_IO_POL_VSYNC_POSITIVE,
 400                            val);
 401
 402         /* Map output pins to channel 0 */
 403         regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
 404                            SUN4I_TCON_GCTL_IOMAP_MASK,
 405                            SUN4I_TCON_GCTL_IOMAP_TCON0);
 406
 407         /* Enable the output on the pins */
 408         regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0);
 409 }
 410
 411 static void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
 412                                  const struct drm_display_mode *mode)
 413 {
 414         unsigned int bp, hsync, vsync, vtotal;
 415         u8 clk_delay;
 416         u32 val;
 417
 418         WARN_ON(!tcon->quirks->has_channel_1);
 419
 420         /* Configure the dot clock */
 421         clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000);
 422
 423         /* Adjust clock delay */
 424         clk_delay = sun4i_tcon_get_clk_delay(mode, 1);
 425         regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
 426                            SUN4I_TCON1_CTL_CLK_DELAY_MASK,
 427                            SUN4I_TCON1_CTL_CLK_DELAY(clk_delay));
 428
 429         /* Set interlaced mode */
 430         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 431                 val = SUN4I_TCON1_CTL_INTERLACE_ENABLE;
 432         else
 433                 val = 0;
 434         regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
 435                            SUN4I_TCON1_CTL_INTERLACE_ENABLE,
 436                            val);
 437
 438         /* Set the input resolution */
 439         regmap_write(tcon->regs, SUN4I_TCON1_BASIC0_REG,
 440                      SUN4I_TCON1_BASIC0_X(mode->crtc_hdisplay) |
 441                      SUN4I_TCON1_BASIC0_Y(mode->crtc_vdisplay));
 442
 443         /* Set the upscaling resolution */
 444         regmap_write(tcon->regs, SUN4I_TCON1_BASIC1_REG,
 445                      SUN4I_TCON1_BASIC1_X(mode->crtc_hdisplay) |
 446                      SUN4I_TCON1_BASIC1_Y(mode->crtc_vdisplay));
 447
 448         /* Set the output resolution */
 449         regmap_write(tcon->regs, SUN4I_TCON1_BASIC2_REG,
 450                      SUN4I_TCON1_BASIC2_X(mode->crtc_hdisplay) |
 451                      SUN4I_TCON1_BASIC2_Y(mode->crtc_vdisplay));
 452
 453         /* Set horizontal display timings */
 454         bp = mode->crtc_htotal - mode->crtc_hsync_start;
 455         DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
 456                          mode->htotal, bp);
 457         regmap_write(tcon->regs, SUN4I_TCON1_BASIC3_REG,
 458                      SUN4I_TCON1_BASIC3_H_TOTAL(mode->crtc_htotal) |
 459                      SUN4I_TCON1_BASIC3_H_BACKPORCH(bp));
 460
 461         bp = mode->crtc_vtotal - mode->crtc_vsync_start;
 462         DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
 463                          mode->crtc_vtotal, bp);
 464
 465         /*
 466          * The vertical resolution needs to be doubled in all
 467          * cases. We could use crtc_vtotal and always multiply by two,
 468          * but that leads to a rounding error in interlace when vtotal
 469          * is odd.
 470          *
 471          * This happens with TV's PAL for example, where vtotal will
 472          * be 625, crtc_vtotal 312, and thus crtc_vtotal * 2 will be
 473          * 624, which apparently confuses the hardware.
 474          *
 475          * To work around this, we will always use vtotal, and
 476          * multiply by two only if we're not in interlace.
 477          */
 478         vtotal = mode->vtotal;
 479         if (!(mode->flags & DRM_MODE_FLAG_INTERLACE))
 480                 vtotal = vtotal * 2;
 481
 482         /* Set vertical display timings */
 483         regmap_write(tcon->regs, SUN4I_TCON1_BASIC4_REG,
 484                      SUN4I_TCON1_BASIC4_V_TOTAL(vtotal) |
 485                      SUN4I_TCON1_BASIC4_V_BACKPORCH(bp));
 486
 487         /* Set Hsync and Vsync length */
 488         hsync = mode->crtc_hsync_end - mode->crtc_hsync_start;
 489         vsync = mode->crtc_vsync_end - mode->crtc_vsync_start;
 490         DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync, vsync);
 491         regmap_write(tcon->regs, SUN4I_TCON1_BASIC5_REG,
 492                      SUN4I_TCON1_BASIC5_V_SYNC(vsync) |
 493                      SUN4I_TCON1_BASIC5_H_SYNC(hsync));
 494
 495         /* Map output pins to channel 1 */
 496         regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
 497                            SUN4I_TCON_GCTL_IOMAP_MASK,
 498                            SUN4I_TCON_GCTL_IOMAP_TCON1);
 499 }
 500
 501 void sun4i_tcon_mode_set(struct sun4i_tcon *tcon,
 502                          const struct drm_encoder *encoder,
 503                          const struct drm_display_mode *mode)
 504 {
 505         switch (encoder->encoder_type) {
 506         case DRM_MODE_ENCODER_LVDS:
 507                 sun4i_tcon0_mode_set_lvds(tcon, encoder, mode);
 508                 break;
 509         case DRM_MODE_ENCODER_NONE:
 510                 sun4i_tcon0_mode_set_rgb(tcon, mode);
 511                 sun4i_tcon_set_mux(tcon, 0, encoder);
 512                 break;
 513         case DRM_MODE_ENCODER_TVDAC:
 514         case DRM_MODE_ENCODER_TMDS:
 515                 sun4i_tcon1_mode_set(tcon, mode);
 516                 sun4i_tcon_set_mux(tcon, 1, encoder);
 517                 break;
 518         default:
 519                 DRM_DEBUG_DRIVER("Unknown encoder type, doing nothing...\n");
 520         }
 521 }
 522 EXPORT_SYMBOL(sun4i_tcon_mode_set);
 523
 524 static void sun4i_tcon_finish_page_flip(struct drm_device *dev,
 525                                         struct sun4i_crtc *scrtc)
 526 {
 527         unsigned long flags;
 528
 529         spin_lock_irqsave(&dev->event_lock, flags);
 530         if (scrtc->event) {
 531                 drm_crtc_send_vblank_event(&scrtc->crtc, scrtc->event);
 532                 drm_crtc_vblank_put(&scrtc->crtc);
 533                 scrtc->event = NULL;
 534         }
 535         spin_unlock_irqrestore(&dev->event_lock, flags);
 536 }
 537
 538 static irqreturn_t sun4i_tcon_handler(int irq, void *private)
 539 {
 540         struct sun4i_tcon *tcon = private;
 541         struct drm_device *drm = tcon->drm;
 542         struct sun4i_crtc *scrtc = tcon->crtc;
 543         unsigned int status;
 544
 545         regmap_read(tcon->regs, SUN4I_TCON_GINT0_REG, &status);
 546
 547         if (!(status & (SUN4I_TCON_GINT0_VBLANK_INT(0) |
 548                         SUN4I_TCON_GINT0_VBLANK_INT(1))))
 549                 return IRQ_NONE;
 550
 551         drm_crtc_handle_vblank(&scrtc->crtc);
 552         sun4i_tcon_finish_page_flip(drm, scrtc);
 553
 554         /* Acknowledge the interrupt */
 555         regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG,
 556                            SUN4I_TCON_GINT0_VBLANK_INT(0) |
 557                            SUN4I_TCON_GINT0_VBLANK_INT(1),
 558                            0);
 559
 560         return IRQ_HANDLED;
 561 }
 562
 563 static int sun4i_tcon_init_clocks(struct device *dev,
 564                                   struct sun4i_tcon *tcon)
 565 {
 566         tcon->clk = devm_clk_get(dev, "ahb");
 567         if (IS_ERR(tcon->clk)) {
 568                 dev_err(dev, "Couldn't get the TCON bus clock\n");
 569                 return PTR_ERR(tcon->clk);
 570         }
 571         clk_prepare_enable(tcon->clk);
 572
 573         tcon->sclk0 = devm_clk_get(dev, "tcon-ch0");
 574         if (IS_ERR(tcon->sclk0)) {
 575                 dev_err(dev, "Couldn't get the TCON channel 0 clock\n");
 576                 return PTR_ERR(tcon->sclk0);
 577         }
 578
 579         if (tcon->quirks->has_channel_1) {
 580                 tcon->sclk1 = devm_clk_get(dev, "tcon-ch1");
 581                 if (IS_ERR(tcon->sclk1)) {
 582                         dev_err(dev, "Couldn't get the TCON channel 1 clock\n");
 583                         return PTR_ERR(tcon->sclk1);
 584                 }
 585         }
 586
 587         return 0;
 588 }
 589
 590 static void sun4i_tcon_free_clocks(struct sun4i_tcon *tcon)
 591 {
 592         clk_disable_unprepare(tcon->clk);
 593 }
 594
 595 static int sun4i_tcon_init_irq(struct device *dev,
 596                                struct sun4i_tcon *tcon)
 597 {
 598         struct platform_device *pdev = to_platform_device(dev);
 599         int irq, ret;
 600
 601         irq = platform_get_irq(pdev, 0);
 602         if (irq < 0) {
 603                 dev_err(dev, "Couldn't retrieve the TCON interrupt\n");
 604                 return irq;
 605         }
 606
 607         ret = devm_request_irq(dev, irq, sun4i_tcon_handler, 0,
 608                                dev_name(dev), tcon);
 609         if (ret) {
 610                 dev_err(dev, "Couldn't request the IRQ\n");
 611                 return ret;
 612         }
 613
 614         return 0;
 615 }
 616
 617 static struct regmap_config sun4i_tcon_regmap_config = {
 618         .reg_bits       = 32,
 619         .val_bits       = 32,
 620         .reg_stride     = 4,
 621         .max_register   = 0x800,
 622 };
 623
 624 static int sun4i_tcon_init_regmap(struct device *dev,
 625                                   struct sun4i_tcon *tcon)
 626 {
 627         struct platform_device *pdev = to_platform_device(dev);
 628         struct resource *res;
 629         void __iomem *regs;
 630
 631         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 632         regs = devm_ioremap_resource(dev, res);
 633         if (IS_ERR(regs))
 634                 return PTR_ERR(regs);
 635
 636         tcon->regs = devm_regmap_init_mmio(dev, regs,
 637                                            &sun4i_tcon_regmap_config);
 638         if (IS_ERR(tcon->regs)) {
 639                 dev_err(dev, "Couldn't create the TCON regmap\n");
 640                 return PTR_ERR(tcon->regs);
 641         }
 642
 643         /* Make sure the TCON is disabled and all IRQs are off */
 644         regmap_write(tcon->regs, SUN4I_TCON_GCTL_REG, 0);
 645         regmap_write(tcon->regs, SUN4I_TCON_GINT0_REG, 0);
 646         regmap_write(tcon->regs, SUN4I_TCON_GINT1_REG, 0);
 647
 648         /* Disable IO lines and set them to tristate */
 649         regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, ~0);
 650         regmap_write(tcon->regs, SUN4I_TCON1_IO_TRI_REG, ~0);
 651
 652         return 0;
 653 }
 654
 655 /*
 656  * On SoCs with the old display pipeline design (Display Engine 1.0),
 657  * the TCON is always tied to just one backend. Hence we can traverse
 658  * the of_graph upwards to find the backend our tcon is connected to,
 659  * and take its ID as our own.
 660  *
 661  * We can either identify backends from their compatible strings, which
 662  * means maintaining a large list of them. Or, since the backend is
 663  * registered and binded before the TCON, we can just go through the
 664  * list of registered backends and compare the device node.
 665  *
 666  * As the structures now store engines instead of backends, here this
 667  * function in fact searches the corresponding engine, and the ID is
 668  * requested via the get_id function of the engine.
 669  */
 670 static struct sunxi_engine *
 671 sun4i_tcon_find_engine_traverse(struct sun4i_drv *drv,
 672                                 struct device_node *node)
 673 {
 674         struct device_node *port, *ep, *remote;
 675         struct sunxi_engine *engine = ERR_PTR(-EINVAL);
 676
 677         port = of_graph_get_port_by_id(node, 0);
 678         if (!port)
 679                 return ERR_PTR(-EINVAL);
 680
 681         /*
 682          * This only works if there is only one path from the TCON
 683          * to any display engine. Otherwise the probe order of the
 684          * TCONs and display engines is not guaranteed. They may
 685          * either bind to the wrong one, or worse, bind to the same
 686          * one if additional checks are not done.
 687          *
 688          * Bail out if there are multiple input connections.
 689          */
 690         if (of_get_available_child_count(port) != 1)
 691                 goto out_put_port;
 692
 693         /* Get the first connection without specifying an ID */
 694         ep = of_get_next_available_child(port, NULL);
 695         if (!ep)
 696                 goto out_put_port;
 697
 698         remote = of_graph_get_remote_port_parent(ep);
 699         if (!remote)
 700                 goto out_put_ep;
 701
 702         /* does this node match any registered engines? */
 703         list_for_each_entry(engine, &drv->engine_list, list)
 704                 if (remote == engine->node)
 705                         goto out_put_remote;
 706
 707         /* keep looking through upstream ports */
 708         engine = sun4i_tcon_find_engine_traverse(drv, remote);
 709
 710 out_put_remote:
 711         of_node_put(remote);
 712 out_put_ep:
 713         of_node_put(ep);
 714 out_put_port:
 715         of_node_put(port);
 716
 717         return engine;
 718 }
 719
 720 /*
 721  * The device tree binding says that the remote endpoint ID of any
 722  * connection between components, up to and including the TCON, of
 723  * the display pipeline should be equal to the actual ID of the local
 724  * component. Thus we can look at any one of the input connections of
 725  * the TCONs, and use that connection's remote endpoint ID as our own.
 726  *
 727  * Since the user of this function already finds the input port,
 728  * the port is passed in directly without further checks.
 729  */
 730 static int sun4i_tcon_of_get_id_from_port(struct device_node *port)
 731 {
 732         struct device_node *ep;
 733         int ret = -EINVAL;
 734
 735         /* try finding an upstream endpoint */
 736         for_each_available_child_of_node(port, ep) {
 737                 struct device_node *remote;
 738                 u32 reg;
 739
 740                 remote = of_graph_get_remote_endpoint(ep);
 741                 if (!remote)
 742                         continue;
 743
 744                 ret = of_property_read_u32(remote, "reg", &reg);
 745                 if (ret)
 746                         continue;
 747
 748                 ret = reg;
 749         }
 750
 751         return ret;
 752 }
 753
 754 /*
 755  * Once we know the TCON's id, we can look through the list of
 756  * engines to find a matching one. We assume all engines have
 757  * been probed and added to the list.
 758  */
 759 static struct sunxi_engine *sun4i_tcon_get_engine_by_id(struct sun4i_drv *drv,
 760                                                         int id)
 761 {
 762         struct sunxi_engine *engine;
 763
 764         list_for_each_entry(engine, &drv->engine_list, list)
 765                 if (engine->id == id)
 766                         return engine;
 767
 768         return ERR_PTR(-EINVAL);
 769 }
 770
 771 /*
 772  * On SoCs with the old display pipeline design (Display Engine 1.0),
 773  * we assumed the TCON was always tied to just one backend. However
 774  * this proved not to be the case. On the A31, the TCON can select
 775  * either backend as its source. On the A20 (and likely on the A10),
 776  * the backend can choose which TCON to output to.
 777  *
 778  * The device tree binding says that the remote endpoint ID of any
 779  * connection between components, up to and including the TCON, of
 780  * the display pipeline should be equal to the actual ID of the local
 781  * component. Thus we should be able to look at any one of the input
 782  * connections of the TCONs, and use that connection's remote endpoint
 783  * ID as our own.
 784  *
 785  * However  the connections between the backend and TCON were assumed
 786  * to be always singular, and their endpoit IDs were all incorrectly
 787  * set to 0. This means for these old device trees, we cannot just look
 788  * up the remote endpoint ID of a TCON input endpoint. TCON1 would be
 789  * incorrectly identified as TCON0.
 790  *
 791  * This function first checks if the TCON node has 2 input endpoints.
 792  * If so, then the device tree is a corrected version, and it will use
 793  * sun4i_tcon_of_get_id() and sun4i_tcon_get_engine_by_id() from above
 794  * to fetch the ID and engine directly. If not, then it is likely an
 795  * old device trees, where the endpoint IDs were incorrect, but did not
 796  * have endpoint connections between the backend and TCON across
 797  * different display pipelines. It will fall back to the old method of
 798  * traversing the  of_graph to try and find a matching engine by device
 799  * node.
 800  *
 801  * In the case of single display pipeline device trees, either method
 802  * works.
 803  */
 804 static struct sunxi_engine *sun4i_tcon_find_engine(struct sun4i_drv *drv,
 805                                                    struct device_node *node)
 806 {
 807         struct device_node *port;
 808         struct sunxi_engine *engine;
 809
 810         port = of_graph_get_port_by_id(node, 0);
 811         if (!port)
 812                 return ERR_PTR(-EINVAL);
 813
 814         /*
 815          * Is this a corrected device tree with cross pipeline
 816          * connections between the backend and TCON?
 817          */
 818         if (of_get_child_count(port) > 1) {
 819                 /* Get our ID directly from an upstream endpoint */
 820                 int id = sun4i_tcon_of_get_id_from_port(port);
 821
 822                 /* Get our engine by matching our ID */
 823                 engine = sun4i_tcon_get_engine_by_id(drv, id);
 824
 825                 of_node_put(port);
 826                 return engine;
 827         }
 828
 829         /* Fallback to old method by traversing input endpoints */
 830         of_node_put(port);
 831         return sun4i_tcon_find_engine_traverse(drv, node);
 832 }
 833
 834 static int sun4i_tcon_bind(struct device *dev, struct device *master,
 835                            void *data)
 836 {
 837         struct drm_device *drm = data;
 838         struct sun4i_drv *drv = drm->dev_private;
 839         struct sunxi_engine *engine;
 840         struct device_node *remote;
 841         struct sun4i_tcon *tcon;
 842         bool has_lvds_rst, has_lvds_alt, can_lvds;
 843         int ret;
 844
 845         engine = sun4i_tcon_find_engine(drv, dev->of_node);
 846         if (IS_ERR(engine)) {
 847                 dev_err(dev, "Couldn't find matching engine\n");
 848                 return -EPROBE_DEFER;
 849         }
 850
 851         tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL);
 852         if (!tcon)
 853                 return -ENOMEM;
 854         dev_set_drvdata(dev, tcon);
 855         tcon->drm = drm;
 856         tcon->dev = dev;
 857         tcon->id = engine->id;
 858         tcon->quirks = of_device_get_match_data(dev);
 859
 860         tcon->lcd_rst = devm_reset_control_get(dev, "lcd");
 861         if (IS_ERR(tcon->lcd_rst)) {
 862                 dev_err(dev, "Couldn't get our reset line\n");
 863                 return PTR_ERR(tcon->lcd_rst);
 864         }
 865
 866         /* Make sure our TCON is reset */
 867         ret = reset_control_reset(tcon->lcd_rst);
 868         if (ret) {
 869                 dev_err(dev, "Couldn't deassert our reset line\n");
 870                 return ret;
 871         }
 872
 873         /*
 874          * This can only be made optional since we've had DT nodes
 875          * without the LVDS reset properties.
 876          *
 877          * If the property is missing, just disable LVDS, and print a
 878          * warning.
 879          */
 880         tcon->lvds_rst = devm_reset_control_get_optional(dev, "lvds");
 881         if (IS_ERR(tcon->lvds_rst)) {
 882                 dev_err(dev, "Couldn't get our reset line\n");
 883                 return PTR_ERR(tcon->lvds_rst);
 884         } else if (tcon->lvds_rst) {
 885                 has_lvds_rst = true;
 886                 reset_control_reset(tcon->lvds_rst);
 887         } else {
 888                 has_lvds_rst = false;
 889         }
 890
 891         /*
 892          * This can only be made optional since we've had DT nodes
 893          * without the LVDS reset properties.
 894          *
 895          * If the property is missing, just disable LVDS, and print a
 896          * warning.
 897          */
 898         if (tcon->quirks->has_lvds_alt) {
 899                 tcon->lvds_pll = devm_clk_get(dev, "lvds-alt");
 900                 if (IS_ERR(tcon->lvds_pll)) {
 901                         if (PTR_ERR(tcon->lvds_pll) == -ENOENT) {
 902                                 has_lvds_alt = false;
 903                         } else {
 904                                 dev_err(dev, "Couldn't get the LVDS PLL\n");
 905                                 return PTR_ERR(tcon->lvds_pll);
 906                         }
 907                 } else {
 908                         has_lvds_alt = true;
 909                 }
 910         }
 911
 912         if (!has_lvds_rst || (tcon->quirks->has_lvds_alt && !has_lvds_alt)) {
 913                 dev_warn(dev,
 914                          "Missing LVDS properties, Please upgrade your DT\n");
 915                 dev_warn(dev, "LVDS output disabled\n");
 916                 can_lvds = false;
 917         } else {
 918                 can_lvds = true;
 919         }
 920
 921         ret = sun4i_tcon_init_clocks(dev, tcon);
 922         if (ret) {
 923                 dev_err(dev, "Couldn't init our TCON clocks\n");
 924                 goto err_assert_reset;
 925         }
 926
 927         ret = sun4i_tcon_init_regmap(dev, tcon);
 928         if (ret) {
 929                 dev_err(dev, "Couldn't init our TCON regmap\n");
 930                 goto err_free_clocks;
 931         }
 932
 933         ret = sun4i_dclk_create(dev, tcon);
 934         if (ret) {
 935                 dev_err(dev, "Couldn't create our TCON dot clock\n");
 936                 goto err_free_clocks;
 937         }
 938
 939         ret = sun4i_tcon_init_irq(dev, tcon);
 940         if (ret) {
 941                 dev_err(dev, "Couldn't init our TCON interrupts\n");
 942                 goto err_free_dotclock;
 943         }
 944
 945         tcon->crtc = sun4i_crtc_init(drm, engine, tcon);
 946         if (IS_ERR(tcon->crtc)) {
 947                 dev_err(dev, "Couldn't create our CRTC\n");
 948                 ret = PTR_ERR(tcon->crtc);
 949                 goto err_free_dotclock;
 950         }
 951
 952         /*
 953          * If we have an LVDS panel connected to the TCON, we should
 954          * just probe the LVDS connector. Otherwise, just probe RGB as
 955          * we used to.
 956          */
 957         remote = of_graph_get_remote_node(dev->of_node, 1, 0);
 958         if (of_device_is_compatible(remote, "panel-lvds"))
 959                 if (can_lvds)
 960                         ret = sun4i_lvds_init(drm, tcon);
 961                 else
 962                         ret = -EINVAL;
 963         else
 964                 ret = sun4i_rgb_init(drm, tcon);
 965         of_node_put(remote);
 966
 967         if (ret < 0)
 968                 goto err_free_dotclock;
 969
 970         if (tcon->quirks->needs_de_be_mux) {
 971                 /*
 972                  * We assume there is no dynamic muxing of backends
 973                  * and TCONs, so we select the backend with same ID.
 974                  *
 975                  * While dynamic selection might be interesting, since
 976                  * the CRTC is tied to the TCON, while the layers are
 977                  * tied to the backends, this means, we will need to
 978                  * switch between groups of layers. There might not be
 979                  * a way to represent this constraint in DRM.
 980                  */
 981                 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
 982                                    SUN4I_TCON0_CTL_SRC_SEL_MASK,
 983                                    tcon->id);
 984                 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
 985                                    SUN4I_TCON1_CTL_SRC_SEL_MASK,
 986                                    tcon->id);
 987         }
 988
 989         list_add_tail(&tcon->list, &drv->tcon_list);
 990
 991         return 0;
 992
 993 err_free_dotclock:
 994         sun4i_dclk_free(tcon);
 995 err_free_clocks:
 996         sun4i_tcon_free_clocks(tcon);
 997 err_assert_reset:
 998         reset_control_assert(tcon->lcd_rst);
 999         return ret;
1000 }
1001
1002 static void sun4i_tcon_unbind(struct device *dev, struct device *master,
1003                               void *data)
1004 {
1005         struct sun4i_tcon *tcon = dev_get_drvdata(dev);
1006
1007         list_del(&tcon->list);
1008         sun4i_dclk_free(tcon);
1009         sun4i_tcon_free_clocks(tcon);
1010 }
1011
1012 static const struct component_ops sun4i_tcon_ops = {
1013         .bind   = sun4i_tcon_bind,
1014         .unbind = sun4i_tcon_unbind,
1015 };
1016
1017 static int sun4i_tcon_probe(struct platform_device *pdev)
1018 {
1019         struct device_node *node = pdev->dev.of_node;
1020         struct drm_bridge *bridge;
1021         struct drm_panel *panel;
1022         int ret;
1023
1024         ret = drm_of_find_panel_or_bridge(node, 1, 0, &panel, &bridge);
1025         if (ret == -EPROBE_DEFER)
1026                 return ret;
1027
1028         return component_add(&pdev->dev, &sun4i_tcon_ops);
1029 }
1030
1031 static int sun4i_tcon_remove(struct platform_device *pdev)
1032 {
1033         component_del(&pdev->dev, &sun4i_tcon_ops);
1034
1035         return 0;
1036 }
1037
1038 /* platform specific TCON muxing callbacks */
1039 static int sun4i_a10_tcon_set_mux(struct sun4i_tcon *tcon,
1040                                   const struct drm_encoder *encoder)
1041 {
1042         struct sun4i_tcon *tcon0 = sun4i_get_tcon0(encoder->dev);
1043         u32 shift;
1044
1045         if (!tcon0)
1046                 return -EINVAL;
1047
1048         switch (encoder->encoder_type) {
1049         case DRM_MODE_ENCODER_TMDS:
1050                 /* HDMI */
1051                 shift = 8;
1052                 break;
1053         default:
1054                 return -EINVAL;
1055         }
1056
1057         regmap_update_bits(tcon0->regs, SUN4I_TCON_MUX_CTRL_REG,
1058                            0x3 << shift, tcon->id << shift);
1059
1060         return 0;
1061 }
1062
1063 static int sun5i_a13_tcon_set_mux(struct sun4i_tcon *tcon,
1064                                   const struct drm_encoder *encoder)
1065 {
1066         u32 val;
1067
1068         if (encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
1069                 val = 1;
1070         else
1071                 val = 0;
1072
1073         /*
1074          * FIXME: Undocumented bits
1075          */
1076         return regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, val);
1077 }
1078
1079 static int sun6i_tcon_set_mux(struct sun4i_tcon *tcon,
1080                               const struct drm_encoder *encoder)
1081 {
1082         struct sun4i_tcon *tcon0 = sun4i_get_tcon0(encoder->dev);
1083         u32 shift;
1084
1085         if (!tcon0)
1086                 return -EINVAL;
1087
1088         switch (encoder->encoder_type) {
1089         case DRM_MODE_ENCODER_TMDS:
1090                 /* HDMI */
1091                 shift = 8;
1092                 break;
1093         default:
1094                 /* TODO A31 has MIPI DSI but A31s does not */
1095                 return -EINVAL;
1096         }
1097
1098         regmap_update_bits(tcon0->regs, SUN4I_TCON_MUX_CTRL_REG,
1099                            0x3 << shift, tcon->id << shift);
1100
1101         return 0;
1102 }
1103
1104 static const struct sun4i_tcon_quirks sun4i_a10_quirks = {
1105         .has_channel_1          = true,
1106         .set_mux                = sun4i_a10_tcon_set_mux,
1107 };
1108
1109 static const struct sun4i_tcon_quirks sun5i_a13_quirks = {
1110         .has_channel_1          = true,
1111         .set_mux                = sun5i_a13_tcon_set_mux,
1112 };
1113
1114 static const struct sun4i_tcon_quirks sun6i_a31_quirks = {
1115         .has_channel_1          = true,
1116         .has_lvds_alt           = true,
1117         .needs_de_be_mux        = true,
1118         .set_mux                = sun6i_tcon_set_mux,
1119 };
1120
1121 static const struct sun4i_tcon_quirks sun6i_a31s_quirks = {
1122         .has_channel_1          = true,
1123         .needs_de_be_mux        = true,
1124 };
1125
1126 static const struct sun4i_tcon_quirks sun7i_a20_quirks = {
1127         .has_channel_1          = true,
1128         /* Same display pipeline structure as A10 */
1129         .set_mux                = sun4i_a10_tcon_set_mux,
1130 };
1131
1132 static const struct sun4i_tcon_quirks sun8i_a33_quirks = {
1133         .has_lvds_alt           = true,
1134 };
1135
1136 static const struct sun4i_tcon_quirks sun8i_a83t_lcd_quirks = {
1137         /* nothing is supported */
1138 };
1139
1140 static const struct sun4i_tcon_quirks sun8i_v3s_quirks = {
1141         /* nothing is supported */
1142 };
1143
1144 /* sun4i_drv uses this list to check if a device node is a TCON */
1145 const struct of_device_id sun4i_tcon_of_table[] = {
1146         { .compatible = "allwinner,sun4i-a10-tcon", .data = &sun4i_a10_quirks },
1147         { .compatible = "allwinner,sun5i-a13-tcon", .data = &sun5i_a13_quirks },
1148         { .compatible = "allwinner,sun6i-a31-tcon", .data = &sun6i_a31_quirks },
1149         { .compatible = "allwinner,sun6i-a31s-tcon", .data = &sun6i_a31s_quirks },
1150         { .compatible = "allwinner,sun7i-a20-tcon", .data = &sun7i_a20_quirks },
1151         { .compatible = "allwinner,sun8i-a33-tcon", .data = &sun8i_a33_quirks },
1152         { .compatible = "allwinner,sun8i-a83t-tcon-lcd", .data = &sun8i_a83t_lcd_quirks },
1153         { .compatible = "allwinner,sun8i-v3s-tcon", .data = &sun8i_v3s_quirks },
1154         { }
1155 };
1156 MODULE_DEVICE_TABLE(of, sun4i_tcon_of_table);
1157 EXPORT_SYMBOL(sun4i_tcon_of_table);
1158
1159 static struct platform_driver sun4i_tcon_platform_driver = {
1160         .probe          = sun4i_tcon_probe,
1161         .remove         = sun4i_tcon_remove,
1162         .driver         = {
1163                 .name           = "sun4i-tcon",
1164                 .of_match_table = sun4i_tcon_of_table,
1165         },
1166 };
1167 module_platform_driver(sun4i_tcon_platform_driver);
1168
1169 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1170 MODULE_DESCRIPTION("Allwinner A10 Timing Controller Driver");
1171 MODULE_LICENSE("GPL");