drivers/accel/ivpu/ivpu_drv.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2020-2024 Intel Corporation
   4  */
   5
   6 #ifndef __IVPU_DRV_H__
   7 #define __IVPU_DRV_H__
   8
   9 #include <drm/drm_device.h>
  10 #include <drm/drm_drv.h>
  11 #include <drm/drm_managed.h>
  12 #include <drm/drm_mm.h>
  13 #include <drm/drm_print.h>
  14
  15 #include <linux/pci.h>
  16 #include <linux/xarray.h>
  17 #include <uapi/drm/ivpu_accel.h>
  18
  19 #include "ivpu_mmu_context.h"
  20 #include "ivpu_ipc.h"
  21
  22 #define DRIVER_NAME "intel_vpu"
  23 #define DRIVER_DESC "Driver for Intel NPU (Neural Processing Unit)"
  24
  25 #define PCI_DEVICE_ID_MTL       0x7d1d
  26 #define PCI_DEVICE_ID_ARL       0xad1d
  27 #define PCI_DEVICE_ID_LNL       0x643e
  28 #define PCI_DEVICE_ID_PTL_P     0xb03e
  29
  30 #define IVPU_HW_IP_37XX 37
  31 #define IVPU_HW_IP_40XX 40
  32 #define IVPU_HW_IP_50XX 50
  33 #define IVPU_HW_IP_60XX 60
  34
  35 #define IVPU_HW_IP_REV_LNL_B0 4
  36
  37 #define IVPU_HW_BTRS_MTL 1
  38 #define IVPU_HW_BTRS_LNL 2
  39
  40 #define IVPU_GLOBAL_CONTEXT_MMU_SSID   0
  41 /* SSID 1 is used by the VPU to represent reserved context */
  42 #define IVPU_RESERVED_CONTEXT_MMU_SSID 1
  43 #define IVPU_USER_CONTEXT_MIN_SSID     2
  44 #define IVPU_USER_CONTEXT_MAX_SSID     (IVPU_USER_CONTEXT_MIN_SSID + 63)
  45
  46 #define IVPU_MIN_DB 1
  47 #define IVPU_MAX_DB 255
  48
  49 #define IVPU_JOB_ID_JOB_MASK            GENMASK(7, 0)
  50 #define IVPU_JOB_ID_CONTEXT_MASK        GENMASK(31, 8)
  51
  52 #define IVPU_NUM_PRIORITIES    4
  53 #define IVPU_NUM_CMDQS_PER_CTX (IVPU_NUM_PRIORITIES)
  54
  55 #define IVPU_CMDQ_MIN_ID 1
  56 #define IVPU_CMDQ_MAX_ID 255
  57
  58 #define IVPU_PLATFORM_SILICON 0
  59 #define IVPU_PLATFORM_SIMICS  2
  60 #define IVPU_PLATFORM_FPGA    3
  61 #define IVPU_PLATFORM_INVALID 8
  62
  63 #define IVPU_SCHED_MODE_AUTO -1
  64
  65 #define IVPU_DBG_REG     BIT(0)
  66 #define IVPU_DBG_IRQ     BIT(1)
  67 #define IVPU_DBG_MMU     BIT(2)
  68 #define IVPU_DBG_FILE    BIT(3)
  69 #define IVPU_DBG_MISC    BIT(4)
  70 #define IVPU_DBG_FW_BOOT BIT(5)
  71 #define IVPU_DBG_PM      BIT(6)
  72 #define IVPU_DBG_IPC     BIT(7)
  73 #define IVPU_DBG_BO      BIT(8)
  74 #define IVPU_DBG_JOB     BIT(9)
  75 #define IVPU_DBG_JSM     BIT(10)
  76 #define IVPU_DBG_KREF    BIT(11)
  77 #define IVPU_DBG_RPM     BIT(12)
  78 #define IVPU_DBG_MMU_MAP BIT(13)
  79
  80 #define ivpu_err(vdev, fmt, ...) \
  81         drm_err(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
  82
  83 #define ivpu_err_ratelimited(vdev, fmt, ...) \
  84         drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
  85
  86 #define ivpu_warn(vdev, fmt, ...) \
  87         drm_warn(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
  88
  89 #define ivpu_warn_ratelimited(vdev, fmt, ...) \
  90         drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
  91
  92 #define ivpu_info(vdev, fmt, ...) drm_info(&(vdev)->drm, fmt, ##__VA_ARGS__)
  93
  94 #define ivpu_dbg(vdev, type, fmt, args...) do {                                \
  95         if (unlikely(IVPU_DBG_##type & ivpu_dbg_mask))                         \
  96                 dev_dbg((vdev)->drm.dev, "[%s] " fmt, #type, ##args);          \
  97 } while (0)
  98
  99 #define IVPU_WA(wa_name) (vdev->wa.wa_name)
 100
 101 #define IVPU_PRINT_WA(wa_name) do {                                     \
 102         if (IVPU_WA(wa_name))                                           \
 103                 ivpu_dbg(vdev, MISC, "Using WA: " #wa_name "\n");       \
 104 } while (0)
 105
 106 struct ivpu_wa_table {
 107         bool punit_disabled;
 108         bool clear_runtime_mem;
 109         bool interrupt_clear_with_0;
 110         bool disable_clock_relinquish;
 111         bool disable_d0i3_msg;
 112         bool wp0_during_power_up;
 113 };
 114
 115 struct ivpu_hw_info;
 116 struct ivpu_mmu_info;
 117 struct ivpu_fw_info;
 118 struct ivpu_ipc_info;
 119 struct ivpu_pm_info;
 120
 121 struct ivpu_device {
 122         struct drm_device drm;
 123         void __iomem *regb;
 124         void __iomem *regv;
 125         u32 platform;
 126         u32 irq;
 127
 128         struct ivpu_wa_table wa;
 129         struct ivpu_hw_info *hw;
 130         struct ivpu_mmu_info *mmu;
 131         struct ivpu_fw_info *fw;
 132         struct ivpu_ipc_info *ipc;
 133         struct ivpu_pm_info *pm;
 134
 135         struct ivpu_mmu_context gctx;
 136         struct ivpu_mmu_context rctx;
 137         struct mutex context_list_lock; /* Protects user context addition/removal */
 138         struct xarray context_xa;
 139         struct xa_limit context_xa_limit;
 140
 141         struct xarray db_xa;
 142         struct xa_limit db_limit;
 143         u32 db_next;
 144
 145         struct mutex bo_list_lock; /* Protects bo_list */
 146         struct list_head bo_list;
 147
 148         struct xarray submitted_jobs_xa;
 149         struct ivpu_ipc_consumer job_done_consumer;
 150
 151         atomic64_t unique_id_counter;
 152
 153         ktime_t busy_start_ts;
 154         ktime_t busy_time;
 155
 156         struct {
 157                 int boot;
 158                 int jsm;
 159                 int tdr;
 160                 int autosuspend;
 161                 int d0i3_entry_msg;
 162                 int state_dump_msg;
 163         } timeout;
 164 };
 165
 166 /*
 167  * file_priv has its own refcount (ref) that allows user space to close the fd
 168  * without blocking even if VPU is still processing some jobs.
 169  */
 170 struct ivpu_file_priv {
 171         struct kref ref;
 172         struct ivpu_device *vdev;
 173         struct mutex lock; /* Protects cmdq */
 174         struct xarray cmdq_xa;
 175         struct ivpu_mmu_context ctx;
 176         struct mutex ms_lock; /* Protects ms_instance_list, ms_info_bo */
 177         struct list_head ms_instance_list;
 178         struct ivpu_bo *ms_info_bo;
 179         struct xa_limit job_limit;
 180         u32 job_id_next;
 181         struct xa_limit cmdq_limit;
 182         u32 cmdq_id_next;
 183         bool has_mmu_faults;
 184         bool bound;
 185         bool aborted;
 186 };
 187
 188 extern int ivpu_dbg_mask;
 189 extern u8 ivpu_pll_min_ratio;
 190 extern u8 ivpu_pll_max_ratio;
 191 extern int ivpu_sched_mode;
 192 extern bool ivpu_disable_mmu_cont_pages;
 193 extern bool ivpu_force_snoop;
 194
 195 #define IVPU_TEST_MODE_FW_TEST            BIT(0)
 196 #define IVPU_TEST_MODE_NULL_HW            BIT(1)
 197 #define IVPU_TEST_MODE_NULL_SUBMISSION    BIT(2)
 198 #define IVPU_TEST_MODE_D0I3_MSG_DISABLE   BIT(4)
 199 #define IVPU_TEST_MODE_D0I3_MSG_ENABLE    BIT(5)
 200 #define IVPU_TEST_MODE_MIP_DISABLE        BIT(6)
 201 #define IVPU_TEST_MODE_DISABLE_TIMEOUTS   BIT(8)
 202 #define IVPU_TEST_MODE_TURBO              BIT(9)
 203 extern int ivpu_test_mode;
 204
 205 struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv);
 206 void ivpu_file_priv_put(struct ivpu_file_priv **link);
 207
 208 int ivpu_boot(struct ivpu_device *vdev);
 209 int ivpu_shutdown(struct ivpu_device *vdev);
 210 void ivpu_prepare_for_reset(struct ivpu_device *vdev);
 211
 212 static inline u8 ivpu_revision(struct ivpu_device *vdev)
 213 {
 214         return to_pci_dev(vdev->drm.dev)->revision;
 215 }
 216
 217 static inline u16 ivpu_device_id(struct ivpu_device *vdev)
 218 {
 219         return to_pci_dev(vdev->drm.dev)->device;
 220 }
 221
 222 static inline int ivpu_hw_ip_gen(struct ivpu_device *vdev)
 223 {
 224         switch (ivpu_device_id(vdev)) {
 225         case PCI_DEVICE_ID_MTL:
 226         case PCI_DEVICE_ID_ARL:
 227                 return IVPU_HW_IP_37XX;
 228         case PCI_DEVICE_ID_LNL:
 229                 return IVPU_HW_IP_40XX;
 230         case PCI_DEVICE_ID_PTL_P:
 231                 return IVPU_HW_IP_50XX;
 232         default:
 233                 dump_stack();
 234                 ivpu_err(vdev, "Unknown NPU IP generation\n");
 235                 return 0;
 236         }
 237 }
 238
 239 static inline int ivpu_hw_btrs_gen(struct ivpu_device *vdev)
 240 {
 241         switch (ivpu_device_id(vdev)) {
 242         case PCI_DEVICE_ID_MTL:
 243         case PCI_DEVICE_ID_ARL:
 244                 return IVPU_HW_BTRS_MTL;
 245         case PCI_DEVICE_ID_LNL:
 246         case PCI_DEVICE_ID_PTL_P:
 247                 return IVPU_HW_BTRS_LNL;
 248         default:
 249                 dump_stack();
 250                 ivpu_err(vdev, "Unknown buttress generation\n");
 251                 return 0;
 252         }
 253 }
 254
 255 static inline struct ivpu_device *to_ivpu_device(struct drm_device *dev)
 256 {
 257         return container_of(dev, struct ivpu_device, drm);
 258 }
 259
 260 static inline u32 ivpu_get_context_count(struct ivpu_device *vdev)
 261 {
 262         struct xa_limit ctx_limit = vdev->context_xa_limit;
 263
 264         return (ctx_limit.max - ctx_limit.min + 1);
 265 }
 266
 267 static inline u32 ivpu_get_platform(struct ivpu_device *vdev)
 268 {
 269         WARN_ON_ONCE(vdev->platform == IVPU_PLATFORM_INVALID);
 270         return vdev->platform;
 271 }
 272
 273 static inline bool ivpu_is_silicon(struct ivpu_device *vdev)
 274 {
 275         return ivpu_get_platform(vdev) == IVPU_PLATFORM_SILICON;
 276 }
 277
 278 static inline bool ivpu_is_simics(struct ivpu_device *vdev)
 279 {
 280         return ivpu_get_platform(vdev) == IVPU_PLATFORM_SIMICS;
 281 }
 282
 283 static inline bool ivpu_is_fpga(struct ivpu_device *vdev)
 284 {
 285         return ivpu_get_platform(vdev) == IVPU_PLATFORM_FPGA;
 286 }
 287
 288 static inline bool ivpu_is_force_snoop_enabled(struct ivpu_device *vdev)
 289 {
 290         return ivpu_force_snoop;
 291 }
 292
 293 #endif /* __IVPU_DRV_H__ */