drivers/clk/renesas/rzv2h-cpg.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Renesas RZ/V2H(P) Clock Pulse Generator
   4  *
   5  * Copyright (C) 2024 Renesas Electronics Corp.
   6  */
   7
   8 #ifndef __RENESAS_RZV2H_CPG_H__
   9 #define __RENESAS_RZV2H_CPG_H__
  10
  11 /**
  12  * struct ddiv - Structure for dynamic switching divider
  13  *
  14  * @offset: register offset
  15  * @shift: position of the divider bit
  16  * @width: width of the divider
  17  * @monbit: monitor bit in CPG_CLKSTATUS0 register
  18  */
  19 struct ddiv {
  20         unsigned int offset:11;
  21         unsigned int shift:4;
  22         unsigned int width:4;
  23         unsigned int monbit:5;
  24 };
  25
  26 #define DDIV_PACK(_offset, _shift, _width, _monbit) \
  27         ((struct ddiv){ \
  28                 .offset = _offset, \
  29                 .shift = _shift, \
  30                 .width = _width, \
  31                 .monbit = _monbit \
  32         })
  33
  34 #define CPG_CDDIV0              (0x400)
  35 #define CPG_CDDIV1              (0x404)
  36
  37 #define CDDIV0_DIVCTL2  DDIV_PACK(CPG_CDDIV0, 8, 3, 2)
  38 #define CDDIV1_DIVCTL0  DDIV_PACK(CPG_CDDIV1, 0, 2, 4)
  39 #define CDDIV1_DIVCTL1  DDIV_PACK(CPG_CDDIV1, 4, 2, 5)
  40 #define CDDIV1_DIVCTL2  DDIV_PACK(CPG_CDDIV1, 8, 2, 6)
  41 #define CDDIV1_DIVCTL3  DDIV_PACK(CPG_CDDIV1, 12, 2, 7)
  42
  43 /**
  44  * Definitions of CPG Core Clocks
  45  *
  46  * These include:
  47  *   - Clock outputs exported to DT
  48  *   - External input clocks
  49  *   - Internal CPG clocks
  50  */
  51 struct cpg_core_clk {
  52         const char *name;
  53         unsigned int id;
  54         unsigned int parent;
  55         unsigned int div;
  56         unsigned int mult;
  57         unsigned int type;
  58         union {
  59                 unsigned int conf;
  60                 struct ddiv ddiv;
  61         } cfg;
  62         const struct clk_div_table *dtable;
  63         u32 flag;
  64 };
  65
  66 enum clk_types {
  67         /* Generic */
  68         CLK_TYPE_IN,            /* External Clock Input */
  69         CLK_TYPE_FF,            /* Fixed Factor Clock */
  70         CLK_TYPE_PLL,
  71         CLK_TYPE_DDIV,          /* Dynamic Switching Divider */
  72 };
  73
  74 /* BIT(31) indicates if CLK1/2 are accessible or not */
  75 #define PLL_CONF(n)             (BIT(31) | ((n) & ~GENMASK(31, 16)))
  76 #define PLL_CLK_ACCESS(n)       ((n) & BIT(31) ? 1 : 0)
  77 #define PLL_CLK1_OFFSET(n)      ((n) & ~GENMASK(31, 16))
  78 #define PLL_CLK2_OFFSET(n)      (((n) & ~GENMASK(31, 16)) + (0x4))
  79
  80 #define DEF_TYPE(_name, _id, _type...) \
  81         { .name = _name, .id = _id, .type = _type }
  82 #define DEF_BASE(_name, _id, _type, _parent...) \
  83         DEF_TYPE(_name, _id, _type, .parent = _parent)
  84 #define DEF_PLL(_name, _id, _parent, _conf) \
  85         DEF_TYPE(_name, _id, CLK_TYPE_PLL, .parent = _parent, .cfg.conf = _conf)
  86 #define DEF_INPUT(_name, _id) \
  87         DEF_TYPE(_name, _id, CLK_TYPE_IN)
  88 #define DEF_FIXED(_name, _id, _parent, _mult, _div) \
  89         DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
  90 #define DEF_DDIV(_name, _id, _parent, _ddiv_packed, _dtable) \
  91         DEF_TYPE(_name, _id, CLK_TYPE_DDIV, \
  92                 .cfg.ddiv = _ddiv_packed, \
  93                 .parent = _parent, \
  94                 .dtable = _dtable, \
  95                 .flag = CLK_DIVIDER_HIWORD_MASK)
  96
  97 /**
  98  * struct rzv2h_mod_clk - Module Clocks definitions
  99  *
 100  * @name: handle between common and hardware-specific interfaces
 101  * @parent: id of parent clock
 102  * @critical: flag to indicate the clock is critical
 103  * @on_index: control register index
 104  * @on_bit: ON bit
 105  * @mon_index: monitor register index
 106  * @mon_bit: monitor bit
 107  */
 108 struct rzv2h_mod_clk {
 109         const char *name;
 110         u16 parent;
 111         bool critical;
 112         u8 on_index;
 113         u8 on_bit;
 114         s8 mon_index;
 115         u8 mon_bit;
 116 };
 117
 118 #define DEF_MOD_BASE(_name, _parent, _critical, _onindex, _onbit, _monindex, _monbit) \
 119         { \
 120                 .name = (_name), \
 121                 .parent = (_parent), \
 122                 .critical = (_critical), \
 123                 .on_index = (_onindex), \
 124                 .on_bit = (_onbit), \
 125                 .mon_index = (_monindex), \
 126                 .mon_bit = (_monbit), \
 127         }
 128
 129 #define DEF_MOD(_name, _parent, _onindex, _onbit, _monindex, _monbit)           \
 130         DEF_MOD_BASE(_name, _parent, false, _onindex, _onbit, _monindex, _monbit)
 131
 132 #define DEF_MOD_CRITICAL(_name, _parent, _onindex, _onbit, _monindex, _monbit)  \
 133         DEF_MOD_BASE(_name, _parent, true, _onindex, _onbit, _monindex, _monbit)
 134
 135 /**
 136  * struct rzv2h_reset - Reset definitions
 137  *
 138  * @reset_index: reset register index
 139  * @reset_bit: reset bit
 140  * @mon_index: monitor register index
 141  * @mon_bit: monitor bit
 142  */
 143 struct rzv2h_reset {
 144         u8 reset_index;
 145         u8 reset_bit;
 146         u8 mon_index;
 147         u8 mon_bit;
 148 };
 149
 150 #define DEF_RST_BASE(_resindex, _resbit, _monindex, _monbit)    \
 151         { \
 152                 .reset_index = (_resindex), \
 153                 .reset_bit = (_resbit), \
 154                 .mon_index = (_monindex), \
 155                 .mon_bit = (_monbit), \
 156         }
 157
 158 #define DEF_RST(_resindex, _resbit, _monindex, _monbit) \
 159         DEF_RST_BASE(_resindex, _resbit, _monindex, _monbit)
 160
 161 /**
 162  * struct rzv2h_cpg_info - SoC-specific CPG Description
 163  *
 164  * @core_clks: Array of Core Clock definitions
 165  * @num_core_clks: Number of entries in core_clks[]
 166  * @last_dt_core_clk: ID of the last Core Clock exported to DT
 167  * @num_total_core_clks: Total number of Core Clocks (exported + internal)
 168  *
 169  * @mod_clks: Array of Module Clock definitions
 170  * @num_mod_clks: Number of entries in mod_clks[]
 171  * @num_hw_mod_clks: Number of Module Clocks supported by the hardware
 172  *
 173  * @resets: Array of Module Reset definitions
 174  * @num_resets: Number of entries in resets[]
 175  */
 176 struct rzv2h_cpg_info {
 177         /* Core Clocks */
 178         const struct cpg_core_clk *core_clks;
 179         unsigned int num_core_clks;
 180         unsigned int last_dt_core_clk;
 181         unsigned int num_total_core_clks;
 182
 183         /* Module Clocks */
 184         const struct rzv2h_mod_clk *mod_clks;
 185         unsigned int num_mod_clks;
 186         unsigned int num_hw_mod_clks;
 187
 188         /* Resets */
 189         const struct rzv2h_reset *resets;
 190         unsigned int num_resets;
 191 };
 192
 193 extern const struct rzv2h_cpg_info r9a09g057_cpg_info;
 194
 195 #endif  /* __RENESAS_RZV2H_CPG_H__ */