drivers/counter/stm32-timer-cnt.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * STM32 Timer Encoder and Counter driver
   4  *
   5  * Copyright (C) STMicroelectronics 2018
   6  *
   7  * Author: Benjamin Gaignard <benjamin.gaignard@st.com>
   8  *
   9  */
  10 #include <linux/counter.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/mfd/stm32-timers.h>
  13 #include <linux/mod_devicetable.h>
  14 #include <linux/module.h>
  15 #include <linux/of.h>
  16 #include <linux/pinctrl/consumer.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/types.h>
  19
  20 #define TIM_CCMR_CCXS   (BIT(8) | BIT(0))
  21 #define TIM_CCMR_MASK   (TIM_CCMR_CC1S | TIM_CCMR_CC2S | \
  22                          TIM_CCMR_IC1F | TIM_CCMR_IC2F)
  23 #define TIM_CCER_MASK   (TIM_CCER_CC1P | TIM_CCER_CC1NP | \
  24                          TIM_CCER_CC2P | TIM_CCER_CC2NP)
  25
  26 #define STM32_CH1_SIG           0
  27 #define STM32_CH2_SIG           1
  28 #define STM32_CLOCK_SIG         2
  29 #define STM32_CH3_SIG           3
  30 #define STM32_CH4_SIG           4
  31
  32 struct stm32_timer_regs {
  33         u32 cr1;
  34         u32 cnt;
  35         u32 smcr;
  36         u32 arr;
  37 };
  38
  39 struct stm32_timer_cnt {
  40         struct regmap *regmap;
  41         struct clk *clk;
  42         u32 max_arr;
  43         bool enabled;
  44         struct stm32_timer_regs bak;
  45         bool has_encoder;
  46         unsigned int nchannels;
  47         unsigned int nr_irqs;
  48         spinlock_t lock; /* protects nb_ovf */
  49         u64 nb_ovf;
  50 };
  51
  52 static const enum counter_function stm32_count_functions[] = {
  53         COUNTER_FUNCTION_INCREASE,
  54         COUNTER_FUNCTION_QUADRATURE_X2_A,
  55         COUNTER_FUNCTION_QUADRATURE_X2_B,
  56         COUNTER_FUNCTION_QUADRATURE_X4,
  57 };
  58
  59 static int stm32_count_read(struct counter_device *counter,
  60                             struct counter_count *count, u64 *val)
  61 {
  62         struct stm32_timer_cnt *const priv = counter_priv(counter);
  63         u32 cnt;
  64
  65         regmap_read(priv->regmap, TIM_CNT, &cnt);
  66         *val = cnt;
  67
  68         return 0;
  69 }
  70
  71 static int stm32_count_write(struct counter_device *counter,
  72                              struct counter_count *count, const u64 val)
  73 {
  74         struct stm32_timer_cnt *const priv = counter_priv(counter);
  75         u32 ceiling;
  76
  77         regmap_read(priv->regmap, TIM_ARR, &ceiling);
  78         if (val > ceiling)
  79                 return -EINVAL;
  80
  81         return regmap_write(priv->regmap, TIM_CNT, val);
  82 }
  83
  84 static int stm32_count_function_read(struct counter_device *counter,
  85                                      struct counter_count *count,
  86                                      enum counter_function *function)
  87 {
  88         struct stm32_timer_cnt *const priv = counter_priv(counter);
  89         u32 smcr;
  90
  91         regmap_read(priv->regmap, TIM_SMCR, &smcr);
  92
  93         switch (smcr & TIM_SMCR_SMS) {
  94         case TIM_SMCR_SMS_SLAVE_MODE_DISABLED:
  95                 *function = COUNTER_FUNCTION_INCREASE;
  96                 return 0;
  97         case TIM_SMCR_SMS_ENCODER_MODE_1:
  98                 *function = COUNTER_FUNCTION_QUADRATURE_X2_A;
  99                 return 0;
 100         case TIM_SMCR_SMS_ENCODER_MODE_2:
 101                 *function = COUNTER_FUNCTION_QUADRATURE_X2_B;
 102                 return 0;
 103         case TIM_SMCR_SMS_ENCODER_MODE_3:
 104                 *function = COUNTER_FUNCTION_QUADRATURE_X4;
 105                 return 0;
 106         default:
 107                 return -EINVAL;
 108         }
 109 }
 110
 111 static int stm32_count_function_write(struct counter_device *counter,
 112                                       struct counter_count *count,
 113                                       enum counter_function function)
 114 {
 115         struct stm32_timer_cnt *const priv = counter_priv(counter);
 116         u32 cr1, sms;
 117
 118         switch (function) {
 119         case COUNTER_FUNCTION_INCREASE:
 120                 sms = TIM_SMCR_SMS_SLAVE_MODE_DISABLED;
 121                 break;
 122         case COUNTER_FUNCTION_QUADRATURE_X2_A:
 123                 if (!priv->has_encoder)
 124                         return -EOPNOTSUPP;
 125                 sms = TIM_SMCR_SMS_ENCODER_MODE_1;
 126                 break;
 127         case COUNTER_FUNCTION_QUADRATURE_X2_B:
 128                 if (!priv->has_encoder)
 129                         return -EOPNOTSUPP;
 130                 sms = TIM_SMCR_SMS_ENCODER_MODE_2;
 131                 break;
 132         case COUNTER_FUNCTION_QUADRATURE_X4:
 133                 if (!priv->has_encoder)
 134                         return -EOPNOTSUPP;
 135                 sms = TIM_SMCR_SMS_ENCODER_MODE_3;
 136                 break;
 137         default:
 138                 return -EINVAL;
 139         }
 140
 141         /* Store enable status */
 142         regmap_read(priv->regmap, TIM_CR1, &cr1);
 143
 144         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
 145
 146         regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms);
 147
 148         /* Make sure that registers are updated */
 149         regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
 150
 151         /* Restore the enable status */
 152         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, cr1);
 153
 154         return 0;
 155 }
 156
 157 static int stm32_count_direction_read(struct counter_device *counter,
 158                                       struct counter_count *count,
 159                                       enum counter_count_direction *direction)
 160 {
 161         struct stm32_timer_cnt *const priv = counter_priv(counter);
 162         u32 cr1;
 163
 164         regmap_read(priv->regmap, TIM_CR1, &cr1);
 165         *direction = (cr1 & TIM_CR1_DIR) ? COUNTER_COUNT_DIRECTION_BACKWARD :
 166                 COUNTER_COUNT_DIRECTION_FORWARD;
 167
 168         return 0;
 169 }
 170
 171 static int stm32_count_ceiling_read(struct counter_device *counter,
 172                                     struct counter_count *count, u64 *ceiling)
 173 {
 174         struct stm32_timer_cnt *const priv = counter_priv(counter);
 175         u32 arr;
 176
 177         regmap_read(priv->regmap, TIM_ARR, &arr);
 178
 179         *ceiling = arr;
 180
 181         return 0;
 182 }
 183
 184 static int stm32_count_ceiling_write(struct counter_device *counter,
 185                                      struct counter_count *count, u64 ceiling)
 186 {
 187         struct stm32_timer_cnt *const priv = counter_priv(counter);
 188
 189         if (ceiling > priv->max_arr)
 190                 return -ERANGE;
 191
 192         /* TIMx_ARR register shouldn't be buffered (ARPE=0) */
 193         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
 194         regmap_write(priv->regmap, TIM_ARR, ceiling);
 195
 196         return 0;
 197 }
 198
 199 static int stm32_count_enable_read(struct counter_device *counter,
 200                                    struct counter_count *count, u8 *enable)
 201 {
 202         struct stm32_timer_cnt *const priv = counter_priv(counter);
 203         u32 cr1;
 204
 205         regmap_read(priv->regmap, TIM_CR1, &cr1);
 206
 207         *enable = cr1 & TIM_CR1_CEN;
 208
 209         return 0;
 210 }
 211
 212 static int stm32_count_enable_write(struct counter_device *counter,
 213                                     struct counter_count *count, u8 enable)
 214 {
 215         struct stm32_timer_cnt *const priv = counter_priv(counter);
 216         u32 cr1;
 217         int ret;
 218
 219         if (enable) {
 220                 regmap_read(priv->regmap, TIM_CR1, &cr1);
 221                 if (!(cr1 & TIM_CR1_CEN)) {
 222                         ret = clk_enable(priv->clk);
 223                         if (ret) {
 224                                 dev_err(counter->parent, "Cannot enable clock %d\n", ret);
 225                                 return ret;
 226                         }
 227                 }
 228
 229                 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,
 230                                    TIM_CR1_CEN);
 231         } else {
 232                 regmap_read(priv->regmap, TIM_CR1, &cr1);
 233                 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
 234                 if (cr1 & TIM_CR1_CEN)
 235                         clk_disable(priv->clk);
 236         }
 237
 238         /* Keep enabled state to properly handle low power states */
 239         priv->enabled = enable;
 240
 241         return 0;
 242 }
 243
 244 static int stm32_count_prescaler_read(struct counter_device *counter,
 245                                       struct counter_count *count, u64 *prescaler)
 246 {
 247         struct stm32_timer_cnt *const priv = counter_priv(counter);
 248         u32 psc;
 249
 250         regmap_read(priv->regmap, TIM_PSC, &psc);
 251
 252         *prescaler = psc + 1;
 253
 254         return 0;
 255 }
 256
 257 static int stm32_count_prescaler_write(struct counter_device *counter,
 258                                        struct counter_count *count, u64 prescaler)
 259 {
 260         struct stm32_timer_cnt *const priv = counter_priv(counter);
 261         u32 psc;
 262
 263         if (!prescaler || prescaler > MAX_TIM_PSC + 1)
 264                 return -ERANGE;
 265
 266         psc = prescaler - 1;
 267
 268         return regmap_write(priv->regmap, TIM_PSC, psc);
 269 }
 270
 271 static int stm32_count_cap_read(struct counter_device *counter,
 272                                 struct counter_count *count,
 273                                 size_t ch, u64 *cap)
 274 {
 275         struct stm32_timer_cnt *const priv = counter_priv(counter);
 276         u32 ccrx;
 277
 278         if (ch >= priv->nchannels)
 279                 return -EOPNOTSUPP;
 280
 281         switch (ch) {
 282         case 0:
 283                 regmap_read(priv->regmap, TIM_CCR1, &ccrx);
 284                 break;
 285         case 1:
 286                 regmap_read(priv->regmap, TIM_CCR2, &ccrx);
 287                 break;
 288         case 2:
 289                 regmap_read(priv->regmap, TIM_CCR3, &ccrx);
 290                 break;
 291         case 3:
 292                 regmap_read(priv->regmap, TIM_CCR4, &ccrx);
 293                 break;
 294         default:
 295                 return -EINVAL;
 296         }
 297
 298         dev_dbg(counter->parent, "CCR%zu: 0x%08x\n", ch + 1, ccrx);
 299
 300         *cap = ccrx;
 301
 302         return 0;
 303 }
 304
 305 static int stm32_count_nb_ovf_read(struct counter_device *counter,
 306                                    struct counter_count *count, u64 *val)
 307 {
 308         struct stm32_timer_cnt *const priv = counter_priv(counter);
 309         unsigned long irqflags;
 310
 311         spin_lock_irqsave(&priv->lock, irqflags);
 312         *val = priv->nb_ovf;
 313         spin_unlock_irqrestore(&priv->lock, irqflags);
 314
 315         return 0;
 316 }
 317
 318 static int stm32_count_nb_ovf_write(struct counter_device *counter,
 319                                     struct counter_count *count, u64 val)
 320 {
 321         struct stm32_timer_cnt *const priv = counter_priv(counter);
 322         unsigned long irqflags;
 323
 324         spin_lock_irqsave(&priv->lock, irqflags);
 325         priv->nb_ovf = val;
 326         spin_unlock_irqrestore(&priv->lock, irqflags);
 327
 328         return 0;
 329 }
 330
 331 static DEFINE_COUNTER_ARRAY_CAPTURE(stm32_count_cap_array, 4);
 332
 333 static struct counter_comp stm32_count_ext[] = {
 334         COUNTER_COMP_DIRECTION(stm32_count_direction_read),
 335         COUNTER_COMP_ENABLE(stm32_count_enable_read, stm32_count_enable_write),
 336         COUNTER_COMP_CEILING(stm32_count_ceiling_read,
 337                              stm32_count_ceiling_write),
 338         COUNTER_COMP_COUNT_U64("prescaler", stm32_count_prescaler_read,
 339                                stm32_count_prescaler_write),
 340         COUNTER_COMP_ARRAY_CAPTURE(stm32_count_cap_read, NULL, stm32_count_cap_array),
 341         COUNTER_COMP_COUNT_U64("num_overflows", stm32_count_nb_ovf_read, stm32_count_nb_ovf_write),
 342 };
 343
 344 static const enum counter_synapse_action stm32_clock_synapse_actions[] = {
 345         COUNTER_SYNAPSE_ACTION_RISING_EDGE,
 346 };
 347
 348 static const enum counter_synapse_action stm32_synapse_actions[] = {
 349         COUNTER_SYNAPSE_ACTION_NONE,
 350         COUNTER_SYNAPSE_ACTION_BOTH_EDGES
 351 };
 352
 353 static int stm32_action_read(struct counter_device *counter,
 354                              struct counter_count *count,
 355                              struct counter_synapse *synapse,
 356                              enum counter_synapse_action *action)
 357 {
 358         enum counter_function function;
 359         int err;
 360
 361         err = stm32_count_function_read(counter, count, &function);
 362         if (err)
 363                 return err;
 364
 365         switch (function) {
 366         case COUNTER_FUNCTION_INCREASE:
 367                 /* counts on internal clock when CEN=1 */
 368                 if (synapse->signal->id == STM32_CLOCK_SIG)
 369                         *action = COUNTER_SYNAPSE_ACTION_RISING_EDGE;
 370                 else
 371                         *action = COUNTER_SYNAPSE_ACTION_NONE;
 372                 return 0;
 373         case COUNTER_FUNCTION_QUADRATURE_X2_A:
 374                 /* counts up/down on TI1FP1 edge depending on TI2FP2 level */
 375                 if (synapse->signal->id == STM32_CH1_SIG)
 376                         *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
 377                 else
 378                         *action = COUNTER_SYNAPSE_ACTION_NONE;
 379                 return 0;
 380         case COUNTER_FUNCTION_QUADRATURE_X2_B:
 381                 /* counts up/down on TI2FP2 edge depending on TI1FP1 level */
 382                 if (synapse->signal->id == STM32_CH2_SIG)
 383                         *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
 384                 else
 385                         *action = COUNTER_SYNAPSE_ACTION_NONE;
 386                 return 0;
 387         case COUNTER_FUNCTION_QUADRATURE_X4:
 388                 /* counts up/down on both TI1FP1 and TI2FP2 edges */
 389                 if (synapse->signal->id == STM32_CH1_SIG || synapse->signal->id == STM32_CH2_SIG)
 390                         *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
 391                 else
 392                         *action = COUNTER_SYNAPSE_ACTION_NONE;
 393                 return 0;
 394         default:
 395                 return -EINVAL;
 396         }
 397 }
 398
 399 struct stm32_count_cc_regs {
 400         u32 ccmr_reg;
 401         u32 ccmr_mask;
 402         u32 ccmr_bits;
 403         u32 ccer_bits;
 404 };
 405
 406 static const struct stm32_count_cc_regs stm32_cc[] = {
 407         { TIM_CCMR1, TIM_CCMR_CC1S, TIM_CCMR_CC1S_TI1,
 408                 TIM_CCER_CC1E | TIM_CCER_CC1P | TIM_CCER_CC1NP },
 409         { TIM_CCMR1, TIM_CCMR_CC2S, TIM_CCMR_CC2S_TI2,
 410                 TIM_CCER_CC2E | TIM_CCER_CC2P | TIM_CCER_CC2NP },
 411         { TIM_CCMR2, TIM_CCMR_CC3S, TIM_CCMR_CC3S_TI3,
 412                 TIM_CCER_CC3E | TIM_CCER_CC3P | TIM_CCER_CC3NP },
 413         { TIM_CCMR2, TIM_CCMR_CC4S, TIM_CCMR_CC4S_TI4,
 414                 TIM_CCER_CC4E | TIM_CCER_CC4P | TIM_CCER_CC4NP },
 415 };
 416
 417 static int stm32_count_capture_configure(struct counter_device *counter, unsigned int ch,
 418                                          bool enable)
 419 {
 420         struct stm32_timer_cnt *const priv = counter_priv(counter);
 421         const struct stm32_count_cc_regs *cc;
 422         u32 ccmr, ccer;
 423
 424         if (ch >= ARRAY_SIZE(stm32_cc) || ch >= priv->nchannels) {
 425                 dev_err(counter->parent, "invalid ch: %d\n", ch);
 426                 return -EINVAL;
 427         }
 428
 429         cc = &stm32_cc[ch];
 430
 431         /*
 432          * configure channel in input capture mode, map channel 1 on TI1, channel2 on TI2...
 433          * Select both edges / non-inverted to trigger a capture.
 434          */
 435         if (enable) {
 436                 /* first clear possibly latched capture flag upon enabling */
 437                 if (!regmap_test_bits(priv->regmap, TIM_CCER, cc->ccer_bits))
 438                         regmap_write(priv->regmap, TIM_SR, ~TIM_SR_CC_IF(ch));
 439                 regmap_update_bits(priv->regmap, cc->ccmr_reg, cc->ccmr_mask,
 440                                    cc->ccmr_bits);
 441                 regmap_set_bits(priv->regmap, TIM_CCER, cc->ccer_bits);
 442         } else {
 443                 regmap_clear_bits(priv->regmap, TIM_CCER, cc->ccer_bits);
 444                 regmap_clear_bits(priv->regmap, cc->ccmr_reg, cc->ccmr_mask);
 445         }
 446
 447         regmap_read(priv->regmap, cc->ccmr_reg, &ccmr);
 448         regmap_read(priv->regmap, TIM_CCER, &ccer);
 449         dev_dbg(counter->parent, "%s(%s) ch%d 0x%08x 0x%08x\n", __func__, enable ? "ena" : "dis",
 450                 ch, ccmr, ccer);
 451
 452         return 0;
 453 }
 454
 455 static int stm32_count_events_configure(struct counter_device *counter)
 456 {
 457         struct stm32_timer_cnt *const priv = counter_priv(counter);
 458         struct counter_event_node *event_node;
 459         u32 dier = 0;
 460         int i, ret;
 461
 462         list_for_each_entry(event_node, &counter->events_list, l) {
 463                 switch (event_node->event) {
 464                 case COUNTER_EVENT_OVERFLOW_UNDERFLOW:
 465                         /* first clear possibly latched UIF before enabling */
 466                         if (!regmap_test_bits(priv->regmap, TIM_DIER, TIM_DIER_UIE))
 467                                 regmap_write(priv->regmap, TIM_SR, (u32)~TIM_SR_UIF);
 468                         dier |= TIM_DIER_UIE;
 469                         break;
 470                 case COUNTER_EVENT_CAPTURE:
 471                         ret = stm32_count_capture_configure(counter, event_node->channel, true);
 472                         if (ret)
 473                                 return ret;
 474                         dier |= TIM_DIER_CCxIE(event_node->channel + 1);
 475                         break;
 476                 default:
 477                         /* should never reach this path */
 478                         return -EINVAL;
 479                 }
 480         }
 481
 482         /* Enable / disable all events at once, from events_list, so write all DIER bits */
 483         regmap_write(priv->regmap, TIM_DIER, dier);
 484
 485         /* check for disabled capture events */
 486         for (i = 0 ; i < priv->nchannels; i++) {
 487                 if (!(dier & TIM_DIER_CCxIE(i + 1))) {
 488                         ret = stm32_count_capture_configure(counter, i, false);
 489                         if (ret)
 490                                 return ret;
 491                 }
 492         }
 493
 494         return 0;
 495 }
 496
 497 static int stm32_count_watch_validate(struct counter_device *counter,
 498                                       const struct counter_watch *watch)
 499 {
 500         struct stm32_timer_cnt *const priv = counter_priv(counter);
 501
 502         /* Interrupts are optional */
 503         if (!priv->nr_irqs)
 504                 return -EOPNOTSUPP;
 505
 506         switch (watch->event) {
 507         case COUNTER_EVENT_CAPTURE:
 508                 if (watch->channel >= priv->nchannels) {
 509                         dev_err(counter->parent, "Invalid channel %d\n", watch->channel);
 510                         return -EINVAL;
 511                 }
 512                 return 0;
 513         case COUNTER_EVENT_OVERFLOW_UNDERFLOW:
 514                 return 0;
 515         default:
 516                 return -EINVAL;
 517         }
 518 }
 519
 520 static const struct counter_ops stm32_timer_cnt_ops = {
 521         .count_read = stm32_count_read,
 522         .count_write = stm32_count_write,
 523         .function_read = stm32_count_function_read,
 524         .function_write = stm32_count_function_write,
 525         .action_read = stm32_action_read,
 526         .events_configure = stm32_count_events_configure,
 527         .watch_validate = stm32_count_watch_validate,
 528 };
 529
 530 static int stm32_count_clk_get_freq(struct counter_device *counter,
 531                                     struct counter_signal *signal, u64 *freq)
 532 {
 533         struct stm32_timer_cnt *const priv = counter_priv(counter);
 534
 535         *freq = clk_get_rate(priv->clk);
 536
 537         return 0;
 538 }
 539
 540 static struct counter_comp stm32_count_clock_ext[] = {
 541         COUNTER_COMP_FREQUENCY(stm32_count_clk_get_freq),
 542 };
 543
 544 static struct counter_signal stm32_signals[] = {
 545         /*
 546          * Need to declare all the signals as a static array, and keep the signals order here,
 547          * even if they're unused or unexisting on some timer instances. It's an abstraction,
 548          * e.g. high level view of the counter features.
 549          *
 550          * Userspace programs may rely on signal0 to be "Channel 1", signal1 to be "Channel 2",
 551          * and so on. When a signal is unexisting, the COUNTER_SYNAPSE_ACTION_NONE can be used,
 552          * to indicate that a signal doesn't affect the counter.
 553          */
 554         {
 555                 .id = STM32_CH1_SIG,
 556                 .name = "Channel 1"
 557         },
 558         {
 559                 .id = STM32_CH2_SIG,
 560                 .name = "Channel 2"
 561         },
 562         {
 563                 .id = STM32_CLOCK_SIG,
 564                 .name = "Clock",
 565                 .ext = stm32_count_clock_ext,
 566                 .num_ext = ARRAY_SIZE(stm32_count_clock_ext),
 567         },
 568         {
 569                 .id = STM32_CH3_SIG,
 570                 .name = "Channel 3"
 571         },
 572         {
 573                 .id = STM32_CH4_SIG,
 574                 .name = "Channel 4"
 575         },
 576 };
 577
 578 static struct counter_synapse stm32_count_synapses[] = {
 579         {
 580                 .actions_list = stm32_synapse_actions,
 581                 .num_actions = ARRAY_SIZE(stm32_synapse_actions),
 582                 .signal = &stm32_signals[STM32_CH1_SIG]
 583         },
 584         {
 585                 .actions_list = stm32_synapse_actions,
 586                 .num_actions = ARRAY_SIZE(stm32_synapse_actions),
 587                 .signal = &stm32_signals[STM32_CH2_SIG]
 588         },
 589         {
 590                 .actions_list = stm32_clock_synapse_actions,
 591                 .num_actions = ARRAY_SIZE(stm32_clock_synapse_actions),
 592                 .signal = &stm32_signals[STM32_CLOCK_SIG]
 593         },
 594         {
 595                 .actions_list = stm32_synapse_actions,
 596                 .num_actions = ARRAY_SIZE(stm32_synapse_actions),
 597                 .signal = &stm32_signals[STM32_CH3_SIG]
 598         },
 599         {
 600                 .actions_list = stm32_synapse_actions,
 601                 .num_actions = ARRAY_SIZE(stm32_synapse_actions),
 602                 .signal = &stm32_signals[STM32_CH4_SIG]
 603         },
 604 };
 605
 606 static struct counter_count stm32_counts = {
 607         .id = 0,
 608         .name = "STM32 Timer Counter",
 609         .functions_list = stm32_count_functions,
 610         .num_functions = ARRAY_SIZE(stm32_count_functions),
 611         .synapses = stm32_count_synapses,
 612         .num_synapses = ARRAY_SIZE(stm32_count_synapses),
 613         .ext = stm32_count_ext,
 614         .num_ext = ARRAY_SIZE(stm32_count_ext)
 615 };
 616
 617 static irqreturn_t stm32_timer_cnt_isr(int irq, void *ptr)
 618 {
 619         struct counter_device *counter = ptr;
 620         struct stm32_timer_cnt *const priv = counter_priv(counter);
 621         u32 clr = GENMASK(31, 0); /* SR flags can be cleared by writing 0 (wr 1 has no effect) */
 622         u32 sr, dier;
 623         int i;
 624
 625         regmap_read(priv->regmap, TIM_SR, &sr);
 626         regmap_read(priv->regmap, TIM_DIER, &dier);
 627         /*
 628          * Some status bits in SR don't match with the enable bits in DIER. Only take care of
 629          * the possibly enabled bits in DIER (that matches in between SR and DIER).
 630          */
 631         dier &= (TIM_DIER_UIE | TIM_DIER_CC1IE | TIM_DIER_CC2IE | TIM_DIER_CC3IE | TIM_DIER_CC4IE);
 632         sr &= dier;
 633
 634         if (sr & TIM_SR_UIF) {
 635                 spin_lock(&priv->lock);
 636                 priv->nb_ovf++;
 637                 spin_unlock(&priv->lock);
 638                 counter_push_event(counter, COUNTER_EVENT_OVERFLOW_UNDERFLOW, 0);
 639                 dev_dbg(counter->parent, "COUNTER_EVENT_OVERFLOW_UNDERFLOW\n");
 640                 /* SR flags can be cleared by writing 0, only clear relevant flag */
 641                 clr &= ~TIM_SR_UIF;
 642         }
 643
 644         /* Check capture events */
 645         for (i = 0 ; i < priv->nchannels; i++) {
 646                 if (sr & TIM_SR_CC_IF(i)) {
 647                         counter_push_event(counter, COUNTER_EVENT_CAPTURE, i);
 648                         clr &= ~TIM_SR_CC_IF(i);
 649                         dev_dbg(counter->parent, "COUNTER_EVENT_CAPTURE, %d\n", i);
 650                 }
 651         }
 652
 653         regmap_write(priv->regmap, TIM_SR, clr);
 654
 655         return IRQ_HANDLED;
 656 };
 657
 658 static void stm32_timer_cnt_detect_channels(struct device *dev,
 659                                             struct stm32_timer_cnt *priv)
 660 {
 661         u32 ccer, ccer_backup;
 662
 663         regmap_read(priv->regmap, TIM_CCER, &ccer_backup);
 664         regmap_set_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE);
 665         regmap_read(priv->regmap, TIM_CCER, &ccer);
 666         regmap_write(priv->regmap, TIM_CCER, ccer_backup);
 667         priv->nchannels = hweight32(ccer & TIM_CCER_CCXE);
 668
 669         dev_dbg(dev, "has %d cc channels\n", priv->nchannels);
 670 }
 671
 672 /* encoder supported on TIM1 TIM2 TIM3 TIM4 TIM5 TIM8 */
 673 #define STM32_TIM_ENCODER_SUPPORTED     (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(7))
 674
 675 static const char * const stm32_timer_trigger_compat[] = {
 676         "st,stm32-timer-trigger",
 677         "st,stm32h7-timer-trigger",
 678 };
 679
 680 static int stm32_timer_cnt_probe_encoder(struct device *dev,
 681                                          struct stm32_timer_cnt *priv)
 682 {
 683         struct device *parent = dev->parent;
 684         struct device_node *tnode = NULL, *pnode = parent->of_node;
 685         int i, ret;
 686         u32 idx;
 687
 688         /*
 689          * Need to retrieve the trigger node index from DT, to be able
 690          * to determine if the counter supports encoder mode. It also
 691          * enforce backward compatibility, and allow to support other
 692          * counter modes in this driver (when the timer doesn't support
 693          * encoder).
 694          */
 695         for (i = 0; i < ARRAY_SIZE(stm32_timer_trigger_compat) && !tnode; i++)
 696                 tnode = of_get_compatible_child(pnode, stm32_timer_trigger_compat[i]);
 697         if (!tnode) {
 698                 dev_err(dev, "Can't find trigger node\n");
 699                 return -ENODATA;
 700         }
 701
 702         ret = of_property_read_u32(tnode, "reg", &idx);
 703         of_node_put(tnode);
 704         if (ret) {
 705                 dev_err(dev, "Can't get index (%d)\n", ret);
 706                 return ret;
 707         }
 708
 709         priv->has_encoder = !!(STM32_TIM_ENCODER_SUPPORTED & BIT(idx));
 710
 711         dev_dbg(dev, "encoder support: %s\n", priv->has_encoder ? "yes" : "no");
 712
 713         return 0;
 714 }
 715
 716 static int stm32_timer_cnt_probe(struct platform_device *pdev)
 717 {
 718         struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
 719         struct device *dev = &pdev->dev;
 720         struct stm32_timer_cnt *priv;
 721         struct counter_device *counter;
 722         int i, ret;
 723
 724         if (IS_ERR_OR_NULL(ddata))
 725                 return -EINVAL;
 726
 727         counter = devm_counter_alloc(dev, sizeof(*priv));
 728         if (!counter)
 729                 return -ENOMEM;
 730
 731         priv = counter_priv(counter);
 732
 733         priv->regmap = ddata->regmap;
 734         priv->clk = ddata->clk;
 735         priv->max_arr = ddata->max_arr;
 736         priv->nr_irqs = ddata->nr_irqs;
 737
 738         ret = stm32_timer_cnt_probe_encoder(dev, priv);
 739         if (ret)
 740                 return ret;
 741
 742         stm32_timer_cnt_detect_channels(dev, priv);
 743
 744         counter->name = dev_name(dev);
 745         counter->parent = dev;
 746         counter->ops = &stm32_timer_cnt_ops;
 747         counter->counts = &stm32_counts;
 748         counter->num_counts = 1;
 749         counter->signals = stm32_signals;
 750         counter->num_signals = ARRAY_SIZE(stm32_signals);
 751
 752         spin_lock_init(&priv->lock);
 753
 754         platform_set_drvdata(pdev, priv);
 755
 756         /* STM32 Timers can have either 1 global, or 4 dedicated interrupts (optional) */
 757         if (priv->nr_irqs == 1) {
 758                 /* All events reported through the global interrupt */
 759                 ret = devm_request_irq(&pdev->dev, ddata->irq[0], stm32_timer_cnt_isr,
 760                                        0, dev_name(dev), counter);
 761                 if (ret) {
 762                         dev_err(dev, "Failed to request irq %d (err %d)\n",
 763                                 ddata->irq[0], ret);
 764                         return ret;
 765                 }
 766         } else {
 767                 for (i = 0; i < priv->nr_irqs; i++) {
 768                         /*
 769                          * Only take care of update IRQ for overflow events, and cc for
 770                          * capture events.
 771                          */
 772                         if (i != STM32_TIMERS_IRQ_UP && i != STM32_TIMERS_IRQ_CC)
 773                                 continue;
 774
 775                         ret = devm_request_irq(&pdev->dev, ddata->irq[i], stm32_timer_cnt_isr,
 776                                                0, dev_name(dev), counter);
 777                         if (ret) {
 778                                 dev_err(dev, "Failed to request irq %d (err %d)\n",
 779                                         ddata->irq[i], ret);
 780                                 return ret;
 781                         }
 782                 }
 783         }
 784
 785         /* Reset input selector to its default input */
 786         regmap_write(priv->regmap, TIM_TISEL, 0x0);
 787
 788         /* Register Counter device */
 789         ret = devm_counter_add(dev, counter);
 790         if (ret < 0)
 791                 dev_err_probe(dev, ret, "Failed to add counter\n");
 792
 793         return ret;
 794 }
 795
 796 static int __maybe_unused stm32_timer_cnt_suspend(struct device *dev)
 797 {
 798         struct stm32_timer_cnt *priv = dev_get_drvdata(dev);
 799
 800         /* Only take care of enabled counter: don't disturb other MFD child */
 801         if (priv->enabled) {
 802                 /* Backup registers that may get lost in low power mode */
 803                 regmap_read(priv->regmap, TIM_SMCR, &priv->bak.smcr);
 804                 regmap_read(priv->regmap, TIM_ARR, &priv->bak.arr);
 805                 regmap_read(priv->regmap, TIM_CNT, &priv->bak.cnt);
 806                 regmap_read(priv->regmap, TIM_CR1, &priv->bak.cr1);
 807
 808                 /* Disable the counter */
 809                 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
 810                 clk_disable(priv->clk);
 811         }
 812
 813         return pinctrl_pm_select_sleep_state(dev);
 814 }
 815
 816 static int __maybe_unused stm32_timer_cnt_resume(struct device *dev)
 817 {
 818         struct stm32_timer_cnt *priv = dev_get_drvdata(dev);
 819         int ret;
 820
 821         ret = pinctrl_pm_select_default_state(dev);
 822         if (ret)
 823                 return ret;
 824
 825         if (priv->enabled) {
 826                 ret = clk_enable(priv->clk);
 827                 if (ret) {
 828                         dev_err(dev, "Cannot enable clock %d\n", ret);
 829                         return ret;
 830                 }
 831
 832                 /* Restore registers that may have been lost */
 833                 regmap_write(priv->regmap, TIM_SMCR, priv->bak.smcr);
 834                 regmap_write(priv->regmap, TIM_ARR, priv->bak.arr);
 835                 regmap_write(priv->regmap, TIM_CNT, priv->bak.cnt);
 836
 837                 /* Also re-enables the counter */
 838                 regmap_write(priv->regmap, TIM_CR1, priv->bak.cr1);
 839         }
 840
 841         return 0;
 842 }
 843
 844 static SIMPLE_DEV_PM_OPS(stm32_timer_cnt_pm_ops, stm32_timer_cnt_suspend,
 845                          stm32_timer_cnt_resume);
 846
 847 static const struct of_device_id stm32_timer_cnt_of_match[] = {
 848         { .compatible = "st,stm32-timer-counter", },
 849         {},
 850 };
 851 MODULE_DEVICE_TABLE(of, stm32_timer_cnt_of_match);
 852
 853 static struct platform_driver stm32_timer_cnt_driver = {
 854         .probe = stm32_timer_cnt_probe,
 855         .driver = {
 856                 .name = "stm32-timer-counter",
 857                 .of_match_table = stm32_timer_cnt_of_match,
 858                 .pm = &stm32_timer_cnt_pm_ops,
 859         },
 860 };
 861 module_platform_driver(stm32_timer_cnt_driver);
 862
 863 MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
 864 MODULE_ALIAS("platform:stm32-timer-counter");
 865 MODULE_DESCRIPTION("STMicroelectronics STM32 TIMER counter driver");
 866 MODULE_LICENSE("GPL v2");
 867 MODULE_IMPORT_NS(COUNTER);