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Merge tag 'trace-printf-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/trace...
[drm/drm-misc.git] / drivers / spi / spi-geni-qcom.c
blob768d7482102adec9b7178077724dc3976a2760c8
1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
3
4 #include <linux/clk.h>
5 #include <linux/dmaengine.h>
6 #include <linux/dma-mapping.h>
7 #include <linux/dma/qcom-gpi-dma.h>
8 #include <linux/interrupt.h>
9 #include <linux/io.h>
10 #include <linux/log2.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <linux/pm_opp.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/property.h>
16 #include <linux/soc/qcom/geni-se.h>
17 #include <linux/spi/spi.h>
18 #include <linux/spinlock.h>
19
20 /* SPI SE specific registers and respective register fields */
21 #define SE_SPI_CPHA 0x224
22 #define CPHA BIT(0)
23
24 #define SE_SPI_LOOPBACK 0x22c
25 #define LOOPBACK_ENABLE 0x1
26 #define NORMAL_MODE 0x0
27 #define LOOPBACK_MSK GENMASK(1, 0)
28
29 #define SE_SPI_CPOL 0x230
30 #define CPOL BIT(2)
31
32 #define SE_SPI_DEMUX_OUTPUT_INV 0x24c
33 #define CS_DEMUX_OUTPUT_INV_MSK GENMASK(3, 0)
34
35 #define SE_SPI_DEMUX_SEL 0x250
36 #define CS_DEMUX_OUTPUT_SEL GENMASK(3, 0)
37
38 #define SE_SPI_TRANS_CFG 0x25c
39 #define CS_TOGGLE BIT(1)
40
41 #define SE_SPI_WORD_LEN 0x268
42 #define WORD_LEN_MSK GENMASK(9, 0)
43 #define MIN_WORD_LEN 4
44
45 #define SE_SPI_TX_TRANS_LEN 0x26c
46 #define SE_SPI_RX_TRANS_LEN 0x270
47 #define TRANS_LEN_MSK GENMASK(23, 0)
48
49 #define SE_SPI_PRE_POST_CMD_DLY 0x274
50
51 #define SE_SPI_DELAY_COUNTERS 0x278
52 #define SPI_INTER_WORDS_DELAY_MSK GENMASK(9, 0)
53 #define SPI_CS_CLK_DELAY_MSK GENMASK(19, 10)
54 #define SPI_CS_CLK_DELAY_SHFT 10
55
56 #define SE_SPI_SLAVE_EN (0x2BC)
57 #define SPI_SLAVE_EN BIT(0)
58
59 /* M_CMD OP codes for SPI */
60 #define SPI_TX_ONLY 1
61 #define SPI_RX_ONLY 2
62 #define SPI_TX_RX 7
63 #define SPI_CS_ASSERT 8
64 #define SPI_CS_DEASSERT 9
65 #define SPI_SCK_ONLY 10
66 /* M_CMD params for SPI */
67 #define SPI_PRE_CMD_DELAY BIT(0)
68 #define TIMESTAMP_BEFORE BIT(1)
69 #define FRAGMENTATION BIT(2)
70 #define TIMESTAMP_AFTER BIT(3)
71 #define POST_CMD_DELAY BIT(4)
72
73 #define GSI_LOOPBACK_EN BIT(0)
74 #define GSI_CS_TOGGLE BIT(3)
75 #define GSI_CPHA BIT(4)
76 #define GSI_CPOL BIT(5)
77
78 struct spi_geni_master {
79 struct geni_se se;
80 struct device *dev;
81 u32 tx_fifo_depth;
82 u32 fifo_width_bits;
83 u32 tx_wm;
84 u32 last_mode;
85 unsigned long cur_speed_hz;
86 unsigned long cur_sclk_hz;
87 unsigned int cur_bits_per_word;
88 unsigned int tx_rem_bytes;
89 unsigned int rx_rem_bytes;
90 const struct spi_transfer *cur_xfer;
91 struct completion cs_done;
92 struct completion cancel_done;
93 struct completion abort_done;
94 struct completion tx_reset_done;
95 struct completion rx_reset_done;
96 unsigned int oversampling;
97 spinlock_t lock;
98 int irq;
99 bool cs_flag;
100 bool abort_failed;
101 struct dma_chan *tx;
102 struct dma_chan *rx;
103 int cur_xfer_mode;
104 };
105
106 static void spi_slv_setup(struct spi_geni_master *mas)
107 {
108 struct geni_se *se = &mas->se;
109
110 writel(SPI_SLAVE_EN, se->base + SE_SPI_SLAVE_EN);
111 writel(GENI_IO_MUX_0_EN, se->base + GENI_OUTPUT_CTRL);
112 writel(START_TRIGGER, se->base + SE_GENI_CFG_SEQ_START);
113 dev_dbg(mas->dev, "spi slave setup done\n");
114 }
115
116 static int get_spi_clk_cfg(unsigned int speed_hz,
117 struct spi_geni_master *mas,
118 unsigned int *clk_idx,
119 unsigned int *clk_div)
120 {
121 unsigned long sclk_freq;
122 unsigned int actual_hz;
123 int ret;
124
125 ret = geni_se_clk_freq_match(&mas->se,
126 speed_hz * mas->oversampling,
127 clk_idx, &sclk_freq, false);
128 if (ret) {
129 dev_err(mas->dev, "Failed(%d) to find src clk for %dHz\n",
130 ret, speed_hz);
131 return ret;
132 }
133
134 *clk_div = DIV_ROUND_UP(sclk_freq, mas->oversampling * speed_hz);
135 actual_hz = sclk_freq / (mas->oversampling * *clk_div);
136
137 dev_dbg(mas->dev, "req %u=>%u sclk %lu, idx %d, div %d\n", speed_hz,
138 actual_hz, sclk_freq, *clk_idx, *clk_div);
139 ret = dev_pm_opp_set_rate(mas->dev, sclk_freq);
140 if (ret)
141 dev_err(mas->dev, "dev_pm_opp_set_rate failed %d\n", ret);
142 else
143 mas->cur_sclk_hz = sclk_freq;
144
145 return ret;
146 }
147
148 static void handle_se_timeout(struct spi_controller *spi,
149 struct spi_message *msg)
150 {
151 struct spi_geni_master *mas = spi_controller_get_devdata(spi);
152 unsigned long time_left;
153 struct geni_se *se = &mas->se;
154 const struct spi_transfer *xfer;
155
156 spin_lock_irq(&mas->lock);
157 if (mas->cur_xfer_mode == GENI_SE_FIFO)
158 writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
159
160 xfer = mas->cur_xfer;
161 mas->cur_xfer = NULL;
162
163 if (spi->target) {
164 /*
165 * skip CMD Cancel sequnece since spi target
166 * doesn`t support CMD Cancel sequnece
167 */
168 spin_unlock_irq(&mas->lock);
169 goto reset_if_dma;
170 }
171
172 reinit_completion(&mas->cancel_done);
173 geni_se_cancel_m_cmd(se);
174 spin_unlock_irq(&mas->lock);
175
176 time_left = wait_for_completion_timeout(&mas->cancel_done, HZ);
177 if (time_left)
178 goto reset_if_dma;
179
180 spin_lock_irq(&mas->lock);
181 reinit_completion(&mas->abort_done);
182 geni_se_abort_m_cmd(se);
183 spin_unlock_irq(&mas->lock);
184
185 time_left = wait_for_completion_timeout(&mas->abort_done, HZ);
186 if (!time_left) {
187 dev_err(mas->dev, "Failed to cancel/abort m_cmd\n");
188
189 /*
190 * No need for a lock since SPI core has a lock and we never
191 * access this from an interrupt.
192 */
193 mas->abort_failed = true;
194 }
195
196 reset_if_dma:
197 if (mas->cur_xfer_mode == GENI_SE_DMA) {
198 if (xfer) {
199 if (xfer->tx_buf) {
200 spin_lock_irq(&mas->lock);
201 reinit_completion(&mas->tx_reset_done);
202 writel(1, se->base + SE_DMA_TX_FSM_RST);
203 spin_unlock_irq(&mas->lock);
204 time_left = wait_for_completion_timeout(&mas->tx_reset_done, HZ);
205 if (!time_left)
206 dev_err(mas->dev, "DMA TX RESET failed\n");
207 }
208 if (xfer->rx_buf) {
209 spin_lock_irq(&mas->lock);
210 reinit_completion(&mas->rx_reset_done);
211 writel(1, se->base + SE_DMA_RX_FSM_RST);
212 spin_unlock_irq(&mas->lock);
213 time_left = wait_for_completion_timeout(&mas->rx_reset_done, HZ);
214 if (!time_left)
215 dev_err(mas->dev, "DMA RX RESET failed\n");
216 }
217 } else {
218 /*
219 * This can happen if a timeout happened and we had to wait
220 * for lock in this function because isr was holding the lock
221 * and handling transfer completion at that time.
222 */
223 dev_warn(mas->dev, "Cancel/Abort on completed SPI transfer\n");
224 }
225 }
226 }
227
228 static void handle_gpi_timeout(struct spi_controller *spi, struct spi_message *msg)
229 {
230 struct spi_geni_master *mas = spi_controller_get_devdata(spi);
231
232 dmaengine_terminate_sync(mas->tx);
233 dmaengine_terminate_sync(mas->rx);
234 }
235
236 static void spi_geni_handle_err(struct spi_controller *spi, struct spi_message *msg)
237 {
238 struct spi_geni_master *mas = spi_controller_get_devdata(spi);
239
240 switch (mas->cur_xfer_mode) {
241 case GENI_SE_FIFO:
242 case GENI_SE_DMA:
243 handle_se_timeout(spi, msg);
244 break;
245 case GENI_GPI_DMA:
246 handle_gpi_timeout(spi, msg);
247 break;
248 default:
249 dev_err(mas->dev, "Abort on Mode:%d not supported", mas->cur_xfer_mode);
250 }
251 }
252
253 static bool spi_geni_is_abort_still_pending(struct spi_geni_master *mas)
254 {
255 struct geni_se *se = &mas->se;
256 u32 m_irq, m_irq_en;
257
258 if (!mas->abort_failed)
259 return false;
260
261 /*
262 * The only known case where a transfer times out and then a cancel
263 * times out then an abort times out is if something is blocking our
264 * interrupt handler from running. Avoid starting any new transfers
265 * until that sorts itself out.
266 */
267 spin_lock_irq(&mas->lock);
268 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS);
269 m_irq_en = readl(se->base + SE_GENI_M_IRQ_EN);
270 spin_unlock_irq(&mas->lock);
271
272 if (m_irq & m_irq_en) {
273 dev_err(mas->dev, "Interrupts pending after abort: %#010x\n",
274 m_irq & m_irq_en);
275 return true;
276 }
277
278 /*
279 * If we're here the problem resolved itself so no need to check more
280 * on future transfers.
281 */
282 mas->abort_failed = false;
283
284 return false;
285 }
286
287 static void spi_geni_set_cs(struct spi_device *slv, bool set_flag)
288 {
289 struct spi_geni_master *mas = spi_controller_get_devdata(slv->controller);
290 struct spi_controller *spi = dev_get_drvdata(mas->dev);
291 struct geni_se *se = &mas->se;
292 unsigned long time_left;
293
294 if (!(slv->mode & SPI_CS_HIGH))
295 set_flag = !set_flag;
296
297 if (set_flag == mas->cs_flag)
298 return;
299
300 pm_runtime_get_sync(mas->dev);
301
302 if (spi_geni_is_abort_still_pending(mas)) {
303 dev_err(mas->dev, "Can't set chip select\n");
304 goto exit;
305 }
306
307 spin_lock_irq(&mas->lock);
308 if (mas->cur_xfer) {
309 dev_err(mas->dev, "Can't set CS when prev xfer running\n");
310 spin_unlock_irq(&mas->lock);
311 goto exit;
312 }
313
314 mas->cs_flag = set_flag;
315 /* set xfer_mode to FIFO to complete cs_done in isr */
316 mas->cur_xfer_mode = GENI_SE_FIFO;
317 geni_se_select_mode(se, mas->cur_xfer_mode);
318
319 reinit_completion(&mas->cs_done);
320 if (set_flag)
321 geni_se_setup_m_cmd(se, SPI_CS_ASSERT, 0);
322 else
323 geni_se_setup_m_cmd(se, SPI_CS_DEASSERT, 0);
324 spin_unlock_irq(&mas->lock);
325
326 time_left = wait_for_completion_timeout(&mas->cs_done, HZ);
327 if (!time_left) {
328 dev_warn(mas->dev, "Timeout setting chip select\n");
329 handle_se_timeout(spi, NULL);
330 }
331
332 exit:
333 pm_runtime_put(mas->dev);
334 }
335
336 static void spi_setup_word_len(struct spi_geni_master *mas, u16 mode,
337 unsigned int bits_per_word)
338 {
339 unsigned int pack_words;
340 bool msb_first = (mode & SPI_LSB_FIRST) ? false : true;
341 struct geni_se *se = &mas->se;
342 u32 word_len;
343
344 /*
345 * If bits_per_word isn't a byte aligned value, set the packing to be
346 * 1 SPI word per FIFO word.
347 */
348 if (!(mas->fifo_width_bits % bits_per_word))
349 pack_words = mas->fifo_width_bits / bits_per_word;
350 else
351 pack_words = 1;
352 geni_se_config_packing(&mas->se, bits_per_word, pack_words, msb_first,
353 true, true);
354 word_len = (bits_per_word - MIN_WORD_LEN) & WORD_LEN_MSK;
355 writel(word_len, se->base + SE_SPI_WORD_LEN);
356 }
357
358 static int geni_spi_set_clock_and_bw(struct spi_geni_master *mas,
359 unsigned long clk_hz)
360 {
361 u32 clk_sel, m_clk_cfg, idx, div;
362 struct geni_se *se = &mas->se;
363 int ret;
364
365 if (clk_hz == mas->cur_speed_hz)
366 return 0;
367
368 ret = get_spi_clk_cfg(clk_hz, mas, &idx, &div);
369 if (ret) {
370 dev_err(mas->dev, "Err setting clk to %lu: %d\n", clk_hz, ret);
371 return ret;
372 }
373
374 /*
375 * SPI core clock gets configured with the requested frequency
376 * or the frequency closer to the requested frequency.
377 * For that reason requested frequency is stored in the
378 * cur_speed_hz and referred in the consecutive transfer instead
379 * of calling clk_get_rate() API.
380 */
381 mas->cur_speed_hz = clk_hz;
382
383 clk_sel = idx & CLK_SEL_MSK;
384 m_clk_cfg = (div << CLK_DIV_SHFT) | SER_CLK_EN;
385 writel(clk_sel, se->base + SE_GENI_CLK_SEL);
386 writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG);
387
388 /* Set BW quota for CPU as driver supports FIFO mode only. */
389 se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz);
390 ret = geni_icc_set_bw(se);
391 if (ret)
392 return ret;
393
394 return 0;
395 }
396
397 static int setup_fifo_params(struct spi_device *spi_slv,
398 struct spi_controller *spi)
399 {
400 struct spi_geni_master *mas = spi_controller_get_devdata(spi);
401 struct geni_se *se = &mas->se;
402 u32 loopback_cfg = 0, cpol = 0, cpha = 0, demux_output_inv = 0;
403 u32 demux_sel;
404
405 if (mas->last_mode != spi_slv->mode) {
406 if (spi_slv->mode & SPI_LOOP)
407 loopback_cfg = LOOPBACK_ENABLE;
408
409 if (spi_slv->mode & SPI_CPOL)
410 cpol = CPOL;
411
412 if (spi_slv->mode & SPI_CPHA)
413 cpha = CPHA;
414
415 if (spi_slv->mode & SPI_CS_HIGH)
416 demux_output_inv = BIT(spi_get_chipselect(spi_slv, 0));
417
418 demux_sel = spi_get_chipselect(spi_slv, 0);
419 mas->cur_bits_per_word = spi_slv->bits_per_word;
420
421 spi_setup_word_len(mas, spi_slv->mode, spi_slv->bits_per_word);
422 writel(loopback_cfg, se->base + SE_SPI_LOOPBACK);
423 writel(demux_sel, se->base + SE_SPI_DEMUX_SEL);
424 writel(cpha, se->base + SE_SPI_CPHA);
425 writel(cpol, se->base + SE_SPI_CPOL);
426 writel(demux_output_inv, se->base + SE_SPI_DEMUX_OUTPUT_INV);
427
428 mas->last_mode = spi_slv->mode;
429 }
430
431 return geni_spi_set_clock_and_bw(mas, spi_slv->max_speed_hz);
432 }
433
434 static void
435 spi_gsi_callback_result(void *cb, const struct dmaengine_result *result)
436 {
437 struct spi_controller *spi = cb;
438
439 spi->cur_msg->status = -EIO;
440 if (result->result != DMA_TRANS_NOERROR) {
441 dev_err(&spi->dev, "DMA txn failed: %d\n", result->result);
442 spi_finalize_current_transfer(spi);
443 return;
444 }
445
446 if (!result->residue) {
447 spi->cur_msg->status = 0;
448 dev_dbg(&spi->dev, "DMA txn completed\n");
449 } else {
450 dev_err(&spi->dev, "DMA xfer has pending: %d\n", result->residue);
451 }
452
453 spi_finalize_current_transfer(spi);
454 }
455
456 static int setup_gsi_xfer(struct spi_transfer *xfer, struct spi_geni_master *mas,
457 struct spi_device *spi_slv, struct spi_controller *spi)
458 {
459 unsigned long flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK;
460 struct dma_slave_config config = {};
461 struct gpi_spi_config peripheral = {};
462 struct dma_async_tx_descriptor *tx_desc, *rx_desc;
463 int ret;
464
465 config.peripheral_config = &peripheral;
466 config.peripheral_size = sizeof(peripheral);
467 peripheral.set_config = true;
468
469 if (xfer->bits_per_word != mas->cur_bits_per_word ||
470 xfer->speed_hz != mas->cur_speed_hz) {
471 mas->cur_bits_per_word = xfer->bits_per_word;
472 mas->cur_speed_hz = xfer->speed_hz;
473 }
474
475 if (xfer->tx_buf && xfer->rx_buf) {
476 peripheral.cmd = SPI_DUPLEX;
477 } else if (xfer->tx_buf) {
478 peripheral.cmd = SPI_TX;
479 peripheral.rx_len = 0;
480 } else if (xfer->rx_buf) {
481 peripheral.cmd = SPI_RX;
482 if (!(mas->cur_bits_per_word % MIN_WORD_LEN)) {
483 peripheral.rx_len = ((xfer->len << 3) / mas->cur_bits_per_word);
484 } else {
485 int bytes_per_word = (mas->cur_bits_per_word / BITS_PER_BYTE) + 1;
486
487 peripheral.rx_len = (xfer->len / bytes_per_word);
488 }
489 }
490
491 peripheral.loopback_en = !!(spi_slv->mode & SPI_LOOP);
492 peripheral.clock_pol_high = !!(spi_slv->mode & SPI_CPOL);
493 peripheral.data_pol_high = !!(spi_slv->mode & SPI_CPHA);
494 peripheral.cs = spi_get_chipselect(spi_slv, 0);
495 peripheral.pack_en = true;
496 peripheral.word_len = xfer->bits_per_word - MIN_WORD_LEN;
497
498 ret = get_spi_clk_cfg(mas->cur_speed_hz, mas,
499 &peripheral.clk_src, &peripheral.clk_div);
500 if (ret) {
501 dev_err(mas->dev, "Err in get_spi_clk_cfg() :%d\n", ret);
502 return ret;
503 }
504
505 if (!xfer->cs_change) {
506 if (!list_is_last(&xfer->transfer_list, &spi->cur_msg->transfers))
507 peripheral.fragmentation = FRAGMENTATION;
508 }
509
510 if (peripheral.cmd & SPI_RX) {
511 dmaengine_slave_config(mas->rx, &config);
512 rx_desc = dmaengine_prep_slave_sg(mas->rx, xfer->rx_sg.sgl, xfer->rx_sg.nents,
513 DMA_DEV_TO_MEM, flags);
514 if (!rx_desc) {
515 dev_err(mas->dev, "Err setting up rx desc\n");
516 return -EIO;
517 }
518 }
519
520 /*
521 * Prepare the TX always, even for RX or tx_buf being null, we would
522 * need TX to be prepared per GSI spec
523 */
524 dmaengine_slave_config(mas->tx, &config);
525 tx_desc = dmaengine_prep_slave_sg(mas->tx, xfer->tx_sg.sgl, xfer->tx_sg.nents,
526 DMA_MEM_TO_DEV, flags);
527 if (!tx_desc) {
528 dev_err(mas->dev, "Err setting up tx desc\n");
529 return -EIO;
530 }
531
532 tx_desc->callback_result = spi_gsi_callback_result;
533 tx_desc->callback_param = spi;
534
535 if (peripheral.cmd & SPI_RX)
536 dmaengine_submit(rx_desc);
537 dmaengine_submit(tx_desc);
538
539 if (peripheral.cmd & SPI_RX)
540 dma_async_issue_pending(mas->rx);
541
542 dma_async_issue_pending(mas->tx);
543 return 1;
544 }
545
546 static u32 get_xfer_len_in_words(struct spi_transfer *xfer,
547 struct spi_geni_master *mas)
548 {
549 u32 len;
550
551 if (!(mas->cur_bits_per_word % MIN_WORD_LEN))
552 len = xfer->len * BITS_PER_BYTE / mas->cur_bits_per_word;
553 else
554 len = xfer->len / (mas->cur_bits_per_word / BITS_PER_BYTE + 1);
555 len &= TRANS_LEN_MSK;
556
557 return len;
558 }
559
560 static bool geni_can_dma(struct spi_controller *ctlr,
561 struct spi_device *slv, struct spi_transfer *xfer)
562 {
563 struct spi_geni_master *mas = spi_controller_get_devdata(slv->controller);
564 u32 len, fifo_size;
565
566 if (mas->cur_xfer_mode == GENI_GPI_DMA)
567 return true;
568
569 /* Set SE DMA mode for SPI target. */
570 if (ctlr->target)
571 return true;
572
573 len = get_xfer_len_in_words(xfer, mas);
574 fifo_size = mas->tx_fifo_depth * mas->fifo_width_bits / mas->cur_bits_per_word;
575
576 if (len > fifo_size)
577 return true;
578 else
579 return false;
580 }
581
582 static int spi_geni_prepare_message(struct spi_controller *spi,
583 struct spi_message *spi_msg)
584 {
585 struct spi_geni_master *mas = spi_controller_get_devdata(spi);
586 int ret;
587
588 switch (mas->cur_xfer_mode) {
589 case GENI_SE_FIFO:
590 case GENI_SE_DMA:
591 if (spi_geni_is_abort_still_pending(mas))
592 return -EBUSY;
593 ret = setup_fifo_params(spi_msg->spi, spi);
594 if (ret)
595 dev_err(mas->dev, "Couldn't select mode %d\n", ret);
596 return ret;
597
598 case GENI_GPI_DMA:
599 /* nothing to do for GPI DMA */
600 return 0;
601 }
602
603 dev_err(mas->dev, "Mode not supported %d", mas->cur_xfer_mode);
604 return -EINVAL;
605 }
606
607 static void spi_geni_release_dma_chan(void *data)
608 {
609 struct spi_geni_master *mas = data;
610
611 if (mas->rx) {
612 dma_release_channel(mas->rx);
613 mas->rx = NULL;
614 }
615
616 if (mas->tx) {
617 dma_release_channel(mas->tx);
618 mas->tx = NULL;
619 }
620 }
621
622 static int spi_geni_grab_gpi_chan(struct spi_geni_master *mas)
623 {
624 int ret;
625
626 mas->tx = dma_request_chan(mas->dev, "tx");
627 if (IS_ERR(mas->tx)) {
628 ret = dev_err_probe(mas->dev, PTR_ERR(mas->tx),
629 "Failed to get tx DMA ch\n");
630 goto err_tx;
631 }
632
633 mas->rx = dma_request_chan(mas->dev, "rx");
634 if (IS_ERR(mas->rx)) {
635 ret = dev_err_probe(mas->dev, PTR_ERR(mas->rx),
636 "Failed to get rx DMA ch\n");
637 goto err_rx;
638 }
639
640 ret = devm_add_action_or_reset(mas->dev, spi_geni_release_dma_chan, mas);
641 if (ret) {
642 dev_err(mas->dev, "Unable to add action.\n");
643 return ret;
644 }
645
646 return 0;
647
648 err_rx:
649 mas->rx = NULL;
650 dma_release_channel(mas->tx);
651 err_tx:
652 mas->tx = NULL;
653 return ret;
654 }
655
656 static int spi_geni_init(struct spi_geni_master *mas)
657 {
658 struct spi_controller *spi = dev_get_drvdata(mas->dev);
659 struct geni_se *se = &mas->se;
660 unsigned int proto, major, minor, ver;
661 u32 spi_tx_cfg, fifo_disable;
662 int ret = -ENXIO;
663
664 pm_runtime_get_sync(mas->dev);
665
666 proto = geni_se_read_proto(se);
667
668 if (spi->target) {
669 if (proto != GENI_SE_SPI_SLAVE) {
670 dev_err(mas->dev, "Invalid proto %d\n", proto);
671 goto out_pm;
672 }
673 spi_slv_setup(mas);
674 } else if (proto != GENI_SE_SPI) {
675 dev_err(mas->dev, "Invalid proto %d\n", proto);
676 goto out_pm;
677 }
678 mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se);
679
680 /* Width of Tx and Rx FIFO is same */
681 mas->fifo_width_bits = geni_se_get_tx_fifo_width(se);
682
683 /*
684 * Hardware programming guide suggests to configure
685 * RX FIFO RFR level to fifo_depth-2.
686 */
687 geni_se_init(se, mas->tx_fifo_depth - 3, mas->tx_fifo_depth - 2);
688 /* Transmit an entire FIFO worth of data per IRQ */
689 mas->tx_wm = 1;
690 ver = geni_se_get_qup_hw_version(se);
691 major = GENI_SE_VERSION_MAJOR(ver);
692 minor = GENI_SE_VERSION_MINOR(ver);
693
694 if (major == 1 && minor == 0)
695 mas->oversampling = 2;
696 else
697 mas->oversampling = 1;
698
699 fifo_disable = readl(se->base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE;
700 switch (fifo_disable) {
701 case 1:
702 ret = spi_geni_grab_gpi_chan(mas);
703 if (!ret) { /* success case */
704 mas->cur_xfer_mode = GENI_GPI_DMA;
705 geni_se_select_mode(se, GENI_GPI_DMA);
706 dev_dbg(mas->dev, "Using GPI DMA mode for SPI\n");
707 break;
708 } else if (ret == -EPROBE_DEFER) {
709 goto out_pm;
710 }
711 /*
712 * in case of failure to get gpi dma channel, we can still do the
713 * FIFO mode, so fallthrough
714 */
715 dev_warn(mas->dev, "FIFO mode disabled, but couldn't get DMA, fall back to FIFO mode\n");
716 fallthrough;
717
718 case 0:
719 mas->cur_xfer_mode = GENI_SE_FIFO;
720 geni_se_select_mode(se, GENI_SE_FIFO);
721 ret = 0;
722 break;
723 }
724
725 /* We always control CS manually */
726 if (!spi->target) {
727 spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG);
728 spi_tx_cfg &= ~CS_TOGGLE;
729 writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG);
730 }
731
732 out_pm:
733 pm_runtime_put(mas->dev);
734 return ret;
735 }
736
737 static unsigned int geni_byte_per_fifo_word(struct spi_geni_master *mas)
738 {
739 /*
740 * Calculate how many bytes we'll put in each FIFO word. If the
741 * transfer words don't pack cleanly into a FIFO word we'll just put
742 * one transfer word in each FIFO word. If they do pack we'll pack 'em.
743 */
744 if (mas->fifo_width_bits % mas->cur_bits_per_word)
745 return roundup_pow_of_two(DIV_ROUND_UP(mas->cur_bits_per_word,
746 BITS_PER_BYTE));
747
748 return mas->fifo_width_bits / BITS_PER_BYTE;
749 }
750
751 static bool geni_spi_handle_tx(struct spi_geni_master *mas)
752 {
753 struct geni_se *se = &mas->se;
754 unsigned int max_bytes;
755 const u8 *tx_buf;
756 unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas);
757 unsigned int i = 0;
758
759 /* Stop the watermark IRQ if nothing to send */
760 if (!mas->cur_xfer) {
761 writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
762 return false;
763 }
764
765 max_bytes = (mas->tx_fifo_depth - mas->tx_wm) * bytes_per_fifo_word;
766 if (mas->tx_rem_bytes < max_bytes)
767 max_bytes = mas->tx_rem_bytes;
768
769 tx_buf = mas->cur_xfer->tx_buf + mas->cur_xfer->len - mas->tx_rem_bytes;
770 while (i < max_bytes) {
771 unsigned int j;
772 unsigned int bytes_to_write;
773 u32 fifo_word = 0;
774 u8 *fifo_byte = (u8 *)&fifo_word;
775
776 bytes_to_write = min(bytes_per_fifo_word, max_bytes - i);
777 for (j = 0; j < bytes_to_write; j++)
778 fifo_byte[j] = tx_buf[i++];
779 iowrite32_rep(se->base + SE_GENI_TX_FIFOn, &fifo_word, 1);
780 }
781 mas->tx_rem_bytes -= max_bytes;
782 if (!mas->tx_rem_bytes) {
783 writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
784 return false;
785 }
786 return true;
787 }
788
789 static void geni_spi_handle_rx(struct spi_geni_master *mas)
790 {
791 struct geni_se *se = &mas->se;
792 u32 rx_fifo_status;
793 unsigned int rx_bytes;
794 unsigned int rx_last_byte_valid;
795 u8 *rx_buf;
796 unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas);
797 unsigned int i = 0;
798
799 rx_fifo_status = readl(se->base + SE_GENI_RX_FIFO_STATUS);
800 rx_bytes = (rx_fifo_status & RX_FIFO_WC_MSK) * bytes_per_fifo_word;
801 if (rx_fifo_status & RX_LAST) {
802 rx_last_byte_valid = rx_fifo_status & RX_LAST_BYTE_VALID_MSK;
803 rx_last_byte_valid >>= RX_LAST_BYTE_VALID_SHFT;
804 if (rx_last_byte_valid && rx_last_byte_valid < 4)
805 rx_bytes -= bytes_per_fifo_word - rx_last_byte_valid;
806 }
807
808 /* Clear out the FIFO and bail if nowhere to put it */
809 if (!mas->cur_xfer) {
810 for (i = 0; i < DIV_ROUND_UP(rx_bytes, bytes_per_fifo_word); i++)
811 readl(se->base + SE_GENI_RX_FIFOn);
812 return;
813 }
814
815 if (mas->rx_rem_bytes < rx_bytes)
816 rx_bytes = mas->rx_rem_bytes;
817
818 rx_buf = mas->cur_xfer->rx_buf + mas->cur_xfer->len - mas->rx_rem_bytes;
819 while (i < rx_bytes) {
820 u32 fifo_word = 0;
821 u8 *fifo_byte = (u8 *)&fifo_word;
822 unsigned int bytes_to_read;
823 unsigned int j;
824
825 bytes_to_read = min(bytes_per_fifo_word, rx_bytes - i);
826 ioread32_rep(se->base + SE_GENI_RX_FIFOn, &fifo_word, 1);
827 for (j = 0; j < bytes_to_read; j++)
828 rx_buf[i++] = fifo_byte[j];
829 }
830 mas->rx_rem_bytes -= rx_bytes;
831 }
832
833 static int setup_se_xfer(struct spi_transfer *xfer,
834 struct spi_geni_master *mas,
835 u16 mode, struct spi_controller *spi)
836 {
837 u32 m_cmd = 0;
838 u32 len;
839 struct geni_se *se = &mas->se;
840 int ret;
841
842 /*
843 * Ensure that our interrupt handler isn't still running from some
844 * prior command before we start messing with the hardware behind
845 * its back. We don't need to _keep_ the lock here since we're only
846 * worried about racing with out interrupt handler. The SPI core
847 * already handles making sure that we're not trying to do two
848 * transfers at once or setting a chip select and doing a transfer
849 * concurrently.
850 *
851 * NOTE: we actually _can't_ hold the lock here because possibly we
852 * might call clk_set_rate() which needs to be able to sleep.
853 */
854 spin_lock_irq(&mas->lock);
855 spin_unlock_irq(&mas->lock);
856
857 if (xfer->bits_per_word != mas->cur_bits_per_word) {
858 spi_setup_word_len(mas, mode, xfer->bits_per_word);
859 mas->cur_bits_per_word = xfer->bits_per_word;
860 }
861
862 /* Speed and bits per word can be overridden per transfer */
863 ret = geni_spi_set_clock_and_bw(mas, xfer->speed_hz);
864 if (ret)
865 return ret;
866
867 mas->tx_rem_bytes = 0;
868 mas->rx_rem_bytes = 0;
869
870 len = get_xfer_len_in_words(xfer, mas);
871
872 mas->cur_xfer = xfer;
873 if (xfer->tx_buf) {
874 m_cmd |= SPI_TX_ONLY;
875 mas->tx_rem_bytes = xfer->len;
876 writel(len, se->base + SE_SPI_TX_TRANS_LEN);
877 }
878
879 if (xfer->rx_buf) {
880 m_cmd |= SPI_RX_ONLY;
881 writel(len, se->base + SE_SPI_RX_TRANS_LEN);
882 mas->rx_rem_bytes = xfer->len;
883 }
884
885 /*
886 * Select DMA mode if sgt are present; and with only 1 entry
887 * This is not a serious limitation because the xfer buffers are
888 * expected to fit into in 1 entry almost always, and if any
889 * doesn't for any reason we fall back to FIFO mode anyway
890 */
891 if (!xfer->tx_sg.nents && !xfer->rx_sg.nents)
892 mas->cur_xfer_mode = GENI_SE_FIFO;
893 else if (xfer->tx_sg.nents > 1 || xfer->rx_sg.nents > 1) {
894 dev_warn_once(mas->dev, "Doing FIFO, cannot handle tx_nents-%d, rx_nents-%d\n",
895 xfer->tx_sg.nents, xfer->rx_sg.nents);
896 mas->cur_xfer_mode = GENI_SE_FIFO;
897 } else
898 mas->cur_xfer_mode = GENI_SE_DMA;
899 geni_se_select_mode(se, mas->cur_xfer_mode);
900
901 /*
902 * Lock around right before we start the transfer since our
903 * interrupt could come in at any time now.
904 */
905 spin_lock_irq(&mas->lock);
906 geni_se_setup_m_cmd(se, m_cmd, FRAGMENTATION);
907
908 if (mas->cur_xfer_mode == GENI_SE_DMA) {
909 if (m_cmd & SPI_RX_ONLY)
910 geni_se_rx_init_dma(se, sg_dma_address(xfer->rx_sg.sgl),
911 sg_dma_len(xfer->rx_sg.sgl));
912 if (m_cmd & SPI_TX_ONLY)
913 geni_se_tx_init_dma(se, sg_dma_address(xfer->tx_sg.sgl),
914 sg_dma_len(xfer->tx_sg.sgl));
915 } else if (m_cmd & SPI_TX_ONLY) {
916 if (geni_spi_handle_tx(mas))
917 writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG);
918 }
919
920 spin_unlock_irq(&mas->lock);
921 return ret;
922 }
923
924 static int spi_geni_transfer_one(struct spi_controller *spi,
925 struct spi_device *slv,
926 struct spi_transfer *xfer)
927 {
928 struct spi_geni_master *mas = spi_controller_get_devdata(spi);
929 int ret;
930
931 if (spi_geni_is_abort_still_pending(mas))
932 return -EBUSY;
933
934 /* Terminate and return success for 0 byte length transfer */
935 if (!xfer->len)
936 return 0;
937
938 if (mas->cur_xfer_mode == GENI_SE_FIFO || mas->cur_xfer_mode == GENI_SE_DMA) {
939 ret = setup_se_xfer(xfer, mas, slv->mode, spi);
940 /* SPI framework expects +ve ret code to wait for transfer complete */
941 if (!ret)
942 ret = 1;
943 return ret;
944 }
945 return setup_gsi_xfer(xfer, mas, slv, spi);
946 }
947
948 static irqreturn_t geni_spi_isr(int irq, void *data)
949 {
950 struct spi_controller *spi = data;
951 struct spi_geni_master *mas = spi_controller_get_devdata(spi);
952 struct geni_se *se = &mas->se;
953 u32 m_irq;
954
955 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS);
956 if (!m_irq)
957 return IRQ_NONE;
958
959 if (m_irq & (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |
960 M_RX_FIFO_RD_ERR_EN | M_RX_FIFO_WR_ERR_EN |
961 M_TX_FIFO_RD_ERR_EN | M_TX_FIFO_WR_ERR_EN))
962 dev_warn(mas->dev, "Unexpected IRQ err status %#010x\n", m_irq);
963
964 spin_lock(&mas->lock);
965
966 if (mas->cur_xfer_mode == GENI_SE_FIFO) {
967 if ((m_irq & M_RX_FIFO_WATERMARK_EN) || (m_irq & M_RX_FIFO_LAST_EN))
968 geni_spi_handle_rx(mas);
969
970 if (m_irq & M_TX_FIFO_WATERMARK_EN)
971 geni_spi_handle_tx(mas);
972
973 if (m_irq & M_CMD_DONE_EN) {
974 if (mas->cur_xfer) {
975 spi_finalize_current_transfer(spi);
976 mas->cur_xfer = NULL;
977 /*
978 * If this happens, then a CMD_DONE came before all the
979 * Tx buffer bytes were sent out. This is unusual, log
980 * this condition and disable the WM interrupt to
981 * prevent the system from stalling due an interrupt
982 * storm.
983 *
984 * If this happens when all Rx bytes haven't been
985 * received, log the condition. The only known time
986 * this can happen is if bits_per_word != 8 and some
987 * registers that expect xfer lengths in num spi_words
988 * weren't written correctly.
989 */
990 if (mas->tx_rem_bytes) {
991 writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
992 dev_err(mas->dev, "Premature done. tx_rem = %d bpw%d\n",
993 mas->tx_rem_bytes, mas->cur_bits_per_word);
994 }
995 if (mas->rx_rem_bytes)
996 dev_err(mas->dev, "Premature done. rx_rem = %d bpw%d\n",
997 mas->rx_rem_bytes, mas->cur_bits_per_word);
998 } else {
999 complete(&mas->cs_done);
1000 }
1001 }
1002 } else if (mas->cur_xfer_mode == GENI_SE_DMA) {
1003 const struct spi_transfer *xfer = mas->cur_xfer;
1004 u32 dma_tx_status = readl_relaxed(se->base + SE_DMA_TX_IRQ_STAT);
1005 u32 dma_rx_status = readl_relaxed(se->base + SE_DMA_RX_IRQ_STAT);
1006
1007 if (dma_tx_status)
1008 writel(dma_tx_status, se->base + SE_DMA_TX_IRQ_CLR);
1009 if (dma_rx_status)
1010 writel(dma_rx_status, se->base + SE_DMA_RX_IRQ_CLR);
1011 if (dma_tx_status & TX_DMA_DONE)
1012 mas->tx_rem_bytes = 0;
1013 if (dma_rx_status & RX_DMA_DONE)
1014 mas->rx_rem_bytes = 0;
1015 if (dma_tx_status & TX_RESET_DONE)
1016 complete(&mas->tx_reset_done);
1017 if (dma_rx_status & RX_RESET_DONE)
1018 complete(&mas->rx_reset_done);
1019 if (!mas->tx_rem_bytes && !mas->rx_rem_bytes && xfer) {
1020 spi_finalize_current_transfer(spi);
1021 mas->cur_xfer = NULL;
1022 }
1023 }
1024
1025 if (m_irq & M_CMD_CANCEL_EN)
1026 complete(&mas->cancel_done);
1027 if (m_irq & M_CMD_ABORT_EN)
1028 complete(&mas->abort_done);
1029
1030 /*
1031 * It's safe or a good idea to Ack all of our interrupts at the end
1032 * of the function. Specifically:
1033 * - M_CMD_DONE_EN / M_RX_FIFO_LAST_EN: Edge triggered interrupts and
1034 * clearing Acks. Clearing at the end relies on nobody else having
1035 * started a new transfer yet or else we could be clearing _their_
1036 * done bit, but everyone grabs the spinlock before starting a new
1037 * transfer.
1038 * - M_RX_FIFO_WATERMARK_EN / M_TX_FIFO_WATERMARK_EN: These appear
1039 * to be "latched level" interrupts so it's important to clear them
1040 * _after_ you've handled the condition and always safe to do so
1041 * since they'll re-assert if they're still happening.
1042 */
1043 writel(m_irq, se->base + SE_GENI_M_IRQ_CLEAR);
1044
1045 spin_unlock(&mas->lock);
1046
1047 return IRQ_HANDLED;
1048 }
1049
1050 static int spi_geni_probe(struct platform_device *pdev)
1051 {
1052 int ret, irq;
1053 struct spi_controller *spi;
1054 struct spi_geni_master *mas;
1055 void __iomem *base;
1056 struct clk *clk;
1057 struct device *dev = &pdev->dev;
1058
1059 irq = platform_get_irq(pdev, 0);
1060 if (irq < 0)
1061 return irq;
1062
1063 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
1064 if (ret)
1065 return dev_err_probe(dev, ret, "could not set DMA mask\n");
1066
1067 base = devm_platform_ioremap_resource(pdev, 0);
1068 if (IS_ERR(base))
1069 return PTR_ERR(base);
1070
1071 clk = devm_clk_get(dev, "se");
1072 if (IS_ERR(clk))
1073 return PTR_ERR(clk);
1074
1075 spi = devm_spi_alloc_host(dev, sizeof(*mas));
1076 if (!spi)
1077 return -ENOMEM;
1078
1079 platform_set_drvdata(pdev, spi);
1080 mas = spi_controller_get_devdata(spi);
1081 mas->irq = irq;
1082 mas->dev = dev;
1083 mas->se.dev = dev;
1084 mas->se.wrapper = dev_get_drvdata(dev->parent);
1085 mas->se.base = base;
1086 mas->se.clk = clk;
1087
1088 ret = devm_pm_opp_set_clkname(&pdev->dev, "se");
1089 if (ret)
1090 return ret;
1091 /* OPP table is optional */
1092 ret = devm_pm_opp_of_add_table(&pdev->dev);
1093 if (ret && ret != -ENODEV) {
1094 dev_err(&pdev->dev, "invalid OPP table in device tree\n");
1095 return ret;
1096 }
1097
1098 spi->bus_num = -1;
1099 spi->dev.of_node = dev->of_node;
1100 spi->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_CS_HIGH;
1101 spi->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1102 spi->num_chipselect = 4;
1103 spi->max_speed_hz = 50000000;
1104 spi->max_dma_len = 0xffff0; /* 24 bits for tx/rx dma length */
1105 spi->prepare_message = spi_geni_prepare_message;
1106 spi->transfer_one = spi_geni_transfer_one;
1107 spi->can_dma = geni_can_dma;
1108 spi->dma_map_dev = dev->parent;
1109 spi->auto_runtime_pm = true;
1110 spi->handle_err = spi_geni_handle_err;
1111 spi->use_gpio_descriptors = true;
1112
1113 init_completion(&mas->cs_done);
1114 init_completion(&mas->cancel_done);
1115 init_completion(&mas->abort_done);
1116 init_completion(&mas->tx_reset_done);
1117 init_completion(&mas->rx_reset_done);
1118 spin_lock_init(&mas->lock);
1119
1120 ret = geni_icc_get(&mas->se, NULL);
1121 if (ret)
1122 return ret;
1123
1124 pm_runtime_use_autosuspend(&pdev->dev);
1125 pm_runtime_set_autosuspend_delay(&pdev->dev, 250);
1126 ret = devm_pm_runtime_enable(dev);
1127 if (ret)
1128 return ret;
1129
1130 if (device_property_read_bool(&pdev->dev, "spi-slave"))
1131 spi->target = true;
1132
1133 /* Set the bus quota to a reasonable value for register access */
1134 mas->se.icc_paths[GENI_TO_CORE].avg_bw = Bps_to_icc(CORE_2X_50_MHZ);
1135 mas->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
1136
1137 ret = geni_icc_set_bw(&mas->se);
1138 if (ret)
1139 return ret;
1140
1141 ret = spi_geni_init(mas);
1142 if (ret)
1143 return ret;
1144
1145 /*
1146 * check the mode supported and set_cs for fifo mode only
1147 * for dma (gsi) mode, the gsi will set cs based on params passed in
1148 * TRE
1149 */
1150 if (!spi->target && mas->cur_xfer_mode == GENI_SE_FIFO)
1151 spi->set_cs = spi_geni_set_cs;
1152
1153 /*
1154 * TX is required per GSI spec, see setup_gsi_xfer().
1155 */
1156 if (mas->cur_xfer_mode == GENI_GPI_DMA)
1157 spi->flags = SPI_CONTROLLER_MUST_TX;
1158
1159 ret = devm_request_irq(dev, mas->irq, geni_spi_isr, 0, dev_name(dev), spi);
1160 if (ret)
1161 return ret;
1162
1163 return devm_spi_register_controller(dev, spi);
1164 }
1165
1166 static int __maybe_unused spi_geni_runtime_suspend(struct device *dev)
1167 {
1168 struct spi_controller *spi = dev_get_drvdata(dev);
1169 struct spi_geni_master *mas = spi_controller_get_devdata(spi);
1170 int ret;
1171
1172 /* Drop the performance state vote */
1173 dev_pm_opp_set_rate(dev, 0);
1174
1175 ret = geni_se_resources_off(&mas->se);
1176 if (ret)
1177 return ret;
1178
1179 return geni_icc_disable(&mas->se);
1180 }
1181
1182 static int __maybe_unused spi_geni_runtime_resume(struct device *dev)
1183 {
1184 struct spi_controller *spi = dev_get_drvdata(dev);
1185 struct spi_geni_master *mas = spi_controller_get_devdata(spi);
1186 int ret;
1187
1188 ret = geni_icc_enable(&mas->se);
1189 if (ret)
1190 return ret;
1191
1192 ret = geni_se_resources_on(&mas->se);
1193 if (ret)
1194 return ret;
1195
1196 return dev_pm_opp_set_rate(mas->dev, mas->cur_sclk_hz);
1197 }
1198
1199 static int __maybe_unused spi_geni_suspend(struct device *dev)
1200 {
1201 struct spi_controller *spi = dev_get_drvdata(dev);
1202 int ret;
1203
1204 ret = spi_controller_suspend(spi);
1205 if (ret)
1206 return ret;
1207
1208 ret = pm_runtime_force_suspend(dev);
1209 if (ret)
1210 spi_controller_resume(spi);
1211
1212 return ret;
1213 }
1214
1215 static int __maybe_unused spi_geni_resume(struct device *dev)
1216 {
1217 struct spi_controller *spi = dev_get_drvdata(dev);
1218 int ret;
1219
1220 ret = pm_runtime_force_resume(dev);
1221 if (ret)
1222 return ret;
1223
1224 ret = spi_controller_resume(spi);
1225 if (ret)
1226 pm_runtime_force_suspend(dev);
1227
1228 return ret;
1229 }
1230
1231 static const struct dev_pm_ops spi_geni_pm_ops = {
1232 SET_RUNTIME_PM_OPS(spi_geni_runtime_suspend,
1233 spi_geni_runtime_resume, NULL)
1234 SET_SYSTEM_SLEEP_PM_OPS(spi_geni_suspend, spi_geni_resume)
1235 };
1236
1237 static const struct of_device_id spi_geni_dt_match[] = {
1238 { .compatible = "qcom,geni-spi" },
1239 {}
1240 };
1241 MODULE_DEVICE_TABLE(of, spi_geni_dt_match);
1242
1243 static struct platform_driver spi_geni_driver = {
1244 .probe = spi_geni_probe,
1245 .driver = {
1246 .name = "geni_spi",
1247 .pm = &spi_geni_pm_ops,
1248 .of_match_table = spi_geni_dt_match,
1249 },
1250 };
1251 module_platform_driver(spi_geni_driver);
1252
1253 MODULE_DESCRIPTION("SPI driver for GENI based QUP cores");
1254 MODULE_LICENSE("GPL v2");
Kernel DRM miscellaneous fixes and cross-tree changes