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drm/tests: hdmi: Fix memory leaks in drm_display_mode_from_cea_vic()
[drm/drm-misc.git] / drivers / iio / adc / ad7173.c
blob0702ec71aa29332036b30e5afd1996fc914baf92
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * AD717x and AD411x family SPI ADC driver
4 *
5 * Supported devices:
6 * AD4111/AD4112/AD4114/AD4115/AD4116
7 * AD7172-2/AD7172-4/AD7173-8/AD7175-2
8 * AD7175-8/AD7176-2/AD7177-2
9 *
10 * Copyright (C) 2015, 2024 Analog Devices, Inc.
11 */
12
13 #include <linux/array_size.h>
14 #include <linux/bitfield.h>
15 #include <linux/bitmap.h>
16 #include <linux/container_of.h>
17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
19 #include <linux/delay.h>
20 #include <linux/device.h>
21 #include <linux/err.h>
22 #include <linux/gpio/driver.h>
23 #include <linux/gpio/regmap.h>
24 #include <linux/idr.h>
25 #include <linux/interrupt.h>
26 #include <linux/math64.h>
27 #include <linux/module.h>
28 #include <linux/mod_devicetable.h>
29 #include <linux/property.h>
30 #include <linux/regmap.h>
31 #include <linux/regulator/consumer.h>
32 #include <linux/slab.h>
33 #include <linux/spi/spi.h>
34 #include <linux/types.h>
35 #include <linux/units.h>
36
37 #include <linux/iio/buffer.h>
38 #include <linux/iio/iio.h>
39 #include <linux/iio/trigger_consumer.h>
40 #include <linux/iio/triggered_buffer.h>
41
42 #include <linux/iio/adc/ad_sigma_delta.h>
43
44 #define AD7173_REG_COMMS 0x00
45 #define AD7173_REG_ADC_MODE 0x01
46 #define AD7173_REG_INTERFACE_MODE 0x02
47 #define AD7173_REG_CRC 0x03
48 #define AD7173_REG_DATA 0x04
49 #define AD7173_REG_GPIO 0x06
50 #define AD7173_REG_ID 0x07
51 #define AD7173_REG_CH(x) (0x10 + (x))
52 #define AD7173_REG_SETUP(x) (0x20 + (x))
53 #define AD7173_REG_FILTER(x) (0x28 + (x))
54 #define AD7173_REG_OFFSET(x) (0x30 + (x))
55 #define AD7173_REG_GAIN(x) (0x38 + (x))
56
57 #define AD7173_RESET_LENGTH BITS_TO_BYTES(64)
58
59 #define AD7173_CH_ENABLE BIT(15)
60 #define AD7173_CH_SETUP_SEL_MASK GENMASK(14, 12)
61 #define AD7173_CH_SETUP_AINPOS_MASK GENMASK(9, 5)
62 #define AD7173_CH_SETUP_AINNEG_MASK GENMASK(4, 0)
63
64 #define AD7173_NO_AINS_PER_CHANNEL 2
65 #define AD7173_CH_ADDRESS(pos, neg) \
66 (FIELD_PREP(AD7173_CH_SETUP_AINPOS_MASK, pos) | \
67 FIELD_PREP(AD7173_CH_SETUP_AINNEG_MASK, neg))
68 #define AD7173_AIN_TEMP_POS 17
69 #define AD7173_AIN_TEMP_NEG 18
70 #define AD7173_AIN_POW_MON_POS 19
71 #define AD7173_AIN_POW_MON_NEG 20
72 #define AD7173_AIN_REF_POS 21
73 #define AD7173_AIN_REF_NEG 22
74
75 #define AD7173_IS_REF_INPUT(x) ((x) == AD7173_AIN_REF_POS || \
76 (x) == AD7173_AIN_REF_NEG)
77
78 #define AD7172_2_ID 0x00d0
79 #define AD7175_ID 0x0cd0
80 #define AD7176_ID 0x0c90
81 #define AD7175_2_ID 0x0cd0
82 #define AD7172_4_ID 0x2050
83 #define AD7173_ID 0x30d0
84 #define AD4111_ID AD7173_ID
85 #define AD4112_ID AD7173_ID
86 #define AD4114_ID AD7173_ID
87 #define AD4116_ID 0x34d0
88 #define AD4115_ID 0x38d0
89 #define AD7175_8_ID 0x3cd0
90 #define AD7177_ID 0x4fd0
91 #define AD7173_ID_MASK GENMASK(15, 4)
92
93 #define AD7173_ADC_MODE_REF_EN BIT(15)
94 #define AD7173_ADC_MODE_SING_CYC BIT(13)
95 #define AD7173_ADC_MODE_MODE_MASK GENMASK(6, 4)
96 #define AD7173_ADC_MODE_CLOCKSEL_MASK GENMASK(3, 2)
97 #define AD7173_ADC_MODE_CLOCKSEL_INT 0x0
98 #define AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT 0x1
99 #define AD7173_ADC_MODE_CLOCKSEL_EXT 0x2
100 #define AD7173_ADC_MODE_CLOCKSEL_XTAL 0x3
101
102 #define AD7173_GPIO_PDSW BIT(14)
103 #define AD7173_GPIO_OP_EN2_3 BIT(13)
104 #define AD7173_GPIO_MUX_IO BIT(12)
105 #define AD7173_GPIO_SYNC_EN BIT(11)
106 #define AD7173_GPIO_ERR_EN BIT(10)
107 #define AD7173_GPIO_ERR_DAT BIT(9)
108 #define AD7173_GPIO_GP_DATA3 BIT(7)
109 #define AD7173_GPIO_GP_DATA2 BIT(6)
110 #define AD7173_GPIO_IP_EN1 BIT(5)
111 #define AD7173_GPIO_IP_EN0 BIT(4)
112 #define AD7173_GPIO_OP_EN1 BIT(3)
113 #define AD7173_GPIO_OP_EN0 BIT(2)
114 #define AD7173_GPIO_GP_DATA1 BIT(1)
115 #define AD7173_GPIO_GP_DATA0 BIT(0)
116
117 #define AD7173_GPO12_DATA(x) BIT((x) + 0)
118 #define AD7173_GPO23_DATA(x) BIT((x) + 4)
119 #define AD4111_GPO01_DATA(x) BIT((x) + 6)
120 #define AD7173_GPO_DATA(x) ((x) < 2 ? AD7173_GPO12_DATA(x) : AD7173_GPO23_DATA(x))
121
122 #define AD7173_INTERFACE_DATA_STAT BIT(6)
123 #define AD7173_INTERFACE_DATA_STAT_EN(x) \
124 FIELD_PREP(AD7173_INTERFACE_DATA_STAT, x)
125
126 #define AD7173_SETUP_BIPOLAR BIT(12)
127 #define AD7173_SETUP_AREF_BUF_MASK GENMASK(11, 10)
128 #define AD7173_SETUP_AIN_BUF_MASK GENMASK(9, 8)
129
130 #define AD7173_SETUP_REF_SEL_MASK GENMASK(5, 4)
131 #define AD7173_SETUP_REF_SEL_AVDD1_AVSS 0x3
132 #define AD7173_SETUP_REF_SEL_INT_REF 0x2
133 #define AD7173_SETUP_REF_SEL_EXT_REF2 0x1
134 #define AD7173_SETUP_REF_SEL_EXT_REF 0x0
135 #define AD7173_VOLTAGE_INT_REF_uV 2500000
136 #define AD7173_TEMP_SENSIIVITY_uV_per_C 477
137 #define AD7177_ODR_START_VALUE 0x07
138 #define AD4111_SHUNT_RESISTOR_OHM 50
139 #define AD4111_DIVIDER_RATIO 10
140 #define AD4111_CURRENT_CHAN_CUTOFF 16
141 #define AD4111_VINCOM_INPUT 0x10
142
143 /* pin < num_voltage_in is a normal voltage input */
144 /* pin >= num_voltage_in_div is a voltage input without a divider */
145 #define AD4111_IS_VINCOM_MISMATCH(pin1, pin2) ((pin1) == AD4111_VINCOM_INPUT && \
146 (pin2) < st->info->num_voltage_in && \
147 (pin2) >= st->info->num_voltage_in_div)
148
149 #define AD7173_FILTER_ODR0_MASK GENMASK(5, 0)
150 #define AD7173_MAX_CONFIGS 8
151
152 struct ad7173_device_info {
153 const unsigned int *sinc5_data_rates;
154 unsigned int num_sinc5_data_rates;
155 unsigned int odr_start_value;
156 /*
157 * AD4116 has both inputs with a voltage divider and without.
158 * These inputs cannot be mixed in the channel configuration.
159 * Does not include the VINCOM input.
160 */
161 unsigned int num_voltage_in_div;
162 unsigned int num_channels;
163 unsigned int num_configs;
164 unsigned int num_voltage_in;
165 unsigned int clock;
166 unsigned int id;
167 char *name;
168 bool has_current_inputs;
169 bool has_vincom_input;
170 bool has_temp;
171 /* ((AVDD1 − AVSS)/5) */
172 bool has_pow_supply_monitoring;
173 bool has_input_buf;
174 bool has_int_ref;
175 bool has_ref2;
176 bool higher_gpio_bits;
177 u8 num_gpios;
178 };
179
180 struct ad7173_channel_config {
181 u8 cfg_slot;
182 bool live;
183
184 /* Following fields are used to compare equality. */
185 struct_group(config_props,
186 bool bipolar;
187 bool input_buf;
188 u8 odr;
189 u8 ref_sel;
190 );
191 };
192
193 struct ad7173_channel {
194 unsigned int chan_reg;
195 unsigned int ain;
196 struct ad7173_channel_config cfg;
197 };
198
199 struct ad7173_state {
200 struct ad_sigma_delta sd;
201 const struct ad7173_device_info *info;
202 struct ad7173_channel *channels;
203 struct regulator_bulk_data regulators[3];
204 unsigned int adc_mode;
205 unsigned int interface_mode;
206 unsigned int num_channels;
207 struct ida cfg_slots_status;
208 unsigned long long config_usage_counter;
209 unsigned long long *config_cnts;
210 struct clk *ext_clk;
211 struct clk_hw int_clk_hw;
212 #if IS_ENABLED(CONFIG_GPIOLIB)
213 struct regmap *reg_gpiocon_regmap;
214 struct gpio_regmap *gpio_regmap;
215 #endif
216 };
217
218 static unsigned int ad4115_sinc5_data_rates[] = {
219 24845000, 24845000, 20725000, 20725000, /* 0-3 */
220 15564000, 13841000, 10390000, 10390000, /* 4-7 */
221 4994000, 2499000, 1000000, 500000, /* 8-11 */
222 395500, 200000, 100000, 59890, /* 12-15 */
223 49920, 20000, 16660, 10000, /* 16-19 */
224 5000, 2500, 2500, /* 20-22 */
225 };
226
227 static unsigned int ad4116_sinc5_data_rates[] = {
228 12422360, 12422360, 12422360, 12422360, /* 0-3 */
229 10362690, 10362690, 7782100, 6290530, /* 4-7 */
230 5194800, 2496900, 1007600, 499900, /* 8-11 */
231 390600, 200300, 100000, 59750, /* 12-15 */
232 49840, 20000, 16650, 10000, /* 16-19 */
233 5000, 2500, 1250, /* 20-22 */
234 };
235
236 static const unsigned int ad7173_sinc5_data_rates[] = {
237 6211000, 6211000, 6211000, 6211000, 6211000, 6211000, 5181000, 4444000, /* 0-7 */
238 3115000, 2597000, 1007000, 503800, 381000, 200300, 100500, 59520, /* 8-15 */
239 49680, 20010, 16333, 10000, 5000, 2500, 1250, /* 16-22 */
240 };
241
242 static const unsigned int ad7175_sinc5_data_rates[] = {
243 50000000, 41667000, 31250000, 27778000, /* 0-3 */
244 20833000, 17857000, 12500000, 10000000, /* 4-7 */
245 5000000, 2500000, 1000000, 500000, /* 8-11 */
246 397500, 200000, 100000, 59920, /* 12-15 */
247 49960, 20000, 16666, 10000, /* 16-19 */
248 5000, /* 20 */
249 };
250
251 static unsigned int ad4111_current_channel_config[] = {
252 /* Ain sel: pos neg */
253 0x1E8, /* 15:IIN0+ 8:IIN0− */
254 0x1C9, /* 14:IIN1+ 9:IIN1− */
255 0x1AA, /* 13:IIN2+ 10:IIN2− */
256 0x18B, /* 12:IIN3+ 11:IIN3− */
257 };
258
259 static const struct ad7173_device_info ad4111_device_info = {
260 .name = "ad4111",
261 .id = AD4111_ID,
262 .num_voltage_in_div = 8,
263 .num_channels = 16,
264 .num_configs = 8,
265 .num_voltage_in = 8,
266 .num_gpios = 2,
267 .higher_gpio_bits = true,
268 .has_temp = true,
269 .has_vincom_input = true,
270 .has_input_buf = true,
271 .has_current_inputs = true,
272 .has_int_ref = true,
273 .clock = 2 * HZ_PER_MHZ,
274 .sinc5_data_rates = ad7173_sinc5_data_rates,
275 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates),
276 };
277
278 static const struct ad7173_device_info ad4112_device_info = {
279 .name = "ad4112",
280 .id = AD4112_ID,
281 .num_voltage_in_div = 8,
282 .num_channels = 16,
283 .num_configs = 8,
284 .num_voltage_in = 8,
285 .num_gpios = 2,
286 .higher_gpio_bits = true,
287 .has_vincom_input = true,
288 .has_temp = true,
289 .has_input_buf = true,
290 .has_current_inputs = true,
291 .has_int_ref = true,
292 .clock = 2 * HZ_PER_MHZ,
293 .sinc5_data_rates = ad7173_sinc5_data_rates,
294 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates),
295 };
296
297 static const struct ad7173_device_info ad4114_device_info = {
298 .name = "ad4114",
299 .id = AD4114_ID,
300 .num_voltage_in_div = 16,
301 .num_channels = 16,
302 .num_configs = 8,
303 .num_voltage_in = 16,
304 .num_gpios = 4,
305 .has_vincom_input = true,
306 .has_temp = true,
307 .has_input_buf = true,
308 .has_int_ref = true,
309 .clock = 2 * HZ_PER_MHZ,
310 .sinc5_data_rates = ad7173_sinc5_data_rates,
311 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates),
312 };
313
314 static const struct ad7173_device_info ad4115_device_info = {
315 .name = "ad4115",
316 .id = AD4115_ID,
317 .num_voltage_in_div = 16,
318 .num_channels = 16,
319 .num_configs = 8,
320 .num_voltage_in = 16,
321 .num_gpios = 4,
322 .has_vincom_input = true,
323 .has_temp = true,
324 .has_input_buf = true,
325 .has_int_ref = true,
326 .clock = 8 * HZ_PER_MHZ,
327 .sinc5_data_rates = ad4115_sinc5_data_rates,
328 .num_sinc5_data_rates = ARRAY_SIZE(ad4115_sinc5_data_rates),
329 };
330
331 static const struct ad7173_device_info ad4116_device_info = {
332 .name = "ad4116",
333 .id = AD4116_ID,
334 .num_voltage_in_div = 11,
335 .num_channels = 16,
336 .num_configs = 8,
337 .num_voltage_in = 16,
338 .num_gpios = 4,
339 .has_vincom_input = true,
340 .has_temp = true,
341 .has_input_buf = true,
342 .has_int_ref = true,
343 .clock = 4 * HZ_PER_MHZ,
344 .sinc5_data_rates = ad4116_sinc5_data_rates,
345 .num_sinc5_data_rates = ARRAY_SIZE(ad4116_sinc5_data_rates),
346 };
347
348 static const struct ad7173_device_info ad7172_2_device_info = {
349 .name = "ad7172-2",
350 .id = AD7172_2_ID,
351 .num_voltage_in = 5,
352 .num_channels = 4,
353 .num_configs = 4,
354 .num_gpios = 2,
355 .has_temp = true,
356 .has_input_buf = true,
357 .has_int_ref = true,
358 .has_pow_supply_monitoring = true,
359 .clock = 2 * HZ_PER_MHZ,
360 .sinc5_data_rates = ad7173_sinc5_data_rates,
361 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates),
362 };
363
364 static const struct ad7173_device_info ad7172_4_device_info = {
365 .name = "ad7172-4",
366 .id = AD7172_4_ID,
367 .num_voltage_in = 9,
368 .num_channels = 8,
369 .num_configs = 8,
370 .num_gpios = 4,
371 .has_input_buf = true,
372 .has_ref2 = true,
373 .has_pow_supply_monitoring = true,
374 .clock = 2 * HZ_PER_MHZ,
375 .sinc5_data_rates = ad7173_sinc5_data_rates,
376 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates),
377 };
378
379 static const struct ad7173_device_info ad7173_8_device_info = {
380 .name = "ad7173-8",
381 .id = AD7173_ID,
382 .num_voltage_in = 17,
383 .num_channels = 16,
384 .num_configs = 8,
385 .num_gpios = 4,
386 .has_temp = true,
387 .has_input_buf = true,
388 .has_int_ref = true,
389 .has_ref2 = true,
390 .clock = 2 * HZ_PER_MHZ,
391 .sinc5_data_rates = ad7173_sinc5_data_rates,
392 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates),
393 };
394
395 static const struct ad7173_device_info ad7175_2_device_info = {
396 .name = "ad7175-2",
397 .id = AD7175_2_ID,
398 .num_voltage_in = 5,
399 .num_channels = 4,
400 .num_configs = 4,
401 .num_gpios = 2,
402 .has_temp = true,
403 .has_input_buf = true,
404 .has_int_ref = true,
405 .has_pow_supply_monitoring = true,
406 .clock = 16 * HZ_PER_MHZ,
407 .sinc5_data_rates = ad7175_sinc5_data_rates,
408 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates),
409 };
410
411 static const struct ad7173_device_info ad7175_8_device_info = {
412 .name = "ad7175-8",
413 .id = AD7175_8_ID,
414 .num_voltage_in = 17,
415 .num_channels = 16,
416 .num_configs = 8,
417 .num_gpios = 4,
418 .has_temp = true,
419 .has_input_buf = true,
420 .has_int_ref = true,
421 .has_ref2 = true,
422 .has_pow_supply_monitoring = true,
423 .clock = 16 * HZ_PER_MHZ,
424 .sinc5_data_rates = ad7175_sinc5_data_rates,
425 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates),
426 };
427
428 static const struct ad7173_device_info ad7176_2_device_info = {
429 .name = "ad7176-2",
430 .id = AD7176_ID,
431 .num_voltage_in = 5,
432 .num_channels = 4,
433 .num_configs = 4,
434 .num_gpios = 2,
435 .has_int_ref = true,
436 .clock = 16 * HZ_PER_MHZ,
437 .sinc5_data_rates = ad7175_sinc5_data_rates,
438 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates),
439 };
440
441 static const struct ad7173_device_info ad7177_2_device_info = {
442 .name = "ad7177-2",
443 .id = AD7177_ID,
444 .num_voltage_in = 5,
445 .num_channels = 4,
446 .num_configs = 4,
447 .num_gpios = 2,
448 .has_temp = true,
449 .has_input_buf = true,
450 .has_int_ref = true,
451 .has_pow_supply_monitoring = true,
452 .clock = 16 * HZ_PER_MHZ,
453 .odr_start_value = AD7177_ODR_START_VALUE,
454 .sinc5_data_rates = ad7175_sinc5_data_rates,
455 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates),
456 };
457
458 static const char *const ad7173_ref_sel_str[] = {
459 [AD7173_SETUP_REF_SEL_EXT_REF] = "vref",
460 [AD7173_SETUP_REF_SEL_EXT_REF2] = "vref2",
461 [AD7173_SETUP_REF_SEL_INT_REF] = "refout-avss",
462 [AD7173_SETUP_REF_SEL_AVDD1_AVSS] = "avdd",
463 };
464
465 static const char *const ad7173_clk_sel[] = {
466 "ext-clk", "xtal"
467 };
468
469 #if IS_ENABLED(CONFIG_GPIOLIB)
470
471 static const struct regmap_range ad7173_range_gpio[] = {
472 regmap_reg_range(AD7173_REG_GPIO, AD7173_REG_GPIO),
473 };
474
475 static const struct regmap_access_table ad7173_access_table = {
476 .yes_ranges = ad7173_range_gpio,
477 .n_yes_ranges = ARRAY_SIZE(ad7173_range_gpio),
478 };
479
480 static const struct regmap_config ad7173_regmap_config = {
481 .reg_bits = 8,
482 .val_bits = 16,
483 .rd_table = &ad7173_access_table,
484 .wr_table = &ad7173_access_table,
485 .read_flag_mask = BIT(6),
486 };
487
488 static int ad7173_mask_xlate(struct gpio_regmap *gpio, unsigned int base,
489 unsigned int offset, unsigned int *reg,
490 unsigned int *mask)
491 {
492 *mask = AD7173_GPO_DATA(offset);
493 *reg = base;
494 return 0;
495 }
496
497 static int ad4111_mask_xlate(struct gpio_regmap *gpio, unsigned int base,
498 unsigned int offset, unsigned int *reg,
499 unsigned int *mask)
500 {
501 *mask = AD4111_GPO01_DATA(offset);
502 *reg = base;
503 return 0;
504 }
505
506 static void ad7173_gpio_disable(void *data)
507 {
508 struct ad7173_state *st = data;
509 unsigned int mask;
510
511 mask = AD7173_GPIO_OP_EN0 | AD7173_GPIO_OP_EN1 | AD7173_GPIO_OP_EN2_3;
512 regmap_update_bits(st->reg_gpiocon_regmap, AD7173_REG_GPIO, mask, ~mask);
513 }
514
515 static int ad7173_gpio_init(struct ad7173_state *st)
516 {
517 struct gpio_regmap_config gpio_regmap = {};
518 struct device *dev = &st->sd.spi->dev;
519 unsigned int mask;
520 int ret;
521
522 st->reg_gpiocon_regmap = devm_regmap_init_spi(st->sd.spi, &ad7173_regmap_config);
523 ret = PTR_ERR_OR_ZERO(st->reg_gpiocon_regmap);
524 if (ret)
525 return dev_err_probe(dev, ret, "Unable to init regmap\n");
526
527 mask = AD7173_GPIO_OP_EN0 | AD7173_GPIO_OP_EN1 | AD7173_GPIO_OP_EN2_3;
528 regmap_update_bits(st->reg_gpiocon_regmap, AD7173_REG_GPIO, mask, mask);
529
530 ret = devm_add_action_or_reset(dev, ad7173_gpio_disable, st);
531 if (ret)
532 return ret;
533
534 gpio_regmap.parent = dev;
535 gpio_regmap.regmap = st->reg_gpiocon_regmap;
536 gpio_regmap.ngpio = st->info->num_gpios;
537 gpio_regmap.reg_set_base = AD7173_REG_GPIO;
538 if (st->info->higher_gpio_bits)
539 gpio_regmap.reg_mask_xlate = ad4111_mask_xlate;
540 else
541 gpio_regmap.reg_mask_xlate = ad7173_mask_xlate;
542
543 st->gpio_regmap = devm_gpio_regmap_register(dev, &gpio_regmap);
544 ret = PTR_ERR_OR_ZERO(st->gpio_regmap);
545 if (ret)
546 return dev_err_probe(dev, ret, "Unable to init gpio-regmap\n");
547
548 return 0;
549 }
550 #else
551 static int ad7173_gpio_init(struct ad7173_state *st)
552 {
553 return 0;
554 }
555 #endif /* CONFIG_GPIOLIB */
556
557 static struct ad7173_state *ad_sigma_delta_to_ad7173(struct ad_sigma_delta *sd)
558 {
559 return container_of(sd, struct ad7173_state, sd);
560 }
561
562 static struct ad7173_state *clk_hw_to_ad7173(struct clk_hw *hw)
563 {
564 return container_of(hw, struct ad7173_state, int_clk_hw);
565 }
566
567 static void ad7173_ida_destroy(void *data)
568 {
569 struct ad7173_state *st = data;
570
571 ida_destroy(&st->cfg_slots_status);
572 }
573
574 static void ad7173_reset_usage_cnts(struct ad7173_state *st)
575 {
576 memset64(st->config_cnts, 0, st->info->num_configs);
577 st->config_usage_counter = 0;
578 }
579
580 static struct ad7173_channel_config *
581 ad7173_find_live_config(struct ad7173_state *st, struct ad7173_channel_config *cfg)
582 {
583 struct ad7173_channel_config *cfg_aux;
584 ptrdiff_t cmp_size;
585 int i;
586
587 cmp_size = sizeof_field(struct ad7173_channel_config, config_props);
588 for (i = 0; i < st->num_channels; i++) {
589 cfg_aux = &st->channels[i].cfg;
590
591 if (cfg_aux->live &&
592 !memcmp(&cfg->config_props, &cfg_aux->config_props, cmp_size))
593 return cfg_aux;
594 }
595 return NULL;
596 }
597
598 /* Could be replaced with a generic LRU implementation */
599 static int ad7173_free_config_slot_lru(struct ad7173_state *st)
600 {
601 int i, lru_position = 0;
602
603 for (i = 1; i < st->info->num_configs; i++)
604 if (st->config_cnts[i] < st->config_cnts[lru_position])
605 lru_position = i;
606
607 for (i = 0; i < st->num_channels; i++)
608 if (st->channels[i].cfg.cfg_slot == lru_position)
609 st->channels[i].cfg.live = false;
610
611 ida_free(&st->cfg_slots_status, lru_position);
612 return ida_alloc(&st->cfg_slots_status, GFP_KERNEL);
613 }
614
615 /* Could be replaced with a generic LRU implementation */
616 static int ad7173_load_config(struct ad7173_state *st,
617 struct ad7173_channel_config *cfg)
618 {
619 unsigned int config;
620 int free_cfg_slot, ret;
621
622 free_cfg_slot = ida_alloc_range(&st->cfg_slots_status, 0,
623 st->info->num_configs - 1, GFP_KERNEL);
624 if (free_cfg_slot < 0)
625 free_cfg_slot = ad7173_free_config_slot_lru(st);
626
627 cfg->cfg_slot = free_cfg_slot;
628 config = FIELD_PREP(AD7173_SETUP_REF_SEL_MASK, cfg->ref_sel);
629
630 if (cfg->bipolar)
631 config |= AD7173_SETUP_BIPOLAR;
632
633 if (cfg->input_buf)
634 config |= AD7173_SETUP_AIN_BUF_MASK;
635
636 ret = ad_sd_write_reg(&st->sd, AD7173_REG_SETUP(free_cfg_slot), 2, config);
637 if (ret)
638 return ret;
639
640 return ad_sd_write_reg(&st->sd, AD7173_REG_FILTER(free_cfg_slot), 2,
641 AD7173_FILTER_ODR0_MASK & cfg->odr);
642 }
643
644 static int ad7173_config_channel(struct ad7173_state *st, int addr)
645 {
646 struct ad7173_channel_config *cfg = &st->channels[addr].cfg;
647 struct ad7173_channel_config *live_cfg;
648 int ret;
649
650 if (!cfg->live) {
651 live_cfg = ad7173_find_live_config(st, cfg);
652 if (live_cfg) {
653 cfg->cfg_slot = live_cfg->cfg_slot;
654 } else {
655 ret = ad7173_load_config(st, cfg);
656 if (ret)
657 return ret;
658 cfg->live = true;
659 }
660 }
661
662 if (st->config_usage_counter == U64_MAX)
663 ad7173_reset_usage_cnts(st);
664
665 st->config_usage_counter++;
666 st->config_cnts[cfg->cfg_slot] = st->config_usage_counter;
667
668 return 0;
669 }
670
671 static int ad7173_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
672 {
673 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd);
674 unsigned int val;
675 int ret;
676
677 ret = ad7173_config_channel(st, channel);
678 if (ret)
679 return ret;
680
681 val = AD7173_CH_ENABLE |
682 FIELD_PREP(AD7173_CH_SETUP_SEL_MASK, st->channels[channel].cfg.cfg_slot) |
683 st->channels[channel].ain;
684
685 return ad_sd_write_reg(&st->sd, AD7173_REG_CH(channel), 2, val);
686 }
687
688 static int ad7173_set_mode(struct ad_sigma_delta *sd,
689 enum ad_sigma_delta_mode mode)
690 {
691 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd);
692
693 st->adc_mode &= ~AD7173_ADC_MODE_MODE_MASK;
694 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_MODE_MASK, mode);
695
696 return ad_sd_write_reg(&st->sd, AD7173_REG_ADC_MODE, 2, st->adc_mode);
697 }
698
699 static int ad7173_append_status(struct ad_sigma_delta *sd, bool append)
700 {
701 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd);
702 unsigned int interface_mode = st->interface_mode;
703 int ret;
704
705 interface_mode &= ~AD7173_INTERFACE_DATA_STAT;
706 interface_mode |= AD7173_INTERFACE_DATA_STAT_EN(append);
707 ret = ad_sd_write_reg(&st->sd, AD7173_REG_INTERFACE_MODE, 2, interface_mode);
708 if (ret)
709 return ret;
710
711 st->interface_mode = interface_mode;
712
713 return 0;
714 }
715
716 static int ad7173_disable_all(struct ad_sigma_delta *sd)
717 {
718 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd);
719 int ret;
720 int i;
721
722 for (i = 0; i < st->num_channels; i++) {
723 ret = ad_sd_write_reg(sd, AD7173_REG_CH(i), 2, 0);
724 if (ret < 0)
725 return ret;
726 }
727
728 return 0;
729 }
730
731 static int ad7173_disable_one(struct ad_sigma_delta *sd, unsigned int chan)
732 {
733 return ad_sd_write_reg(sd, AD7173_REG_CH(chan), 2, 0);
734 }
735
736 static struct ad_sigma_delta_info ad7173_sigma_delta_info = {
737 .set_channel = ad7173_set_channel,
738 .append_status = ad7173_append_status,
739 .disable_all = ad7173_disable_all,
740 .disable_one = ad7173_disable_one,
741 .set_mode = ad7173_set_mode,
742 .has_registers = true,
743 .addr_shift = 0,
744 .read_mask = BIT(6),
745 .status_ch_mask = GENMASK(3, 0),
746 .data_reg = AD7173_REG_DATA,
747 };
748
749 static int ad7173_setup(struct iio_dev *indio_dev)
750 {
751 struct ad7173_state *st = iio_priv(indio_dev);
752 struct device *dev = &st->sd.spi->dev;
753 u8 buf[AD7173_RESET_LENGTH];
754 unsigned int id;
755 int ret;
756
757 /* reset the serial interface */
758 memset(buf, 0xff, AD7173_RESET_LENGTH);
759 ret = spi_write_then_read(st->sd.spi, buf, sizeof(buf), NULL, 0);
760 if (ret < 0)
761 return ret;
762
763 /* datasheet recommends a delay of at least 500us after reset */
764 fsleep(500);
765
766 ret = ad_sd_read_reg(&st->sd, AD7173_REG_ID, 2, &id);
767 if (ret)
768 return ret;
769
770 id &= AD7173_ID_MASK;
771 if (id != st->info->id)
772 dev_warn(dev, "Unexpected device id: 0x%04X, expected: 0x%04X\n",
773 id, st->info->id);
774
775 st->adc_mode |= AD7173_ADC_MODE_SING_CYC;
776 st->interface_mode = 0x0;
777
778 st->config_usage_counter = 0;
779 st->config_cnts = devm_kcalloc(dev, st->info->num_configs,
780 sizeof(*st->config_cnts), GFP_KERNEL);
781 if (!st->config_cnts)
782 return -ENOMEM;
783
784 /* All channels are enabled by default after a reset */
785 return ad7173_disable_all(&st->sd);
786 }
787
788 static unsigned int ad7173_get_ref_voltage_milli(struct ad7173_state *st,
789 u8 reference_select)
790 {
791 int vref;
792
793 switch (reference_select) {
794 case AD7173_SETUP_REF_SEL_EXT_REF:
795 vref = regulator_get_voltage(st->regulators[0].consumer);
796 break;
797
798 case AD7173_SETUP_REF_SEL_EXT_REF2:
799 vref = regulator_get_voltage(st->regulators[1].consumer);
800 break;
801
802 case AD7173_SETUP_REF_SEL_INT_REF:
803 vref = AD7173_VOLTAGE_INT_REF_uV;
804 break;
805
806 case AD7173_SETUP_REF_SEL_AVDD1_AVSS:
807 vref = regulator_get_voltage(st->regulators[2].consumer);
808 break;
809
810 default:
811 return -EINVAL;
812 }
813
814 if (vref < 0)
815 return vref;
816
817 return vref / (MICRO / MILLI);
818 }
819
820 static int ad7173_read_raw(struct iio_dev *indio_dev,
821 struct iio_chan_spec const *chan,
822 int *val, int *val2, long info)
823 {
824 struct ad7173_state *st = iio_priv(indio_dev);
825 struct ad7173_channel *ch = &st->channels[chan->address];
826 unsigned int reg;
827 u64 temp;
828 int ret;
829
830 switch (info) {
831 case IIO_CHAN_INFO_RAW:
832 ret = ad_sigma_delta_single_conversion(indio_dev, chan, val);
833 if (ret < 0)
834 return ret;
835
836 return IIO_VAL_INT;
837 case IIO_CHAN_INFO_SCALE:
838
839 switch (chan->type) {
840 case IIO_TEMP:
841 temp = AD7173_VOLTAGE_INT_REF_uV * MILLI;
842 temp /= AD7173_TEMP_SENSIIVITY_uV_per_C;
843 *val = temp;
844 *val2 = chan->scan_type.realbits;
845 return IIO_VAL_FRACTIONAL_LOG2;
846 case IIO_VOLTAGE:
847 *val = ad7173_get_ref_voltage_milli(st, ch->cfg.ref_sel);
848 *val2 = chan->scan_type.realbits - !!(ch->cfg.bipolar);
849
850 if (chan->channel < st->info->num_voltage_in_div)
851 *val *= AD4111_DIVIDER_RATIO;
852 return IIO_VAL_FRACTIONAL_LOG2;
853 case IIO_CURRENT:
854 *val = ad7173_get_ref_voltage_milli(st, ch->cfg.ref_sel);
855 *val /= AD4111_SHUNT_RESISTOR_OHM;
856 *val2 = chan->scan_type.realbits - ch->cfg.bipolar;
857 return IIO_VAL_FRACTIONAL_LOG2;
858 default:
859 return -EINVAL;
860 }
861 case IIO_CHAN_INFO_OFFSET:
862
863 switch (chan->type) {
864 case IIO_TEMP:
865 /* 0 Kelvin -> raw sample */
866 temp = -ABSOLUTE_ZERO_MILLICELSIUS;
867 temp *= AD7173_TEMP_SENSIIVITY_uV_per_C;
868 temp <<= chan->scan_type.realbits;
869 temp = DIV_U64_ROUND_CLOSEST(temp,
870 AD7173_VOLTAGE_INT_REF_uV *
871 MILLI);
872 *val = -temp;
873 return IIO_VAL_INT;
874 case IIO_VOLTAGE:
875 case IIO_CURRENT:
876 *val = -BIT(chan->scan_type.realbits - 1);
877 return IIO_VAL_INT;
878 default:
879 return -EINVAL;
880 }
881 case IIO_CHAN_INFO_SAMP_FREQ:
882 reg = st->channels[chan->address].cfg.odr;
883
884 *val = st->info->sinc5_data_rates[reg] / MILLI;
885 *val2 = (st->info->sinc5_data_rates[reg] % MILLI) * (MICRO / MILLI);
886
887 return IIO_VAL_INT_PLUS_MICRO;
888 default:
889 return -EINVAL;
890 }
891 }
892
893 static int ad7173_write_raw(struct iio_dev *indio_dev,
894 struct iio_chan_spec const *chan,
895 int val, int val2, long info)
896 {
897 struct ad7173_state *st = iio_priv(indio_dev);
898 struct ad7173_channel_config *cfg;
899 unsigned int freq, i;
900 int ret;
901
902 ret = iio_device_claim_direct_mode(indio_dev);
903 if (ret)
904 return ret;
905
906 switch (info) {
907 /*
908 * This attribute sets the sampling frequency for each channel individually.
909 * There are no issues for raw or buffered reads of an individual channel.
910 *
911 * When multiple channels are enabled in buffered mode, the effective
912 * sampling rate of a channel is lowered in correlation to the number
913 * of channels enabled and the sampling rate of the other channels.
914 *
915 * Example: 3 channels enabled with rates CH1:6211sps CH2,CH3:10sps
916 * While the reading of CH1 takes only 0.16ms, the reading of CH2 and CH3
917 * will take 100ms each.
918 *
919 * This will cause the reading of CH1 to be actually done once every
920 * 200.16ms, an effective rate of 4.99sps.
921 */
922 case IIO_CHAN_INFO_SAMP_FREQ:
923 freq = val * MILLI + val2 / MILLI;
924 for (i = st->info->odr_start_value; i < st->info->num_sinc5_data_rates - 1; i++)
925 if (freq >= st->info->sinc5_data_rates[i])
926 break;
927
928 cfg = &st->channels[chan->address].cfg;
929 cfg->odr = i;
930 cfg->live = false;
931 break;
932
933 default:
934 ret = -EINVAL;
935 break;
936 }
937
938 iio_device_release_direct_mode(indio_dev);
939 return ret;
940 }
941
942 static int ad7173_update_scan_mode(struct iio_dev *indio_dev,
943 const unsigned long *scan_mask)
944 {
945 struct ad7173_state *st = iio_priv(indio_dev);
946 int i, ret;
947
948 for (i = 0; i < indio_dev->num_channels; i++) {
949 if (test_bit(i, scan_mask))
950 ret = ad7173_set_channel(&st->sd, i);
951 else
952 ret = ad_sd_write_reg(&st->sd, AD7173_REG_CH(i), 2, 0);
953 if (ret < 0)
954 return ret;
955 }
956
957 return 0;
958 }
959
960 static int ad7173_debug_reg_access(struct iio_dev *indio_dev, unsigned int reg,
961 unsigned int writeval, unsigned int *readval)
962 {
963 struct ad7173_state *st = iio_priv(indio_dev);
964 u8 reg_size;
965
966 if (reg == AD7173_REG_COMMS)
967 reg_size = 1;
968 else if (reg == AD7173_REG_CRC || reg == AD7173_REG_DATA ||
969 reg >= AD7173_REG_OFFSET(0))
970 reg_size = 3;
971 else
972 reg_size = 2;
973
974 if (readval)
975 return ad_sd_read_reg(&st->sd, reg, reg_size, readval);
976
977 return ad_sd_write_reg(&st->sd, reg, reg_size, writeval);
978 }
979
980 static const struct iio_info ad7173_info = {
981 .read_raw = &ad7173_read_raw,
982 .write_raw = &ad7173_write_raw,
983 .debugfs_reg_access = &ad7173_debug_reg_access,
984 .validate_trigger = ad_sd_validate_trigger,
985 .update_scan_mode = ad7173_update_scan_mode,
986 };
987
988 static const struct iio_chan_spec ad7173_channel_template = {
989 .type = IIO_VOLTAGE,
990 .indexed = 1,
991 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
992 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_SAMP_FREQ),
993 .scan_type = {
994 .sign = 'u',
995 .realbits = 24,
996 .storagebits = 32,
997 .endianness = IIO_BE,
998 },
999 };
1000
1001 static const struct iio_chan_spec ad7173_temp_iio_channel_template = {
1002 .type = IIO_TEMP,
1003 .channel = AD7173_AIN_TEMP_POS,
1004 .channel2 = AD7173_AIN_TEMP_NEG,
1005 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1006 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_OFFSET) |
1007 BIT(IIO_CHAN_INFO_SAMP_FREQ),
1008 .scan_type = {
1009 .sign = 'u',
1010 .realbits = 24,
1011 .storagebits = 32,
1012 .endianness = IIO_BE,
1013 },
1014 };
1015
1016 static void ad7173_disable_regulators(void *data)
1017 {
1018 struct ad7173_state *st = data;
1019
1020 regulator_bulk_disable(ARRAY_SIZE(st->regulators), st->regulators);
1021 }
1022
1023 static void ad7173_clk_disable_unprepare(void *clk)
1024 {
1025 clk_disable_unprepare(clk);
1026 }
1027
1028 static unsigned long ad7173_sel_clk(struct ad7173_state *st,
1029 unsigned int clk_sel)
1030 {
1031 int ret;
1032
1033 st->adc_mode &= ~AD7173_ADC_MODE_CLOCKSEL_MASK;
1034 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK, clk_sel);
1035 ret = ad_sd_write_reg(&st->sd, AD7173_REG_ADC_MODE, 0x2, st->adc_mode);
1036
1037 return ret;
1038 }
1039
1040 static unsigned long ad7173_clk_recalc_rate(struct clk_hw *hw,
1041 unsigned long parent_rate)
1042 {
1043 struct ad7173_state *st = clk_hw_to_ad7173(hw);
1044
1045 return st->info->clock / HZ_PER_KHZ;
1046 }
1047
1048 static int ad7173_clk_output_is_enabled(struct clk_hw *hw)
1049 {
1050 struct ad7173_state *st = clk_hw_to_ad7173(hw);
1051 u32 clk_sel;
1052
1053 clk_sel = FIELD_GET(AD7173_ADC_MODE_CLOCKSEL_MASK, st->adc_mode);
1054 return clk_sel == AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT;
1055 }
1056
1057 static int ad7173_clk_output_prepare(struct clk_hw *hw)
1058 {
1059 struct ad7173_state *st = clk_hw_to_ad7173(hw);
1060
1061 return ad7173_sel_clk(st, AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT);
1062 }
1063
1064 static void ad7173_clk_output_unprepare(struct clk_hw *hw)
1065 {
1066 struct ad7173_state *st = clk_hw_to_ad7173(hw);
1067
1068 ad7173_sel_clk(st, AD7173_ADC_MODE_CLOCKSEL_INT);
1069 }
1070
1071 static const struct clk_ops ad7173_int_clk_ops = {
1072 .recalc_rate = ad7173_clk_recalc_rate,
1073 .is_enabled = ad7173_clk_output_is_enabled,
1074 .prepare = ad7173_clk_output_prepare,
1075 .unprepare = ad7173_clk_output_unprepare,
1076 };
1077
1078 static int ad7173_register_clk_provider(struct iio_dev *indio_dev)
1079 {
1080 struct ad7173_state *st = iio_priv(indio_dev);
1081 struct device *dev = indio_dev->dev.parent;
1082 struct fwnode_handle *fwnode = dev_fwnode(dev);
1083 struct clk_init_data init = {};
1084 int ret;
1085
1086 if (!IS_ENABLED(CONFIG_COMMON_CLK))
1087 return 0;
1088
1089 init.name = fwnode_get_name(fwnode);
1090 init.ops = &ad7173_int_clk_ops;
1091
1092 st->int_clk_hw.init = &init;
1093 ret = devm_clk_hw_register(dev, &st->int_clk_hw);
1094 if (ret)
1095 return ret;
1096
1097 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
1098 &st->int_clk_hw);
1099 }
1100
1101 static int ad4111_validate_current_ain(struct ad7173_state *st,
1102 const unsigned int ain[AD7173_NO_AINS_PER_CHANNEL])
1103 {
1104 struct device *dev = &st->sd.spi->dev;
1105
1106 if (!st->info->has_current_inputs)
1107 return dev_err_probe(dev, -EINVAL,
1108 "Model %s does not support current channels\n",
1109 st->info->name);
1110
1111 if (ain[0] >= ARRAY_SIZE(ad4111_current_channel_config))
1112 return dev_err_probe(dev, -EINVAL,
1113 "For current channels single-channel must be <[0-3]>\n");
1114
1115 return 0;
1116 }
1117
1118 static int ad7173_validate_voltage_ain_inputs(struct ad7173_state *st,
1119 unsigned int ain0, unsigned int ain1)
1120 {
1121 struct device *dev = &st->sd.spi->dev;
1122 bool special_input0, special_input1;
1123
1124 /* (AVDD1-AVSS)/5 power supply monitoring */
1125 if (ain0 == AD7173_AIN_POW_MON_POS && ain1 == AD7173_AIN_POW_MON_NEG &&
1126 st->info->has_pow_supply_monitoring)
1127 return 0;
1128
1129 special_input0 = AD7173_IS_REF_INPUT(ain0) ||
1130 (ain0 == AD4111_VINCOM_INPUT && st->info->has_vincom_input);
1131 special_input1 = AD7173_IS_REF_INPUT(ain1) ||
1132 (ain1 == AD4111_VINCOM_INPUT && st->info->has_vincom_input);
1133
1134 if ((ain0 >= st->info->num_voltage_in && !special_input0) ||
1135 (ain1 >= st->info->num_voltage_in && !special_input1)) {
1136 if (ain0 == AD4111_VINCOM_INPUT || ain1 == AD4111_VINCOM_INPUT)
1137 return dev_err_probe(dev, -EINVAL,
1138 "VINCOM not supported for %s\n", st->info->name);
1139
1140 return dev_err_probe(dev, -EINVAL,
1141 "Input pin number out of range for pair (%d %d).\n",
1142 ain0, ain1);
1143 }
1144
1145 if (AD4111_IS_VINCOM_MISMATCH(ain0, ain1) ||
1146 AD4111_IS_VINCOM_MISMATCH(ain1, ain0))
1147 return dev_err_probe(dev, -EINVAL,
1148 "VINCOM must be paired with inputs having divider.\n");
1149
1150 if (!special_input0 && !special_input1 &&
1151 ((ain0 >= st->info->num_voltage_in_div) !=
1152 (ain1 >= st->info->num_voltage_in_div)))
1153 return dev_err_probe(dev, -EINVAL,
1154 "Both inputs must either have a voltage divider or not have: (%d %d).\n",
1155 ain0, ain1);
1156
1157 return 0;
1158 }
1159
1160 static int ad7173_validate_reference(struct ad7173_state *st, int ref_sel)
1161 {
1162 struct device *dev = &st->sd.spi->dev;
1163 int ret;
1164
1165 if (ref_sel == AD7173_SETUP_REF_SEL_INT_REF && !st->info->has_int_ref)
1166 return dev_err_probe(dev, -EINVAL,
1167 "Internal reference is not available on current model.\n");
1168
1169 if (ref_sel == AD7173_SETUP_REF_SEL_EXT_REF2 && !st->info->has_ref2)
1170 return dev_err_probe(dev, -EINVAL,
1171 "External reference 2 is not available on current model.\n");
1172
1173 ret = ad7173_get_ref_voltage_milli(st, ref_sel);
1174 if (ret < 0)
1175 return dev_err_probe(dev, ret, "Cannot use reference %u\n",
1176 ref_sel);
1177
1178 return 0;
1179 }
1180
1181 static int ad7173_fw_parse_channel_config(struct iio_dev *indio_dev)
1182 {
1183 struct ad7173_channel *chans_st_arr, *chan_st_priv;
1184 struct ad7173_state *st = iio_priv(indio_dev);
1185 struct device *dev = indio_dev->dev.parent;
1186 struct iio_chan_spec *chan_arr, *chan;
1187 unsigned int ain[AD7173_NO_AINS_PER_CHANNEL], chan_index = 0;
1188 int ref_sel, ret, num_channels;
1189
1190 num_channels = device_get_child_node_count(dev);
1191
1192 if (st->info->has_temp)
1193 num_channels++;
1194
1195 if (num_channels == 0)
1196 return dev_err_probe(dev, -ENODATA, "No channels specified\n");
1197
1198 if (num_channels > st->info->num_channels)
1199 return dev_err_probe(dev, -EINVAL,
1200 "Too many channels specified. Maximum is %d, not including temperature channel if supported.\n",
1201 st->info->num_channels);
1202
1203 indio_dev->num_channels = num_channels;
1204 st->num_channels = num_channels;
1205
1206 chan_arr = devm_kcalloc(dev, sizeof(*indio_dev->channels),
1207 st->num_channels, GFP_KERNEL);
1208 if (!chan_arr)
1209 return -ENOMEM;
1210
1211 chans_st_arr = devm_kcalloc(dev, st->num_channels, sizeof(*st->channels),
1212 GFP_KERNEL);
1213 if (!chans_st_arr)
1214 return -ENOMEM;
1215
1216 indio_dev->channels = chan_arr;
1217 st->channels = chans_st_arr;
1218
1219 if (st->info->has_temp) {
1220 chan_arr[chan_index] = ad7173_temp_iio_channel_template;
1221 chan_st_priv = &chans_st_arr[chan_index];
1222 chan_st_priv->ain =
1223 AD7173_CH_ADDRESS(chan_arr[chan_index].channel,
1224 chan_arr[chan_index].channel2);
1225 chan_st_priv->cfg.bipolar = false;
1226 chan_st_priv->cfg.input_buf = st->info->has_input_buf;
1227 chan_st_priv->cfg.ref_sel = AD7173_SETUP_REF_SEL_INT_REF;
1228 st->adc_mode |= AD7173_ADC_MODE_REF_EN;
1229
1230 chan_index++;
1231 }
1232
1233 device_for_each_child_node_scoped(dev, child) {
1234 bool is_current_chan = false;
1235
1236 chan = &chan_arr[chan_index];
1237 *chan = ad7173_channel_template;
1238 chan_st_priv = &chans_st_arr[chan_index];
1239 ret = fwnode_property_read_u32_array(child, "diff-channels",
1240 ain, ARRAY_SIZE(ain));
1241 if (ret) {
1242 ret = fwnode_property_read_u32(child, "single-channel",
1243 ain);
1244 if (ret)
1245 return dev_err_probe(dev, ret,
1246 "Channel must define one of diff-channels or single-channel.\n");
1247
1248 is_current_chan = fwnode_property_read_bool(child, "adi,current-channel");
1249 } else {
1250 chan->differential = true;
1251 }
1252
1253 if (is_current_chan) {
1254 ret = ad4111_validate_current_ain(st, ain);
1255 if (ret)
1256 return ret;
1257 } else {
1258 if (!chan->differential) {
1259 ret = fwnode_property_read_u32(child,
1260 "common-mode-channel", ain + 1);
1261 if (ret)
1262 return dev_err_probe(dev, ret,
1263 "common-mode-channel must be defined for single-ended channels.\n");
1264 }
1265 ret = ad7173_validate_voltage_ain_inputs(st, ain[0], ain[1]);
1266 if (ret)
1267 return ret;
1268 }
1269
1270 ret = fwnode_property_match_property_string(child,
1271 "adi,reference-select",
1272 ad7173_ref_sel_str,
1273 ARRAY_SIZE(ad7173_ref_sel_str));
1274 if (ret < 0)
1275 ref_sel = AD7173_SETUP_REF_SEL_INT_REF;
1276 else
1277 ref_sel = ret;
1278
1279 ret = ad7173_validate_reference(st, ref_sel);
1280 if (ret)
1281 return ret;
1282
1283 if (ref_sel == AD7173_SETUP_REF_SEL_INT_REF)
1284 st->adc_mode |= AD7173_ADC_MODE_REF_EN;
1285 chan_st_priv->cfg.ref_sel = ref_sel;
1286
1287 chan->address = chan_index;
1288 chan->scan_index = chan_index;
1289 chan->channel = ain[0];
1290 chan_st_priv->chan_reg = chan_index;
1291 chan_st_priv->cfg.input_buf = st->info->has_input_buf;
1292 chan_st_priv->cfg.odr = 0;
1293
1294 chan_st_priv->cfg.bipolar = fwnode_property_read_bool(child, "bipolar");
1295 if (chan_st_priv->cfg.bipolar)
1296 chan->info_mask_separate |= BIT(IIO_CHAN_INFO_OFFSET);
1297
1298 if (is_current_chan) {
1299 chan->type = IIO_CURRENT;
1300 chan->differential = false;
1301 chan->channel2 = 0;
1302 chan_st_priv->ain = ad4111_current_channel_config[ain[0]];
1303 } else {
1304 chan_st_priv->cfg.input_buf = st->info->has_input_buf;
1305 chan->channel2 = ain[1];
1306 chan_st_priv->ain = AD7173_CH_ADDRESS(ain[0], ain[1]);
1307 }
1308
1309 chan_index++;
1310 }
1311 return 0;
1312 }
1313
1314 static int ad7173_fw_parse_device_config(struct iio_dev *indio_dev)
1315 {
1316 struct ad7173_state *st = iio_priv(indio_dev);
1317 struct device *dev = indio_dev->dev.parent;
1318 int ret;
1319
1320 st->regulators[0].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_EXT_REF];
1321 st->regulators[1].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_EXT_REF2];
1322 st->regulators[2].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_AVDD1_AVSS];
1323
1324 /*
1325 * If a regulator is not available, it will be set to a dummy regulator.
1326 * Each channel reference is checked with regulator_get_voltage() before
1327 * setting attributes so if any channel uses a dummy supply the driver
1328 * probe will fail.
1329 */
1330 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(st->regulators),
1331 st->regulators);
1332 if (ret)
1333 return dev_err_probe(dev, ret, "Failed to get regulators\n");
1334
1335 ret = regulator_bulk_enable(ARRAY_SIZE(st->regulators), st->regulators);
1336 if (ret)
1337 return dev_err_probe(dev, ret, "Failed to enable regulators\n");
1338
1339 ret = devm_add_action_or_reset(dev, ad7173_disable_regulators, st);
1340 if (ret)
1341 return dev_err_probe(dev, ret,
1342 "Failed to add regulators disable action\n");
1343
1344 ret = device_property_match_property_string(dev, "clock-names",
1345 ad7173_clk_sel,
1346 ARRAY_SIZE(ad7173_clk_sel));
1347 if (ret < 0) {
1348 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK,
1349 AD7173_ADC_MODE_CLOCKSEL_INT);
1350 ad7173_register_clk_provider(indio_dev);
1351 } else {
1352 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK,
1353 AD7173_ADC_MODE_CLOCKSEL_EXT + ret);
1354 st->ext_clk = devm_clk_get(dev, ad7173_clk_sel[ret]);
1355 if (IS_ERR(st->ext_clk))
1356 return dev_err_probe(dev, PTR_ERR(st->ext_clk),
1357 "Failed to get external clock\n");
1358
1359 ret = clk_prepare_enable(st->ext_clk);
1360 if (ret)
1361 return dev_err_probe(dev, ret,
1362 "Failed to enable external clock\n");
1363
1364 ret = devm_add_action_or_reset(dev, ad7173_clk_disable_unprepare,
1365 st->ext_clk);
1366 if (ret)
1367 return ret;
1368 }
1369
1370 ret = fwnode_irq_get_byname(dev_fwnode(dev), "rdy");
1371 if (ret < 0)
1372 return dev_err_probe(dev, ret, "Interrupt 'rdy' is required\n");
1373
1374 ad7173_sigma_delta_info.irq_line = ret;
1375
1376 return ad7173_fw_parse_channel_config(indio_dev);
1377 }
1378
1379 static int ad7173_probe(struct spi_device *spi)
1380 {
1381 struct device *dev = &spi->dev;
1382 struct ad7173_state *st;
1383 struct iio_dev *indio_dev;
1384 int ret;
1385
1386 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1387 if (!indio_dev)
1388 return -ENOMEM;
1389
1390 st = iio_priv(indio_dev);
1391 st->info = spi_get_device_match_data(spi);
1392 if (!st->info)
1393 return -ENODEV;
1394
1395 ida_init(&st->cfg_slots_status);
1396 ret = devm_add_action_or_reset(dev, ad7173_ida_destroy, st);
1397 if (ret)
1398 return ret;
1399
1400 indio_dev->name = st->info->name;
1401 indio_dev->modes = INDIO_DIRECT_MODE;
1402 indio_dev->info = &ad7173_info;
1403
1404 spi->mode = SPI_MODE_3;
1405 spi_setup(spi);
1406
1407 ad7173_sigma_delta_info.num_slots = st->info->num_configs;
1408 ret = ad_sd_init(&st->sd, indio_dev, spi, &ad7173_sigma_delta_info);
1409 if (ret)
1410 return ret;
1411
1412 ret = ad7173_fw_parse_device_config(indio_dev);
1413 if (ret)
1414 return ret;
1415
1416 ret = devm_ad_sd_setup_buffer_and_trigger(dev, indio_dev);
1417 if (ret)
1418 return ret;
1419
1420 ret = ad7173_setup(indio_dev);
1421 if (ret)
1422 return ret;
1423
1424 ret = devm_iio_device_register(dev, indio_dev);
1425 if (ret)
1426 return ret;
1427
1428 if (IS_ENABLED(CONFIG_GPIOLIB))
1429 return ad7173_gpio_init(st);
1430
1431 return 0;
1432 }
1433
1434 static const struct of_device_id ad7173_of_match[] = {
1435 { .compatible = "adi,ad4111", .data = &ad4111_device_info },
1436 { .compatible = "adi,ad4112", .data = &ad4112_device_info },
1437 { .compatible = "adi,ad4114", .data = &ad4114_device_info },
1438 { .compatible = "adi,ad4115", .data = &ad4115_device_info },
1439 { .compatible = "adi,ad4116", .data = &ad4116_device_info },
1440 { .compatible = "adi,ad7172-2", .data = &ad7172_2_device_info },
1441 { .compatible = "adi,ad7172-4", .data = &ad7172_4_device_info },
1442 { .compatible = "adi,ad7173-8", .data = &ad7173_8_device_info },
1443 { .compatible = "adi,ad7175-2", .data = &ad7175_2_device_info },
1444 { .compatible = "adi,ad7175-8", .data = &ad7175_8_device_info },
1445 { .compatible = "adi,ad7176-2", .data = &ad7176_2_device_info },
1446 { .compatible = "adi,ad7177-2", .data = &ad7177_2_device_info },
1447 { }
1448 };
1449 MODULE_DEVICE_TABLE(of, ad7173_of_match);
1450
1451 static const struct spi_device_id ad7173_id_table[] = {
1452 { "ad4111", (kernel_ulong_t)&ad4111_device_info },
1453 { "ad4112", (kernel_ulong_t)&ad4112_device_info },
1454 { "ad4114", (kernel_ulong_t)&ad4114_device_info },
1455 { "ad4115", (kernel_ulong_t)&ad4115_device_info },
1456 { "ad4116", (kernel_ulong_t)&ad4116_device_info },
1457 { "ad7172-2", (kernel_ulong_t)&ad7172_2_device_info },
1458 { "ad7172-4", (kernel_ulong_t)&ad7172_4_device_info },
1459 { "ad7173-8", (kernel_ulong_t)&ad7173_8_device_info },
1460 { "ad7175-2", (kernel_ulong_t)&ad7175_2_device_info },
1461 { "ad7175-8", (kernel_ulong_t)&ad7175_8_device_info },
1462 { "ad7176-2", (kernel_ulong_t)&ad7176_2_device_info },
1463 { "ad7177-2", (kernel_ulong_t)&ad7177_2_device_info },
1464 { }
1465 };
1466 MODULE_DEVICE_TABLE(spi, ad7173_id_table);
1467
1468 static struct spi_driver ad7173_driver = {
1469 .driver = {
1470 .name = "ad7173",
1471 .of_match_table = ad7173_of_match,
1472 },
1473 .probe = ad7173_probe,
1474 .id_table = ad7173_id_table,
1475 };
1476 module_spi_driver(ad7173_driver);
1477
1478 MODULE_IMPORT_NS(IIO_AD_SIGMA_DELTA);
1479 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafo.de>");
1480 MODULE_AUTHOR("Dumitru Ceclan <dumitru.ceclan@analog.com>");
1481 MODULE_DESCRIPTION("Analog Devices AD7173 and similar ADC driver");
1482 MODULE_LICENSE("GPL");
Kernel DRM miscellaneous fixes and cross-tree changes