arch/arm64/kernel/setup.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Based on arch/arm/kernel/setup.c
   4  *
   5  * Copyright (C) 1995-2001 Russell King
   6  * Copyright (C) 2012 ARM Ltd.
   7  */
   8
   9 #include <linux/acpi.h>
  10 #include <linux/export.h>
  11 #include <linux/kernel.h>
  12 #include <linux/stddef.h>
  13 #include <linux/ioport.h>
  14 #include <linux/delay.h>
  15 #include <linux/initrd.h>
  16 #include <linux/console.h>
  17 #include <linux/cache.h>
  18 #include <linux/screen_info.h>
  19 #include <linux/init.h>
  20 #include <linux/kexec.h>
  21 #include <linux/root_dev.h>
  22 #include <linux/cpu.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/smp.h>
  25 #include <linux/fs.h>
  26 #include <linux/panic_notifier.h>
  27 #include <linux/proc_fs.h>
  28 #include <linux/memblock.h>
  29 #include <linux/of_fdt.h>
  30 #include <linux/efi.h>
  31 #include <linux/psci.h>
  32 #include <linux/sched/task.h>
  33 #include <linux/scs.h>
  34 #include <linux/mm.h>
  35
  36 #include <asm/acpi.h>
  37 #include <asm/fixmap.h>
  38 #include <asm/cpu.h>
  39 #include <asm/cputype.h>
  40 #include <asm/daifflags.h>
  41 #include <asm/elf.h>
  42 #include <asm/cpufeature.h>
  43 #include <asm/cpu_ops.h>
  44 #include <asm/kasan.h>
  45 #include <asm/numa.h>
  46 #include <asm/scs.h>
  47 #include <asm/sections.h>
  48 #include <asm/setup.h>
  49 #include <asm/smp_plat.h>
  50 #include <asm/cacheflush.h>
  51 #include <asm/tlbflush.h>
  52 #include <asm/traps.h>
  53 #include <asm/efi.h>
  54 #include <asm/xen/hypervisor.h>
  55 #include <asm/mmu_context.h>
  56
  57 static int num_standard_resources;
  58 static struct resource *standard_resources;
  59
  60 phys_addr_t __fdt_pointer __initdata;
  61 u64 mmu_enabled_at_boot __initdata;
  62
  63 /*
  64  * Standard memory resources
  65  */
  66 static struct resource mem_res[] = {
  67         {
  68                 .name = "Kernel code",
  69                 .start = 0,
  70                 .end = 0,
  71                 .flags = IORESOURCE_SYSTEM_RAM
  72         },
  73         {
  74                 .name = "Kernel data",
  75                 .start = 0,
  76                 .end = 0,
  77                 .flags = IORESOURCE_SYSTEM_RAM
  78         }
  79 };
  80
  81 #define kernel_code mem_res[0]
  82 #define kernel_data mem_res[1]
  83
  84 /*
  85  * The recorded values of x0 .. x3 upon kernel entry.
  86  */
  87 u64 __cacheline_aligned boot_args[4];
  88
  89 void __init smp_setup_processor_id(void)
  90 {
  91         u64 mpidr = read_cpuid_mpidr() & MPIDR_HWID_BITMASK;
  92         set_cpu_logical_map(0, mpidr);
  93
  94         pr_info("Booting Linux on physical CPU 0x%010lx [0x%08x]\n",
  95                 (unsigned long)mpidr, read_cpuid_id());
  96 }
  97
  98 bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
  99 {
 100         return phys_id == cpu_logical_map(cpu);
 101 }
 102
 103 struct mpidr_hash mpidr_hash;
 104 /**
 105  * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
 106  *                        level in order to build a linear index from an
 107  *                        MPIDR value. Resulting algorithm is a collision
 108  *                        free hash carried out through shifting and ORing
 109  */
 110 static void __init smp_build_mpidr_hash(void)
 111 {
 112         u32 i, affinity, fs[4], bits[4], ls;
 113         u64 mask = 0;
 114         /*
 115          * Pre-scan the list of MPIDRS and filter out bits that do
 116          * not contribute to affinity levels, ie they never toggle.
 117          */
 118         for_each_possible_cpu(i)
 119                 mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
 120         pr_debug("mask of set bits %#llx\n", mask);
 121         /*
 122          * Find and stash the last and first bit set at all affinity levels to
 123          * check how many bits are required to represent them.
 124          */
 125         for (i = 0; i < 4; i++) {
 126                 affinity = MPIDR_AFFINITY_LEVEL(mask, i);
 127                 /*
 128                  * Find the MSB bit and LSB bits position
 129                  * to determine how many bits are required
 130                  * to express the affinity level.
 131                  */
 132                 ls = fls(affinity);
 133                 fs[i] = affinity ? ffs(affinity) - 1 : 0;
 134                 bits[i] = ls - fs[i];
 135         }
 136         /*
 137          * An index can be created from the MPIDR_EL1 by isolating the
 138          * significant bits at each affinity level and by shifting
 139          * them in order to compress the 32 bits values space to a
 140          * compressed set of values. This is equivalent to hashing
 141          * the MPIDR_EL1 through shifting and ORing. It is a collision free
 142          * hash though not minimal since some levels might contain a number
 143          * of CPUs that is not an exact power of 2 and their bit
 144          * representation might contain holes, eg MPIDR_EL1[7:0] = {0x2, 0x80}.
 145          */
 146         mpidr_hash.shift_aff[0] = MPIDR_LEVEL_SHIFT(0) + fs[0];
 147         mpidr_hash.shift_aff[1] = MPIDR_LEVEL_SHIFT(1) + fs[1] - bits[0];
 148         mpidr_hash.shift_aff[2] = MPIDR_LEVEL_SHIFT(2) + fs[2] -
 149                                                 (bits[1] + bits[0]);
 150         mpidr_hash.shift_aff[3] = MPIDR_LEVEL_SHIFT(3) +
 151                                   fs[3] - (bits[2] + bits[1] + bits[0]);
 152         mpidr_hash.mask = mask;
 153         mpidr_hash.bits = bits[3] + bits[2] + bits[1] + bits[0];
 154         pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] aff3[%u] mask[%#llx] bits[%u]\n",
 155                 mpidr_hash.shift_aff[0],
 156                 mpidr_hash.shift_aff[1],
 157                 mpidr_hash.shift_aff[2],
 158                 mpidr_hash.shift_aff[3],
 159                 mpidr_hash.mask,
 160                 mpidr_hash.bits);
 161         /*
 162          * 4x is an arbitrary value used to warn on a hash table much bigger
 163          * than expected on most systems.
 164          */
 165         if (mpidr_hash_size() > 4 * num_possible_cpus())
 166                 pr_warn("Large number of MPIDR hash buckets detected\n");
 167 }
 168
 169 static void __init setup_machine_fdt(phys_addr_t dt_phys)
 170 {
 171         int size;
 172         void *dt_virt = fixmap_remap_fdt(dt_phys, &size, PAGE_KERNEL);
 173         const char *name;
 174
 175         if (dt_virt)
 176                 memblock_reserve(dt_phys, size);
 177
 178         if (!dt_virt || !early_init_dt_scan(dt_virt)) {
 179                 pr_crit("\n"
 180                         "Error: invalid device tree blob at physical address %pa (virtual address 0x%px)\n"
 181                         "The dtb must be 8-byte aligned and must not exceed 2 MB in size\n"
 182                         "\nPlease check your bootloader.",
 183                         &dt_phys, dt_virt);
 184
 185                 /*
 186                  * Note that in this _really_ early stage we cannot even BUG()
 187                  * or oops, so the least terrible thing to do is cpu_relax(),
 188                  * or else we could end-up printing non-initialized data, etc.
 189                  */
 190                 while (true)
 191                         cpu_relax();
 192         }
 193
 194         /* Early fixups are done, map the FDT as read-only now */
 195         fixmap_remap_fdt(dt_phys, &size, PAGE_KERNEL_RO);
 196
 197         name = of_flat_dt_get_machine_name();
 198         if (!name)
 199                 return;
 200
 201         pr_info("Machine model: %s\n", name);
 202         dump_stack_set_arch_desc("%s (DT)", name);
 203 }
 204
 205 static void __init request_standard_resources(void)
 206 {
 207         struct memblock_region *region;
 208         struct resource *res;
 209         unsigned long i = 0;
 210         size_t res_size;
 211
 212         kernel_code.start   = __pa_symbol(_stext);
 213         kernel_code.end     = __pa_symbol(__init_begin - 1);
 214         kernel_data.start   = __pa_symbol(_sdata);
 215         kernel_data.end     = __pa_symbol(_end - 1);
 216         insert_resource(&iomem_resource, &kernel_code);
 217         insert_resource(&iomem_resource, &kernel_data);
 218
 219         num_standard_resources = memblock.memory.cnt;
 220         res_size = num_standard_resources * sizeof(*standard_resources);
 221         standard_resources = memblock_alloc(res_size, SMP_CACHE_BYTES);
 222         if (!standard_resources)
 223                 panic("%s: Failed to allocate %zu bytes\n", __func__, res_size);
 224
 225         for_each_mem_region(region) {
 226                 res = &standard_resources[i++];
 227                 if (memblock_is_nomap(region)) {
 228                         res->name  = "reserved";
 229                         res->flags = IORESOURCE_MEM;
 230                         res->start = __pfn_to_phys(memblock_region_reserved_base_pfn(region));
 231                         res->end = __pfn_to_phys(memblock_region_reserved_end_pfn(region)) - 1;
 232                 } else {
 233                         res->name  = "System RAM";
 234                         res->flags = IORESOURCE_SYSTEM_RAM | IORESOURCE_BUSY;
 235                         res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
 236                         res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
 237                 }
 238
 239                 insert_resource(&iomem_resource, res);
 240         }
 241 }
 242
 243 static int __init reserve_memblock_reserved_regions(void)
 244 {
 245         u64 i, j;
 246
 247         for (i = 0; i < num_standard_resources; ++i) {
 248                 struct resource *mem = &standard_resources[i];
 249                 phys_addr_t r_start, r_end, mem_size = resource_size(mem);
 250
 251                 if (!memblock_is_region_reserved(mem->start, mem_size))
 252                         continue;
 253
 254                 for_each_reserved_mem_range(j, &r_start, &r_end) {
 255                         resource_size_t start, end;
 256
 257                         start = max(PFN_PHYS(PFN_DOWN(r_start)), mem->start);
 258                         end = min(PFN_PHYS(PFN_UP(r_end)) - 1, mem->end);
 259
 260                         if (start > mem->end || end < mem->start)
 261                                 continue;
 262
 263                         reserve_region_with_split(mem, start, end, "reserved");
 264                 }
 265         }
 266
 267         return 0;
 268 }
 269 arch_initcall(reserve_memblock_reserved_regions);
 270
 271 u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID };
 272
 273 u64 cpu_logical_map(unsigned int cpu)
 274 {
 275         return __cpu_logical_map[cpu];
 276 }
 277
 278 void __init __no_sanitize_address setup_arch(char **cmdline_p)
 279 {
 280         setup_initial_init_mm(_stext, _etext, _edata, _end);
 281
 282         *cmdline_p = boot_command_line;
 283
 284         kaslr_init();
 285
 286         early_fixmap_init();
 287         early_ioremap_init();
 288
 289         setup_machine_fdt(__fdt_pointer);
 290
 291         /*
 292          * Initialise the static keys early as they may be enabled by the
 293          * cpufeature code and early parameters.
 294          */
 295         jump_label_init();
 296         parse_early_param();
 297
 298         dynamic_scs_init();
 299
 300         /*
 301          * The primary CPU enters the kernel with all DAIF exceptions masked.
 302          *
 303          * We must unmask Debug and SError before preemption or scheduling is
 304          * possible to ensure that these are consistently unmasked across
 305          * threads, and we want to unmask SError as soon as possible after
 306          * initializing earlycon so that we can report any SErrors immediately.
 307          *
 308          * IRQ and FIQ will be unmasked after the root irqchip has been
 309          * detected and initialized.
 310          */
 311         local_daif_restore(DAIF_PROCCTX_NOIRQ);
 312
 313         /*
 314          * TTBR0 is only used for the identity mapping at this stage. Make it
 315          * point to zero page to avoid speculatively fetching new entries.
 316          */
 317         cpu_uninstall_idmap();
 318
 319         xen_early_init();
 320         efi_init();
 321
 322         if (!efi_enabled(EFI_BOOT)) {
 323                 if ((u64)_text % MIN_KIMG_ALIGN)
 324                         pr_warn(FW_BUG "Kernel image misaligned at boot, please fix your bootloader!");
 325                 WARN_TAINT(mmu_enabled_at_boot, TAINT_FIRMWARE_WORKAROUND,
 326                            FW_BUG "Booted with MMU enabled!");
 327         }
 328
 329         arm64_memblock_init();
 330
 331         paging_init();
 332
 333         acpi_table_upgrade();
 334
 335         /* Parse the ACPI tables for possible boot-time configuration */
 336         acpi_boot_table_init();
 337
 338         if (acpi_disabled)
 339                 unflatten_device_tree();
 340
 341         bootmem_init();
 342
 343         kasan_init();
 344
 345         request_standard_resources();
 346
 347         early_ioremap_reset();
 348
 349         if (acpi_disabled)
 350                 psci_dt_init();
 351         else
 352                 psci_acpi_init();
 353
 354         init_bootcpu_ops();
 355         smp_init_cpus();
 356         smp_build_mpidr_hash();
 357
 358 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
 359         /*
 360          * Make sure init_thread_info.ttbr0 always generates translation
 361          * faults in case uaccess_enable() is inadvertently called by the init
 362          * thread.
 363          */
 364         init_task.thread_info.ttbr0 = phys_to_ttbr(__pa_symbol(reserved_pg_dir));
 365 #endif
 366
 367         if (boot_args[1] || boot_args[2] || boot_args[3]) {
 368                 pr_err("WARNING: x1-x3 nonzero in violation of boot protocol:\n"
 369                         "\tx1: %016llx\n\tx2: %016llx\n\tx3: %016llx\n"
 370                         "This indicates a broken bootloader or old kernel\n",
 371                         boot_args[1], boot_args[2], boot_args[3]);
 372         }
 373 }
 374
 375 static inline bool cpu_can_disable(unsigned int cpu)
 376 {
 377 #ifdef CONFIG_HOTPLUG_CPU
 378         const struct cpu_operations *ops = get_cpu_ops(cpu);
 379
 380         if (ops && ops->cpu_can_disable)
 381                 return ops->cpu_can_disable(cpu);
 382 #endif
 383         return false;
 384 }
 385
 386 bool arch_cpu_is_hotpluggable(int num)
 387 {
 388         return cpu_can_disable(num);
 389 }
 390
 391 static void dump_kernel_offset(void)
 392 {
 393         const unsigned long offset = kaslr_offset();
 394
 395         if (IS_ENABLED(CONFIG_RANDOMIZE_BASE) && offset > 0) {
 396                 pr_emerg("Kernel Offset: 0x%lx from 0x%lx\n",
 397                          offset, KIMAGE_VADDR);
 398                 pr_emerg("PHYS_OFFSET: 0x%llx\n", PHYS_OFFSET);
 399         } else {
 400                 pr_emerg("Kernel Offset: disabled\n");
 401         }
 402 }
 403
 404 static int arm64_panic_block_dump(struct notifier_block *self,
 405                                   unsigned long v, void *p)
 406 {
 407         dump_kernel_offset();
 408         dump_cpu_features();
 409         dump_mem_limit();
 410         return 0;
 411 }
 412
 413 static struct notifier_block arm64_panic_block = {
 414         .notifier_call = arm64_panic_block_dump
 415 };
 416
 417 static int __init register_arm64_panic_block(void)
 418 {
 419         atomic_notifier_chain_register(&panic_notifier_list,
 420                                        &arm64_panic_block);
 421         return 0;
 422 }
 423 device_initcall(register_arm64_panic_block);
 424
 425 static int __init check_mmu_enabled_at_boot(void)
 426 {
 427         if (!efi_enabled(EFI_BOOT) && mmu_enabled_at_boot)
 428                 panic("Non-EFI boot detected with MMU and caches enabled");
 429         return 0;
 430 }
 431 device_initcall_sync(check_mmu_enabled_at_boot);