?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
drm/panthor: Don't add write fences to the shared BOs
[drm/drm-misc.git] / arch / x86 / kernel / cpu / intel.c
blobe7656cbef68d54ba8459991984d130568c0c5c47
1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/kernel.h>
3 #include <linux/pgtable.h>
4
5 #include <linux/string.h>
6 #include <linux/bitops.h>
7 #include <linux/smp.h>
8 #include <linux/sched.h>
9 #include <linux/sched/clock.h>
10 #include <linux/semaphore.h>
11 #include <linux/thread_info.h>
12 #include <linux/init.h>
13 #include <linux/uaccess.h>
14 #include <linux/workqueue.h>
15 #include <linux/delay.h>
16 #include <linux/cpuhotplug.h>
17
18 #include <asm/cpufeature.h>
19 #include <asm/msr.h>
20 #include <asm/bugs.h>
21 #include <asm/cpu.h>
22 #include <asm/intel-family.h>
23 #include <asm/microcode.h>
24 #include <asm/hwcap2.h>
25 #include <asm/elf.h>
26 #include <asm/cpu_device_id.h>
27 #include <asm/cmdline.h>
28 #include <asm/traps.h>
29 #include <asm/resctrl.h>
30 #include <asm/numa.h>
31 #include <asm/thermal.h>
32
33 #ifdef CONFIG_X86_64
34 #include <linux/topology.h>
35 #endif
36
37 #include "cpu.h"
38
39 #ifdef CONFIG_X86_LOCAL_APIC
40 #include <asm/mpspec.h>
41 #include <asm/apic.h>
42 #endif
43
44 enum split_lock_detect_state {
45 sld_off = 0,
46 sld_warn,
47 sld_fatal,
48 sld_ratelimit,
49 };
50
51 /*
52 * Default to sld_off because most systems do not support split lock detection.
53 * sld_state_setup() will switch this to sld_warn on systems that support
54 * split lock/bus lock detect, unless there is a command line override.
55 */
56 static enum split_lock_detect_state sld_state __ro_after_init = sld_off;
57 static u64 msr_test_ctrl_cache __ro_after_init;
58
59 /*
60 * With a name like MSR_TEST_CTL it should go without saying, but don't touch
61 * MSR_TEST_CTL unless the CPU is one of the whitelisted models. Writing it
62 * on CPUs that do not support SLD can cause fireworks, even when writing '0'.
63 */
64 static bool cpu_model_supports_sld __ro_after_init;
65
66 /*
67 * Processors which have self-snooping capability can handle conflicting
68 * memory type across CPUs by snooping its own cache. However, there exists
69 * CPU models in which having conflicting memory types still leads to
70 * unpredictable behavior, machine check errors, or hangs. Clear this
71 * feature to prevent its use on machines with known erratas.
72 */
73 static void check_memory_type_self_snoop_errata(struct cpuinfo_x86 *c)
74 {
75 switch (c->x86_vfm) {
76 case INTEL_CORE_YONAH:
77 case INTEL_CORE2_MEROM:
78 case INTEL_CORE2_MEROM_L:
79 case INTEL_CORE2_PENRYN:
80 case INTEL_CORE2_DUNNINGTON:
81 case INTEL_NEHALEM:
82 case INTEL_NEHALEM_G:
83 case INTEL_NEHALEM_EP:
84 case INTEL_NEHALEM_EX:
85 case INTEL_WESTMERE:
86 case INTEL_WESTMERE_EP:
87 case INTEL_SANDYBRIDGE:
88 setup_clear_cpu_cap(X86_FEATURE_SELFSNOOP);
89 }
90 }
91
92 static bool ring3mwait_disabled __read_mostly;
93
94 static int __init ring3mwait_disable(char *__unused)
95 {
96 ring3mwait_disabled = true;
97 return 1;
98 }
99 __setup("ring3mwait=disable", ring3mwait_disable);
100
101 static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)
102 {
103 /*
104 * Ring 3 MONITOR/MWAIT feature cannot be detected without
105 * cpu model and family comparison.
106 */
107 if (c->x86 != 6)
108 return;
109 switch (c->x86_vfm) {
110 case INTEL_XEON_PHI_KNL:
111 case INTEL_XEON_PHI_KNM:
112 break;
113 default:
114 return;
115 }
116
117 if (ring3mwait_disabled)
118 return;
119
120 set_cpu_cap(c, X86_FEATURE_RING3MWAIT);
121 this_cpu_or(msr_misc_features_shadow,
122 1UL << MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT);
123
124 if (c == &boot_cpu_data)
125 ELF_HWCAP2 |= HWCAP2_RING3MWAIT;
126 }
127
128 /*
129 * Early microcode releases for the Spectre v2 mitigation were broken.
130 * Information taken from;
131 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf
132 * - https://kb.vmware.com/s/article/52345
133 * - Microcode revisions observed in the wild
134 * - Release note from 20180108 microcode release
135 */
136 struct sku_microcode {
137 u32 vfm;
138 u8 stepping;
139 u32 microcode;
140 };
141 static const struct sku_microcode spectre_bad_microcodes[] = {
142 { INTEL_KABYLAKE, 0x0B, 0x80 },
143 { INTEL_KABYLAKE, 0x0A, 0x80 },
144 { INTEL_KABYLAKE, 0x09, 0x80 },
145 { INTEL_KABYLAKE_L, 0x0A, 0x80 },
146 { INTEL_KABYLAKE_L, 0x09, 0x80 },
147 { INTEL_SKYLAKE_X, 0x03, 0x0100013e },
148 { INTEL_SKYLAKE_X, 0x04, 0x0200003c },
149 { INTEL_BROADWELL, 0x04, 0x28 },
150 { INTEL_BROADWELL_G, 0x01, 0x1b },
151 { INTEL_BROADWELL_D, 0x02, 0x14 },
152 { INTEL_BROADWELL_D, 0x03, 0x07000011 },
153 { INTEL_BROADWELL_X, 0x01, 0x0b000025 },
154 { INTEL_HASWELL_L, 0x01, 0x21 },
155 { INTEL_HASWELL_G, 0x01, 0x18 },
156 { INTEL_HASWELL, 0x03, 0x23 },
157 { INTEL_HASWELL_X, 0x02, 0x3b },
158 { INTEL_HASWELL_X, 0x04, 0x10 },
159 { INTEL_IVYBRIDGE_X, 0x04, 0x42a },
160 /* Observed in the wild */
161 { INTEL_SANDYBRIDGE_X, 0x06, 0x61b },
162 { INTEL_SANDYBRIDGE_X, 0x07, 0x712 },
163 };
164
165 static bool bad_spectre_microcode(struct cpuinfo_x86 *c)
166 {
167 int i;
168
169 /*
170 * We know that the hypervisor lie to us on the microcode version so
171 * we may as well hope that it is running the correct version.
172 */
173 if (cpu_has(c, X86_FEATURE_HYPERVISOR))
174 return false;
175
176 for (i = 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) {
177 if (c->x86_vfm == spectre_bad_microcodes[i].vfm &&
178 c->x86_stepping == spectre_bad_microcodes[i].stepping)
179 return (c->microcode <= spectre_bad_microcodes[i].microcode);
180 }
181 return false;
182 }
183
184 #define MSR_IA32_TME_ACTIVATE 0x982
185
186 /* Helpers to access TME_ACTIVATE MSR */
187 #define TME_ACTIVATE_LOCKED(x) (x & 0x1)
188 #define TME_ACTIVATE_ENABLED(x) (x & 0x2)
189
190 #define TME_ACTIVATE_KEYID_BITS(x) ((x >> 32) & 0xf) /* Bits 35:32 */
191
192 static void detect_tme_early(struct cpuinfo_x86 *c)
193 {
194 u64 tme_activate;
195 int keyid_bits;
196
197 rdmsrl(MSR_IA32_TME_ACTIVATE, tme_activate);
198
199 if (!TME_ACTIVATE_LOCKED(tme_activate) || !TME_ACTIVATE_ENABLED(tme_activate)) {
200 pr_info_once("x86/tme: not enabled by BIOS\n");
201 clear_cpu_cap(c, X86_FEATURE_TME);
202 return;
203 }
204 pr_info_once("x86/tme: enabled by BIOS\n");
205 keyid_bits = TME_ACTIVATE_KEYID_BITS(tme_activate);
206 if (!keyid_bits)
207 return;
208
209 /*
210 * KeyID bits are set by BIOS and can be present regardless
211 * of whether the kernel is using them. They effectively lower
212 * the number of physical address bits.
213 *
214 * Update cpuinfo_x86::x86_phys_bits accordingly.
215 */
216 c->x86_phys_bits -= keyid_bits;
217 pr_info_once("x86/mktme: BIOS enabled: x86_phys_bits reduced by %d\n",
218 keyid_bits);
219 }
220
221 void intel_unlock_cpuid_leafs(struct cpuinfo_x86 *c)
222 {
223 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
224 return;
225
226 if (c->x86 < 6 || (c->x86 == 6 && c->x86_model < 0xd))
227 return;
228
229 /*
230 * The BIOS can have limited CPUID to leaf 2, which breaks feature
231 * enumeration. Unlock it and update the maximum leaf info.
232 */
233 if (msr_clear_bit(MSR_IA32_MISC_ENABLE, MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0)
234 c->cpuid_level = cpuid_eax(0);
235 }
236
237 static void early_init_intel(struct cpuinfo_x86 *c)
238 {
239 u64 misc_enable;
240
241 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
242 (c->x86 == 0x6 && c->x86_model >= 0x0e))
243 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
244
245 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64))
246 c->microcode = intel_get_microcode_revision();
247
248 /* Now if any of them are set, check the blacklist and clear the lot */
249 if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) ||
250 cpu_has(c, X86_FEATURE_INTEL_STIBP) ||
251 cpu_has(c, X86_FEATURE_IBRS) || cpu_has(c, X86_FEATURE_IBPB) ||
252 cpu_has(c, X86_FEATURE_STIBP)) && bad_spectre_microcode(c)) {
253 pr_warn("Intel Spectre v2 broken microcode detected; disabling Speculation Control\n");
254 setup_clear_cpu_cap(X86_FEATURE_IBRS);
255 setup_clear_cpu_cap(X86_FEATURE_IBPB);
256 setup_clear_cpu_cap(X86_FEATURE_STIBP);
257 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL);
258 setup_clear_cpu_cap(X86_FEATURE_MSR_SPEC_CTRL);
259 setup_clear_cpu_cap(X86_FEATURE_INTEL_STIBP);
260 setup_clear_cpu_cap(X86_FEATURE_SSBD);
261 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL_SSBD);
262 }
263
264 /*
265 * Atom erratum AAE44/AAF40/AAG38/AAH41:
266 *
267 * A race condition between speculative fetches and invalidating
268 * a large page. This is worked around in microcode, but we
269 * need the microcode to have already been loaded... so if it is
270 * not, recommend a BIOS update and disable large pages.
271 */
272 if (c->x86_vfm == INTEL_ATOM_BONNELL && c->x86_stepping <= 2 &&
273 c->microcode < 0x20e) {
274 pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n");
275 clear_cpu_cap(c, X86_FEATURE_PSE);
276 }
277
278 #ifdef CONFIG_X86_64
279 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
280 #else
281 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
282 if (c->x86 == 15 && c->x86_cache_alignment == 64)
283 c->x86_cache_alignment = 128;
284 #endif
285
286 /* CPUID workaround for 0F33/0F34 CPU */
287 if (c->x86 == 0xF && c->x86_model == 0x3
288 && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4))
289 c->x86_phys_bits = 36;
290
291 /*
292 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
293 * with P/T states and does not stop in deep C-states.
294 *
295 * It is also reliable across cores and sockets. (but not across
296 * cabinets - we turn it off in that case explicitly.)
297 */
298 if (c->x86_power & (1 << 8)) {
299 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
300 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
301 }
302
303 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */
304 switch (c->x86_vfm) {
305 case INTEL_ATOM_SALTWELL_MID:
306 case INTEL_ATOM_SALTWELL_TABLET:
307 case INTEL_ATOM_SILVERMONT_MID:
308 case INTEL_ATOM_AIRMONT_NP:
309 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
310 break;
311 }
312
313 /*
314 * PAT is broken on early family 6 CPUs, the last of which
315 * is "Yonah" where the erratum is named "AN7":
316 *
317 * Page with PAT (Page Attribute Table) Set to USWC
318 * (Uncacheable Speculative Write Combine) While
319 * Associated MTRR (Memory Type Range Register) Is UC
320 * (Uncacheable) May Consolidate to UC
321 *
322 * Disable PAT and fall back to MTRR on these CPUs.
323 */
324 if (c->x86_vfm >= INTEL_PENTIUM_PRO &&
325 c->x86_vfm <= INTEL_CORE_YONAH)
326 clear_cpu_cap(c, X86_FEATURE_PAT);
327
328 /*
329 * If fast string is not enabled in IA32_MISC_ENABLE for any reason,
330 * clear the fast string and enhanced fast string CPU capabilities.
331 */
332 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
333 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
334 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) {
335 pr_info("Disabled fast string operations\n");
336 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD);
337 setup_clear_cpu_cap(X86_FEATURE_ERMS);
338 }
339 }
340
341 /*
342 * Intel Quark Core DevMan_001.pdf section 6.4.11
343 * "The operating system also is required to invalidate (i.e., flush)
344 * the TLB when any changes are made to any of the page table entries.
345 * The operating system must reload CR3 to cause the TLB to be flushed"
346 *
347 * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h
348 * should be false so that __flush_tlb_all() causes CR3 instead of CR4.PGE
349 * to be modified.
350 */
351 if (c->x86_vfm == INTEL_QUARK_X1000) {
352 pr_info("Disabling PGE capability bit\n");
353 setup_clear_cpu_cap(X86_FEATURE_PGE);
354 }
355
356 check_memory_type_self_snoop_errata(c);
357
358 /*
359 * Adjust the number of physical bits early because it affects the
360 * valid bits of the MTRR mask registers.
361 */
362 if (cpu_has(c, X86_FEATURE_TME))
363 detect_tme_early(c);
364 }
365
366 static void bsp_init_intel(struct cpuinfo_x86 *c)
367 {
368 resctrl_cpu_detect(c);
369 }
370
371 #ifdef CONFIG_X86_32
372 /*
373 * Early probe support logic for ppro memory erratum #50
374 *
375 * This is called before we do cpu ident work
376 */
377
378 int ppro_with_ram_bug(void)
379 {
380 /* Uses data from early_cpu_detect now */
381 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
382 boot_cpu_data.x86 == 6 &&
383 boot_cpu_data.x86_model == 1 &&
384 boot_cpu_data.x86_stepping < 8) {
385 pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n");
386 return 1;
387 }
388 return 0;
389 }
390
391 static void intel_smp_check(struct cpuinfo_x86 *c)
392 {
393 /* calling is from identify_secondary_cpu() ? */
394 if (!c->cpu_index)
395 return;
396
397 /*
398 * Mask B, Pentium, but not Pentium MMX
399 */
400 if (c->x86 == 5 &&
401 c->x86_stepping >= 1 && c->x86_stepping <= 4 &&
402 c->x86_model <= 3) {
403 /*
404 * Remember we have B step Pentia with bugs
405 */
406 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
407 "with B stepping processors.\n");
408 }
409 }
410
411 static int forcepae;
412 static int __init forcepae_setup(char *__unused)
413 {
414 forcepae = 1;
415 return 1;
416 }
417 __setup("forcepae", forcepae_setup);
418
419 static void intel_workarounds(struct cpuinfo_x86 *c)
420 {
421 #ifdef CONFIG_X86_F00F_BUG
422 /*
423 * All models of Pentium and Pentium with MMX technology CPUs
424 * have the F0 0F bug, which lets nonprivileged users lock up the
425 * system. Announce that the fault handler will be checking for it.
426 * The Quark is also family 5, but does not have the same bug.
427 */
428 clear_cpu_bug(c, X86_BUG_F00F);
429 if (c->x86 == 5 && c->x86_model < 9) {
430 static int f00f_workaround_enabled;
431
432 set_cpu_bug(c, X86_BUG_F00F);
433 if (!f00f_workaround_enabled) {
434 pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n");
435 f00f_workaround_enabled = 1;
436 }
437 }
438 #endif
439
440 /*
441 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
442 * model 3 mask 3
443 */
444 if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633)
445 clear_cpu_cap(c, X86_FEATURE_SEP);
446
447 /*
448 * PAE CPUID issue: many Pentium M report no PAE but may have a
449 * functionally usable PAE implementation.
450 * Forcefully enable PAE if kernel parameter "forcepae" is present.
451 */
452 if (forcepae) {
453 pr_warn("PAE forced!\n");
454 set_cpu_cap(c, X86_FEATURE_PAE);
455 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
456 }
457
458 /*
459 * P4 Xeon erratum 037 workaround.
460 * Hardware prefetcher may cause stale data to be loaded into the cache.
461 */
462 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) {
463 if (msr_set_bit(MSR_IA32_MISC_ENABLE,
464 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) {
465 pr_info("CPU: C0 stepping P4 Xeon detected.\n");
466 pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n");
467 }
468 }
469
470 /*
471 * See if we have a good local APIC by checking for buggy Pentia,
472 * i.e. all B steppings and the C2 stepping of P54C when using their
473 * integrated APIC (see 11AP erratum in "Pentium Processor
474 * Specification Update").
475 */
476 if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
477 (c->x86_stepping < 0x6 || c->x86_stepping == 0xb))
478 set_cpu_bug(c, X86_BUG_11AP);
479
480
481 #ifdef CONFIG_X86_INTEL_USERCOPY
482 /*
483 * Set up the preferred alignment for movsl bulk memory moves
484 */
485 switch (c->x86) {
486 case 4: /* 486: untested */
487 break;
488 case 5: /* Old Pentia: untested */
489 break;
490 case 6: /* PII/PIII only like movsl with 8-byte alignment */
491 movsl_mask.mask = 7;
492 break;
493 case 15: /* P4 is OK down to 8-byte alignment */
494 movsl_mask.mask = 7;
495 break;
496 }
497 #endif
498
499 intel_smp_check(c);
500 }
501 #else
502 static void intel_workarounds(struct cpuinfo_x86 *c)
503 {
504 }
505 #endif
506
507 static void srat_detect_node(struct cpuinfo_x86 *c)
508 {
509 #ifdef CONFIG_NUMA
510 unsigned node;
511 int cpu = smp_processor_id();
512
513 /* Don't do the funky fallback heuristics the AMD version employs
514 for now. */
515 node = numa_cpu_node(cpu);
516 if (node == NUMA_NO_NODE || !node_online(node)) {
517 /* reuse the value from init_cpu_to_node() */
518 node = cpu_to_node(cpu);
519 }
520 numa_set_node(cpu, node);
521 #endif
522 }
523
524 static void init_cpuid_fault(struct cpuinfo_x86 *c)
525 {
526 u64 msr;
527
528 if (!rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) {
529 if (msr & MSR_PLATFORM_INFO_CPUID_FAULT)
530 set_cpu_cap(c, X86_FEATURE_CPUID_FAULT);
531 }
532 }
533
534 static void init_intel_misc_features(struct cpuinfo_x86 *c)
535 {
536 u64 msr;
537
538 if (rdmsrl_safe(MSR_MISC_FEATURES_ENABLES, &msr))
539 return;
540
541 /* Clear all MISC features */
542 this_cpu_write(msr_misc_features_shadow, 0);
543
544 /* Check features and update capabilities and shadow control bits */
545 init_cpuid_fault(c);
546 probe_xeon_phi_r3mwait(c);
547
548 msr = this_cpu_read(msr_misc_features_shadow);
549 wrmsrl(MSR_MISC_FEATURES_ENABLES, msr);
550 }
551
552 static void split_lock_init(void);
553 static void bus_lock_init(void);
554
555 static void init_intel(struct cpuinfo_x86 *c)
556 {
557 early_init_intel(c);
558
559 intel_workarounds(c);
560
561 init_intel_cacheinfo(c);
562
563 if (c->cpuid_level > 9) {
564 unsigned eax = cpuid_eax(10);
565 /* Check for version and the number of counters */
566 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
567 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
568 }
569
570 if (cpu_has(c, X86_FEATURE_XMM2))
571 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
572
573 if (boot_cpu_has(X86_FEATURE_DS)) {
574 unsigned int l1, l2;
575
576 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
577 if (!(l1 & MSR_IA32_MISC_ENABLE_BTS_UNAVAIL))
578 set_cpu_cap(c, X86_FEATURE_BTS);
579 if (!(l1 & MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL))
580 set_cpu_cap(c, X86_FEATURE_PEBS);
581 }
582
583 if (boot_cpu_has(X86_FEATURE_CLFLUSH) &&
584 (c->x86_vfm == INTEL_CORE2_DUNNINGTON ||
585 c->x86_vfm == INTEL_NEHALEM_EX ||
586 c->x86_vfm == INTEL_WESTMERE_EX))
587 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR);
588
589 if (boot_cpu_has(X86_FEATURE_MWAIT) && c->x86_vfm == INTEL_ATOM_GOLDMONT)
590 set_cpu_bug(c, X86_BUG_MONITOR);
591
592 #ifdef CONFIG_X86_64
593 if (c->x86 == 15)
594 c->x86_cache_alignment = c->x86_clflush_size * 2;
595 if (c->x86 == 6)
596 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
597 #else
598 /*
599 * Names for the Pentium II/Celeron processors
600 * detectable only by also checking the cache size.
601 * Dixon is NOT a Celeron.
602 */
603 if (c->x86 == 6) {
604 unsigned int l2 = c->x86_cache_size;
605 char *p = NULL;
606
607 switch (c->x86_model) {
608 case 5:
609 if (l2 == 0)
610 p = "Celeron (Covington)";
611 else if (l2 == 256)
612 p = "Mobile Pentium II (Dixon)";
613 break;
614
615 case 6:
616 if (l2 == 128)
617 p = "Celeron (Mendocino)";
618 else if (c->x86_stepping == 0 || c->x86_stepping == 5)
619 p = "Celeron-A";
620 break;
621
622 case 8:
623 if (l2 == 128)
624 p = "Celeron (Coppermine)";
625 break;
626 }
627
628 if (p)
629 strcpy(c->x86_model_id, p);
630 }
631
632 if (c->x86 == 15)
633 set_cpu_cap(c, X86_FEATURE_P4);
634 if (c->x86 == 6)
635 set_cpu_cap(c, X86_FEATURE_P3);
636 #endif
637
638 /* Work around errata */
639 srat_detect_node(c);
640
641 init_ia32_feat_ctl(c);
642
643 init_intel_misc_features(c);
644
645 split_lock_init();
646 bus_lock_init();
647
648 intel_init_thermal(c);
649 }
650
651 #ifdef CONFIG_X86_32
652 static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
653 {
654 /*
655 * Intel PIII Tualatin. This comes in two flavours.
656 * One has 256kb of cache, the other 512. We have no way
657 * to determine which, so we use a boottime override
658 * for the 512kb model, and assume 256 otherwise.
659 */
660 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
661 size = 256;
662
663 /*
664 * Intel Quark SoC X1000 contains a 4-way set associative
665 * 16K cache with a 16 byte cache line and 256 lines per tag
666 */
667 if ((c->x86 == 5) && (c->x86_model == 9))
668 size = 16;
669 return size;
670 }
671 #endif
672
673 #define TLB_INST_4K 0x01
674 #define TLB_INST_4M 0x02
675 #define TLB_INST_2M_4M 0x03
676
677 #define TLB_INST_ALL 0x05
678 #define TLB_INST_1G 0x06
679
680 #define TLB_DATA_4K 0x11
681 #define TLB_DATA_4M 0x12
682 #define TLB_DATA_2M_4M 0x13
683 #define TLB_DATA_4K_4M 0x14
684
685 #define TLB_DATA_1G 0x16
686
687 #define TLB_DATA0_4K 0x21
688 #define TLB_DATA0_4M 0x22
689 #define TLB_DATA0_2M_4M 0x23
690
691 #define STLB_4K 0x41
692 #define STLB_4K_2M 0x42
693
694 static const struct _tlb_table intel_tlb_table[] = {
695 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" },
696 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" },
697 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" },
698 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" },
699 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" },
700 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" },
701 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages" },
702 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
703 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
704 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
705 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
706 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" },
707 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" },
708 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" },
709 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
710 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" },
711 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" },
712 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" },
713 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" },
714 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" },
715 { 0x6b, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 8-way associative" },
716 { 0x6c, TLB_DATA_2M_4M, 128, " TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" },
717 { 0x6d, TLB_DATA_1G, 16, " TLB_DATA 1 GByte pages, fully associative" },
718 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
719 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" },
720 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
721 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" },
722 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" },
723 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" },
724 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" },
725 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" },
726 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" },
727 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
728 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },
729 { 0xc2, TLB_DATA_2M_4M, 16, " TLB_DATA 2 MByte/4MByte pages, 4-way associative" },
730 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" },
731 { 0x00, 0, 0 }
732 };
733
734 static void intel_tlb_lookup(const unsigned char desc)
735 {
736 unsigned char k;
737 if (desc == 0)
738 return;
739
740 /* look up this descriptor in the table */
741 for (k = 0; intel_tlb_table[k].descriptor != desc &&
742 intel_tlb_table[k].descriptor != 0; k++)
743 ;
744
745 if (intel_tlb_table[k].tlb_type == 0)
746 return;
747
748 switch (intel_tlb_table[k].tlb_type) {
749 case STLB_4K:
750 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
751 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
752 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
753 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
754 break;
755 case STLB_4K_2M:
756 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
757 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
758 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
759 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
760 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
761 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
762 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
763 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
764 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
765 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
766 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
767 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
768 break;
769 case TLB_INST_ALL:
770 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
771 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
772 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
773 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
774 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
775 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
776 break;
777 case TLB_INST_4K:
778 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
779 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
780 break;
781 case TLB_INST_4M:
782 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
783 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
784 break;
785 case TLB_INST_2M_4M:
786 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
787 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
788 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
789 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
790 break;
791 case TLB_DATA_4K:
792 case TLB_DATA0_4K:
793 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
794 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
795 break;
796 case TLB_DATA_4M:
797 case TLB_DATA0_4M:
798 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
799 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
800 break;
801 case TLB_DATA_2M_4M:
802 case TLB_DATA0_2M_4M:
803 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
804 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
805 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
806 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
807 break;
808 case TLB_DATA_4K_4M:
809 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
810 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
811 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
812 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
813 break;
814 case TLB_DATA_1G:
815 if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries)
816 tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries;
817 break;
818 }
819 }
820
821 static void intel_detect_tlb(struct cpuinfo_x86 *c)
822 {
823 int i, j, n;
824 unsigned int regs[4];
825 unsigned char *desc = (unsigned char *)regs;
826
827 if (c->cpuid_level < 2)
828 return;
829
830 /* Number of times to iterate */
831 n = cpuid_eax(2) & 0xFF;
832
833 for (i = 0 ; i < n ; i++) {
834 cpuid(2, &regs[0], &regs[1], &regs[2], &regs[3]);
835
836 /* If bit 31 is set, this is an unknown format */
837 for (j = 0 ; j < 3 ; j++)
838 if (regs[j] & (1 << 31))
839 regs[j] = 0;
840
841 /* Byte 0 is level count, not a descriptor */
842 for (j = 1 ; j < 16 ; j++)
843 intel_tlb_lookup(desc[j]);
844 }
845 }
846
847 static const struct cpu_dev intel_cpu_dev = {
848 .c_vendor = "Intel",
849 .c_ident = { "GenuineIntel" },
850 #ifdef CONFIG_X86_32
851 .legacy_models = {
852 { .family = 4, .model_names =
853 {
854 [0] = "486 DX-25/33",
855 [1] = "486 DX-50",
856 [2] = "486 SX",
857 [3] = "486 DX/2",
858 [4] = "486 SL",
859 [5] = "486 SX/2",
860 [7] = "486 DX/2-WB",
861 [8] = "486 DX/4",
862 [9] = "486 DX/4-WB"
863 }
864 },
865 { .family = 5, .model_names =
866 {
867 [0] = "Pentium 60/66 A-step",
868 [1] = "Pentium 60/66",
869 [2] = "Pentium 75 - 200",
870 [3] = "OverDrive PODP5V83",
871 [4] = "Pentium MMX",
872 [7] = "Mobile Pentium 75 - 200",
873 [8] = "Mobile Pentium MMX",
874 [9] = "Quark SoC X1000",
875 }
876 },
877 { .family = 6, .model_names =
878 {
879 [0] = "Pentium Pro A-step",
880 [1] = "Pentium Pro",
881 [3] = "Pentium II (Klamath)",
882 [4] = "Pentium II (Deschutes)",
883 [5] = "Pentium II (Deschutes)",
884 [6] = "Mobile Pentium II",
885 [7] = "Pentium III (Katmai)",
886 [8] = "Pentium III (Coppermine)",
887 [10] = "Pentium III (Cascades)",
888 [11] = "Pentium III (Tualatin)",
889 }
890 },
891 { .family = 15, .model_names =
892 {
893 [0] = "Pentium 4 (Unknown)",
894 [1] = "Pentium 4 (Willamette)",
895 [2] = "Pentium 4 (Northwood)",
896 [4] = "Pentium 4 (Foster)",
897 [5] = "Pentium 4 (Foster)",
898 }
899 },
900 },
901 .legacy_cache_size = intel_size_cache,
902 #endif
903 .c_detect_tlb = intel_detect_tlb,
904 .c_early_init = early_init_intel,
905 .c_bsp_init = bsp_init_intel,
906 .c_init = init_intel,
907 .c_x86_vendor = X86_VENDOR_INTEL,
908 };
909
910 cpu_dev_register(intel_cpu_dev);
911
912 #undef pr_fmt
913 #define pr_fmt(fmt) "x86/split lock detection: " fmt
914
915 static const struct {
916 const char *option;
917 enum split_lock_detect_state state;
918 } sld_options[] __initconst = {
919 { "off", sld_off },
920 { "warn", sld_warn },
921 { "fatal", sld_fatal },
922 { "ratelimit:", sld_ratelimit },
923 };
924
925 static struct ratelimit_state bld_ratelimit;
926
927 static unsigned int sysctl_sld_mitigate = 1;
928 static DEFINE_SEMAPHORE(buslock_sem, 1);
929
930 #ifdef CONFIG_PROC_SYSCTL
931 static struct ctl_table sld_sysctls[] = {
932 {
933 .procname = "split_lock_mitigate",
934 .data = &sysctl_sld_mitigate,
935 .maxlen = sizeof(unsigned int),
936 .mode = 0644,
937 .proc_handler = proc_douintvec_minmax,
938 .extra1 = SYSCTL_ZERO,
939 .extra2 = SYSCTL_ONE,
940 },
941 };
942
943 static int __init sld_mitigate_sysctl_init(void)
944 {
945 register_sysctl_init("kernel", sld_sysctls);
946 return 0;
947 }
948
949 late_initcall(sld_mitigate_sysctl_init);
950 #endif
951
952 static inline bool match_option(const char *arg, int arglen, const char *opt)
953 {
954 int len = strlen(opt), ratelimit;
955
956 if (strncmp(arg, opt, len))
957 return false;
958
959 /*
960 * Min ratelimit is 1 bus lock/sec.
961 * Max ratelimit is 1000 bus locks/sec.
962 */
963 if (sscanf(arg, "ratelimit:%d", &ratelimit) == 1 &&
964 ratelimit > 0 && ratelimit <= 1000) {
965 ratelimit_state_init(&bld_ratelimit, HZ, ratelimit);
966 ratelimit_set_flags(&bld_ratelimit, RATELIMIT_MSG_ON_RELEASE);
967 return true;
968 }
969
970 return len == arglen;
971 }
972
973 static bool split_lock_verify_msr(bool on)
974 {
975 u64 ctrl, tmp;
976
977 if (rdmsrl_safe(MSR_TEST_CTRL, &ctrl))
978 return false;
979 if (on)
980 ctrl |= MSR_TEST_CTRL_SPLIT_LOCK_DETECT;
981 else
982 ctrl &= ~MSR_TEST_CTRL_SPLIT_LOCK_DETECT;
983 if (wrmsrl_safe(MSR_TEST_CTRL, ctrl))
984 return false;
985 rdmsrl(MSR_TEST_CTRL, tmp);
986 return ctrl == tmp;
987 }
988
989 static void __init sld_state_setup(void)
990 {
991 enum split_lock_detect_state state = sld_warn;
992 char arg[20];
993 int i, ret;
994
995 if (!boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT) &&
996 !boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT))
997 return;
998
999 ret = cmdline_find_option(boot_command_line, "split_lock_detect",
1000 arg, sizeof(arg));
1001 if (ret >= 0) {
1002 for (i = 0; i < ARRAY_SIZE(sld_options); i++) {
1003 if (match_option(arg, ret, sld_options[i].option)) {
1004 state = sld_options[i].state;
1005 break;
1006 }
1007 }
1008 }
1009 sld_state = state;
1010 }
1011
1012 static void __init __split_lock_setup(void)
1013 {
1014 if (!split_lock_verify_msr(false)) {
1015 pr_info("MSR access failed: Disabled\n");
1016 return;
1017 }
1018
1019 rdmsrl(MSR_TEST_CTRL, msr_test_ctrl_cache);
1020
1021 if (!split_lock_verify_msr(true)) {
1022 pr_info("MSR access failed: Disabled\n");
1023 return;
1024 }
1025
1026 /* Restore the MSR to its cached value. */
1027 wrmsrl(MSR_TEST_CTRL, msr_test_ctrl_cache);
1028
1029 setup_force_cpu_cap(X86_FEATURE_SPLIT_LOCK_DETECT);
1030 }
1031
1032 /*
1033 * MSR_TEST_CTRL is per core, but we treat it like a per CPU MSR. Locking
1034 * is not implemented as one thread could undo the setting of the other
1035 * thread immediately after dropping the lock anyway.
1036 */
1037 static void sld_update_msr(bool on)
1038 {
1039 u64 test_ctrl_val = msr_test_ctrl_cache;
1040
1041 if (on)
1042 test_ctrl_val |= MSR_TEST_CTRL_SPLIT_LOCK_DETECT;
1043
1044 wrmsrl(MSR_TEST_CTRL, test_ctrl_val);
1045 }
1046
1047 static void split_lock_init(void)
1048 {
1049 /*
1050 * #DB for bus lock handles ratelimit and #AC for split lock is
1051 * disabled.
1052 */
1053 if (sld_state == sld_ratelimit) {
1054 split_lock_verify_msr(false);
1055 return;
1056 }
1057
1058 if (cpu_model_supports_sld)
1059 split_lock_verify_msr(sld_state != sld_off);
1060 }
1061
1062 static void __split_lock_reenable_unlock(struct work_struct *work)
1063 {
1064 sld_update_msr(true);
1065 up(&buslock_sem);
1066 }
1067
1068 static DECLARE_DELAYED_WORK(sl_reenable_unlock, __split_lock_reenable_unlock);
1069
1070 static void __split_lock_reenable(struct work_struct *work)
1071 {
1072 sld_update_msr(true);
1073 }
1074 static DECLARE_DELAYED_WORK(sl_reenable, __split_lock_reenable);
1075
1076 /*
1077 * If a CPU goes offline with pending delayed work to re-enable split lock
1078 * detection then the delayed work will be executed on some other CPU. That
1079 * handles releasing the buslock_sem, but because it executes on a
1080 * different CPU probably won't re-enable split lock detection. This is a
1081 * problem on HT systems since the sibling CPU on the same core may then be
1082 * left running with split lock detection disabled.
1083 *
1084 * Unconditionally re-enable detection here.
1085 */
1086 static int splitlock_cpu_offline(unsigned int cpu)
1087 {
1088 sld_update_msr(true);
1089
1090 return 0;
1091 }
1092
1093 static void split_lock_warn(unsigned long ip)
1094 {
1095 struct delayed_work *work;
1096 int cpu;
1097
1098 if (!current->reported_split_lock)
1099 pr_warn_ratelimited("#AC: %s/%d took a split_lock trap at address: 0x%lx\n",
1100 current->comm, current->pid, ip);
1101 current->reported_split_lock = 1;
1102
1103 if (sysctl_sld_mitigate) {
1104 /*
1105 * misery factor #1:
1106 * sleep 10ms before trying to execute split lock.
1107 */
1108 if (msleep_interruptible(10) > 0)
1109 return;
1110 /*
1111 * Misery factor #2:
1112 * only allow one buslocked disabled core at a time.
1113 */
1114 if (down_interruptible(&buslock_sem) == -EINTR)
1115 return;
1116 work = &sl_reenable_unlock;
1117 } else {
1118 work = &sl_reenable;
1119 }
1120
1121 cpu = get_cpu();
1122 schedule_delayed_work_on(cpu, work, 2);
1123
1124 /* Disable split lock detection on this CPU to make progress */
1125 sld_update_msr(false);
1126 put_cpu();
1127 }
1128
1129 bool handle_guest_split_lock(unsigned long ip)
1130 {
1131 if (sld_state == sld_warn) {
1132 split_lock_warn(ip);
1133 return true;
1134 }
1135
1136 pr_warn_once("#AC: %s/%d %s split_lock trap at address: 0x%lx\n",
1137 current->comm, current->pid,
1138 sld_state == sld_fatal ? "fatal" : "bogus", ip);
1139
1140 current->thread.error_code = 0;
1141 current->thread.trap_nr = X86_TRAP_AC;
1142 force_sig_fault(SIGBUS, BUS_ADRALN, NULL);
1143 return false;
1144 }
1145 EXPORT_SYMBOL_GPL(handle_guest_split_lock);
1146
1147 static void bus_lock_init(void)
1148 {
1149 u64 val;
1150
1151 if (!boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT))
1152 return;
1153
1154 rdmsrl(MSR_IA32_DEBUGCTLMSR, val);
1155
1156 if ((boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT) &&
1157 (sld_state == sld_warn || sld_state == sld_fatal)) ||
1158 sld_state == sld_off) {
1159 /*
1160 * Warn and fatal are handled by #AC for split lock if #AC for
1161 * split lock is supported.
1162 */
1163 val &= ~DEBUGCTLMSR_BUS_LOCK_DETECT;
1164 } else {
1165 val |= DEBUGCTLMSR_BUS_LOCK_DETECT;
1166 }
1167
1168 wrmsrl(MSR_IA32_DEBUGCTLMSR, val);
1169 }
1170
1171 bool handle_user_split_lock(struct pt_regs *regs, long error_code)
1172 {
1173 if ((regs->flags & X86_EFLAGS_AC) || sld_state == sld_fatal)
1174 return false;
1175 split_lock_warn(regs->ip);
1176 return true;
1177 }
1178
1179 void handle_bus_lock(struct pt_regs *regs)
1180 {
1181 switch (sld_state) {
1182 case sld_off:
1183 break;
1184 case sld_ratelimit:
1185 /* Enforce no more than bld_ratelimit bus locks/sec. */
1186 while (!__ratelimit(&bld_ratelimit))
1187 msleep(20);
1188 /* Warn on the bus lock. */
1189 fallthrough;
1190 case sld_warn:
1191 pr_warn_ratelimited("#DB: %s/%d took a bus_lock trap at address: 0x%lx\n",
1192 current->comm, current->pid, regs->ip);
1193 break;
1194 case sld_fatal:
1195 force_sig_fault(SIGBUS, BUS_ADRALN, NULL);
1196 break;
1197 }
1198 }
1199
1200 /*
1201 * CPU models that are known to have the per-core split-lock detection
1202 * feature even though they do not enumerate IA32_CORE_CAPABILITIES.
1203 */
1204 static const struct x86_cpu_id split_lock_cpu_ids[] __initconst = {
1205 X86_MATCH_VFM(INTEL_ICELAKE_X, 0),
1206 X86_MATCH_VFM(INTEL_ICELAKE_L, 0),
1207 X86_MATCH_VFM(INTEL_ICELAKE_D, 0),
1208 {}
1209 };
1210
1211 static void __init split_lock_setup(struct cpuinfo_x86 *c)
1212 {
1213 const struct x86_cpu_id *m;
1214 u64 ia32_core_caps;
1215
1216 if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
1217 return;
1218
1219 /* Check for CPUs that have support but do not enumerate it: */
1220 m = x86_match_cpu(split_lock_cpu_ids);
1221 if (m)
1222 goto supported;
1223
1224 if (!cpu_has(c, X86_FEATURE_CORE_CAPABILITIES))
1225 return;
1226
1227 /*
1228 * Not all bits in MSR_IA32_CORE_CAPS are architectural, but
1229 * MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT is. All CPUs that set
1230 * it have split lock detection.
1231 */
1232 rdmsrl(MSR_IA32_CORE_CAPS, ia32_core_caps);
1233 if (ia32_core_caps & MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT)
1234 goto supported;
1235
1236 /* CPU is not in the model list and does not have the MSR bit: */
1237 return;
1238
1239 supported:
1240 cpu_model_supports_sld = true;
1241 __split_lock_setup();
1242 }
1243
1244 static void sld_state_show(void)
1245 {
1246 if (!boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT) &&
1247 !boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
1248 return;
1249
1250 switch (sld_state) {
1251 case sld_off:
1252 pr_info("disabled\n");
1253 break;
1254 case sld_warn:
1255 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) {
1256 pr_info("#AC: crashing the kernel on kernel split_locks and warning on user-space split_locks\n");
1257 if (cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
1258 "x86/splitlock", NULL, splitlock_cpu_offline) < 0)
1259 pr_warn("No splitlock CPU offline handler\n");
1260 } else if (boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT)) {
1261 pr_info("#DB: warning on user-space bus_locks\n");
1262 }
1263 break;
1264 case sld_fatal:
1265 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) {
1266 pr_info("#AC: crashing the kernel on kernel split_locks and sending SIGBUS on user-space split_locks\n");
1267 } else if (boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT)) {
1268 pr_info("#DB: sending SIGBUS on user-space bus_locks%s\n",
1269 boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT) ?
1270 " from non-WB" : "");
1271 }
1272 break;
1273 case sld_ratelimit:
1274 if (boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT))
1275 pr_info("#DB: setting system wide bus lock rate limit to %u/sec\n", bld_ratelimit.burst);
1276 break;
1277 }
1278 }
1279
1280 void __init sld_setup(struct cpuinfo_x86 *c)
1281 {
1282 split_lock_setup(c);
1283 sld_state_setup();
1284 sld_state_show();
1285 }
1286
1287 #define X86_HYBRID_CPU_TYPE_ID_SHIFT 24
1288
1289 /**
1290 * get_this_hybrid_cpu_type() - Get the type of this hybrid CPU
1291 *
1292 * Returns the CPU type [31:24] (i.e., Atom or Core) of a CPU in
1293 * a hybrid processor. If the processor is not hybrid, returns 0.
1294 */
1295 u8 get_this_hybrid_cpu_type(void)
1296 {
1297 if (!cpu_feature_enabled(X86_FEATURE_HYBRID_CPU))
1298 return 0;
1299
1300 return cpuid_eax(0x0000001a) >> X86_HYBRID_CPU_TYPE_ID_SHIFT;
1301 }
Kernel DRM miscellaneous fixes and cross-tree changes