include/fx2regs.h

   1 // Copyright (C) 2008 Ubixum, Inc.
   2 //
   3 // This library is free software; you can redistribute it and/or
   4 // modify it under the terms of the GNU Lesser General Public
   5 // License as published by the Free Software Foundation; either
   6 // version 2.1 of the License, or (at your option) any later version.
   7 //
   8 // This library is distributed in the hope that it will be useful,
   9 // but WITHOUT ANY WARRANTY; without even the implied warranty of
  10 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11 // Lesser General Public License for more details.
  12 //
  13 // You should have received a copy of the GNU Lesser General Public
  14 // License along with this library; if not, write to the Free Software
  15 // Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
  16
  17 /*! \file
  18  *
  19  * This is the basic header/register file for working with the cypress fx2
  20  * (cyc768013) and variants 8051 chipset.  It contains the special function
  21  * register definitions as well as the special configuration registers
  22  * addresses.
  23  *
  24  * The TRM for the fx2 chip contains the full documentation for what each of
  25  * these registers do.
  26  *
  27  * */
  28
  29
  30 /** \mainpage FX2LIB Documentation
  31  *  \verbinclude README
  32  **/
  33
  34 #ifndef FX2REGS_H
  35 #define FX2REGS_H
  36
  37 #include "fx2types.h"
  38
  39 xdata at 0xE400 volatile BYTE GPIF_WAVE_DATA;
  40 xdata at 0xE480 volatile BYTE RES_WAVEDATA_END;
  41
  42 // General Configuration
  43
  44 xdata at 0xE600 volatile BYTE CPUCS;  //! Control & Status
  45 xdata at 0xE601 volatile BYTE IFCONFIG;  //! Interface Configuration
  46 xdata at 0xE602 volatile BYTE PINFLAGSAB;  //! FIFO FLAGA and FLAGB Assignments
  47 xdata at 0xE603 volatile BYTE PINFLAGSCD;  //! FIFO FLAGC and FLAGD Assignments
  48 xdata at 0xE604 volatile BYTE FIFORESET;  //! Restore FIFOS to default state
  49 xdata at 0xE605 volatile BYTE BREAKPT;  //! Breakpoint
  50 xdata at 0xE606 volatile BYTE BPADDRH;  //! Breakpoint Address H
  51 xdata at 0xE607 volatile BYTE BPADDRL;  //! Breakpoint Address L
  52 xdata at 0xE608 volatile BYTE UART230;  //! 230 Kbaud clock for T0,T1,T2
  53 xdata at 0xE609 volatile BYTE FIFOPINPOLAR;  //! FIFO polarities
  54 xdata at 0xE60A volatile BYTE REVID;  //! Chip Revision
  55 xdata at 0xE60B volatile BYTE REVCTL;  //! Chip Revision Control
  56
  57 // Endpoint Configuration
  58
  59 xdata at 0xE610 volatile BYTE EP1OUTCFG;  //! Endpoint 1-OUT Configuration
  60 xdata at 0xE611 volatile BYTE EP1INCFG;  //! Endpoint 1-IN Configuration
  61 xdata at 0xE612 volatile BYTE EP2CFG;  //! Endpoint 2 Configuration
  62 xdata at 0xE613 volatile BYTE EP4CFG;  //! Endpoint 4 Configuration
  63 xdata at 0xE614 volatile BYTE EP6CFG;  //! Endpoint 6 Configuration
  64 xdata at 0xE615 volatile BYTE EP8CFG;  //! Endpoint 8 Configuration
  65 xdata at 0xE618 volatile BYTE EP2FIFOCFG;  //! Endpoint 2 FIFO configuration
  66 xdata at 0xE619 volatile BYTE EP4FIFOCFG;  //! Endpoint 4 FIFO configuration
  67 xdata at 0xE61A volatile BYTE EP6FIFOCFG;  //! Endpoint 6 FIFO configuration
  68 xdata at 0xE61B volatile BYTE EP8FIFOCFG;  //! Endpoint 8 FIFO configuration
  69 xdata at 0xE620 volatile BYTE EP2AUTOINLENH;  //! Endpoint 2 Packet Length H (IN only)
  70 xdata at 0xE621 volatile BYTE EP2AUTOINLENL;  //! Endpoint 2 Packet Length L (IN only)
  71 xdata at 0xE622 volatile BYTE EP4AUTOINLENH;  //! Endpoint 4 Packet Length H (IN only)
  72 xdata at 0xE623 volatile BYTE EP4AUTOINLENL;  //! Endpoint 4 Packet Length L (IN only)
  73 xdata at 0xE624 volatile BYTE EP6AUTOINLENH;  //! Endpoint 6 Packet Length H (IN only)
  74 xdata at 0xE625 volatile BYTE EP6AUTOINLENL;  //! Endpoint 6 Packet Length L (IN only)
  75 xdata at 0xE626 volatile BYTE EP8AUTOINLENH;  //! Endpoint 8 Packet Length H (IN only)
  76 xdata at 0xE627 volatile BYTE EP8AUTOINLENL;  //! Endpoint 8 Packet Length L (IN only)
  77 xdata at 0xE630 volatile BYTE EP2FIFOPFH;  //! EP2 Programmable Flag trigger H
  78 xdata at 0xE631 volatile BYTE EP2FIFOPFL;  //! EP2 Programmable Flag trigger L
  79 xdata at 0xE632 volatile BYTE EP4FIFOPFH;  //! EP4 Programmable Flag trigger H
  80 xdata at 0xE633 volatile BYTE EP4FIFOPFL;  //! EP4 Programmable Flag trigger L
  81 xdata at 0xE634 volatile BYTE EP6FIFOPFH;  //! EP6 Programmable Flag trigger H
  82 xdata at 0xE635 volatile BYTE EP6FIFOPFL;  //! EP6 Programmable Flag trigger L
  83 xdata at 0xE636 volatile BYTE EP8FIFOPFH;  //! EP8 Programmable Flag trigger H
  84 xdata at 0xE637 volatile BYTE EP8FIFOPFL;  //! EP8 Programmable Flag trigger L
  85 xdata at 0xE640 volatile BYTE EP2ISOINPKTS;  //! EP2 (if ISO) IN Packets per frame (1-3)
  86 xdata at 0xE641 volatile BYTE EP4ISOINPKTS;  //! EP4 (if ISO) IN Packets per frame (1-3)
  87 xdata at 0xE642 volatile BYTE EP6ISOINPKTS;  //! EP6 (if ISO) IN Packets per frame (1-3)
  88 xdata at 0xE643 volatile BYTE EP8ISOINPKTS;  //! EP8 (if ISO) IN Packets per frame (1-3)
  89 xdata at 0xE648 volatile BYTE INPKTEND;  //! Force IN Packet End
  90 xdata at 0xE649 volatile BYTE OUTPKTEND;  //! Force OUT Packet End
  91
  92 // Interrupts
  93
  94 xdata at 0xE650 volatile BYTE EP2FIFOIE;  //! Endpoint 2 Flag Interrupt Enable
  95 xdata at 0xE651 volatile BYTE EP2FIFOIRQ;  //! Endpoint 2 Flag Interrupt Request
  96 xdata at 0xE652 volatile BYTE EP4FIFOIE;  //! Endpoint 4 Flag Interrupt Enable
  97 xdata at 0xE653 volatile BYTE EP4FIFOIRQ;  //! Endpoint 4 Flag Interrupt Request
  98 xdata at 0xE654 volatile BYTE EP6FIFOIE;  //! Endpoint 6 Flag Interrupt Enable
  99 xdata at 0xE655 volatile BYTE EP6FIFOIRQ;  //! Endpoint 6 Flag Interrupt Request
 100 xdata at 0xE656 volatile BYTE EP8FIFOIE;  //! Endpoint 8 Flag Interrupt Enable
 101 xdata at 0xE657 volatile BYTE EP8FIFOIRQ;  //! Endpoint 8 Flag Interrupt Request
 102 xdata at 0xE658 volatile BYTE IBNIE;  //! IN-BULK-NAK Interrupt Enable
 103 xdata at 0xE659 volatile BYTE IBNIRQ;  //! IN-BULK-NAK interrupt Request
 104 xdata at 0xE65A volatile BYTE NAKIE;  //! Endpoint Ping NAK interrupt Enable
 105 xdata at 0xE65B volatile BYTE NAKIRQ;  //! Endpoint Ping NAK interrupt Request
 106 xdata at 0xE65C volatile BYTE USBIE;  //! USB Int Enables
 107 xdata at 0xE65D volatile BYTE USBIRQ;  //! USB Interrupt Requests
 108 xdata at 0xE65E volatile BYTE EPIE;  //! Endpoint Interrupt Enables
 109 xdata at 0xE65F volatile BYTE EPIRQ;  //! Endpoint Interrupt Requests
 110 xdata at 0xE660 volatile BYTE GPIFIE;  //! GPIF Interrupt Enable
 111 xdata at 0xE661 volatile BYTE GPIFIRQ;  //! GPIF Interrupt Request
 112 xdata at 0xE662 volatile BYTE USBERRIE;  //! USB Error Interrupt Enables
 113 xdata at 0xE663 volatile BYTE USBERRIRQ;  //! USB Error Interrupt Requests
 114 xdata at 0xE664 volatile BYTE ERRCNTLIM;  //! USB Error counter and limit
 115 xdata at 0xE665 volatile BYTE CLRERRCNT;  //! Clear Error Counter EC[3..0]
 116 xdata at 0xE666 volatile BYTE INT2IVEC;  //! Interupt 2 (USB) Autovector
 117 xdata at 0xE667 volatile BYTE INT4IVEC;  //! Interupt 4 (FIFOS & GPIF) Autovector
 118 xdata at 0xE668 volatile BYTE INTSETUP;  //! Interrupt 2&4 Setup
 119
 120 // Input/Output
 121
 122 xdata at 0xE670 volatile BYTE PORTACFG;  //! I/O PORTA Alternate Configuration
 123 xdata at 0xE671 volatile BYTE PORTCCFG;  //! I/O PORTC Alternate Configuration
 124 xdata at 0xE672 volatile BYTE PORTECFG;  //! I/O PORTE Alternate Configuration
 125 xdata at 0xE678 volatile BYTE I2CS;  //! Control & Status
 126 xdata at 0xE679 volatile BYTE I2DAT;  //! Data
 127 xdata at 0xE67A volatile BYTE I2CTL;  //! I2C Control
 128 xdata at 0xE67B volatile BYTE XAUTODAT1;  //! Autoptr1 MOVX access
 129 xdata at 0xE67C volatile BYTE XAUTODAT2;  //! Autoptr2 MOVX access
 130
 131 #define EXTAUTODAT1 XAUTODAT1
 132 #define EXTAUTODAT2 XAUTODAT2
 133
 134 // USB Control
 135
 136 xdata at 0xE680 volatile BYTE USBCS;  //! USB Control & Status
 137 xdata at 0xE681 volatile BYTE SUSPEND;  //! Put chip into suspend
 138 xdata at 0xE682 volatile BYTE WAKEUPCS;  //! Wakeup source and polarity
 139 xdata at 0xE683 volatile BYTE TOGCTL;  //! Toggle Control
 140 xdata at 0xE684 volatile BYTE USBFRAMEH;  //! USB Frame count H
 141 xdata at 0xE685 volatile BYTE USBFRAMEL;  //! USB Frame count L
 142 xdata at 0xE686 volatile BYTE MICROFRAME;  //! Microframe count, 0-7
 143 xdata at 0xE687 volatile BYTE FNADDR;  //! USB Function address
 144
 145 // Endpoints
 146
 147 xdata at 0xE68A volatile BYTE EP0BCH;  //! Endpoint 0 Byte Count H
 148 xdata at 0xE68B volatile BYTE EP0BCL;  //! Endpoint 0 Byte Count L
 149 xdata at 0xE68D volatile BYTE EP1OUTBC;  //! Endpoint 1 OUT Byte Count
 150 xdata at 0xE68F volatile BYTE EP1INBC;  //! Endpoint 1 IN Byte Count
 151 xdata at 0xE690 volatile BYTE EP2BCH;  //! Endpoint 2 Byte Count H
 152 xdata at 0xE691 volatile BYTE EP2BCL;  //! Endpoint 2 Byte Count L
 153 xdata at 0xE694 volatile BYTE EP4BCH;  //! Endpoint 4 Byte Count H
 154 xdata at 0xE695 volatile BYTE EP4BCL;  //! Endpoint 4 Byte Count L
 155 xdata at 0xE698 volatile BYTE EP6BCH;  //! Endpoint 6 Byte Count H
 156 xdata at 0xE699 volatile BYTE EP6BCL;  //! Endpoint 6 Byte Count L
 157 xdata at 0xE69C volatile BYTE EP8BCH;  //! Endpoint 8 Byte Count H
 158 xdata at 0xE69D volatile BYTE EP8BCL;  //! Endpoint 8 Byte Count L
 159 xdata at 0xE6A0 volatile BYTE EP0CS;  //! Endpoint  Control and Status
 160 xdata at 0xE6A1 volatile BYTE EP1OUTCS;  //! Endpoint 1 OUT Control and Status
 161 xdata at 0xE6A2 volatile BYTE EP1INCS;  //! Endpoint 1 IN Control and Status
 162 xdata at 0xE6A3 volatile BYTE EP2CS;  //! Endpoint 2 Control and Status
 163 xdata at 0xE6A4 volatile BYTE EP4CS;  //! Endpoint 4 Control and Status
 164 xdata at 0xE6A5 volatile BYTE EP6CS;  //! Endpoint 6 Control and Status
 165 xdata at 0xE6A6 volatile BYTE EP8CS;  //! Endpoint 8 Control and Status
 166 xdata at 0xE6A7 volatile BYTE EP2FIFOFLGS;  //! Endpoint 2 Flags
 167 xdata at 0xE6A8 volatile BYTE EP4FIFOFLGS;  //! Endpoint 4 Flags
 168 xdata at 0xE6A9 volatile BYTE EP6FIFOFLGS;  //! Endpoint 6 Flags
 169 xdata at 0xE6AA volatile BYTE EP8FIFOFLGS;  //! Endpoint 8 Flags
 170 xdata at 0xE6AB volatile BYTE EP2FIFOBCH;  //! EP2 FIFO total byte count H
 171 xdata at 0xE6AC volatile BYTE EP2FIFOBCL;  //! EP2 FIFO total byte count L
 172 xdata at 0xE6AD volatile BYTE EP4FIFOBCH;  //! EP4 FIFO total byte count H
 173 xdata at 0xE6AE volatile BYTE EP4FIFOBCL;  //! EP4 FIFO total byte count L
 174 xdata at 0xE6AF volatile BYTE EP6FIFOBCH;  //! EP6 FIFO total byte count H
 175 xdata at 0xE6B0 volatile BYTE EP6FIFOBCL;  //! EP6 FIFO total byte count L
 176 xdata at 0xE6B1 volatile BYTE EP8FIFOBCH;  //! EP8 FIFO total byte count H
 177 xdata at 0xE6B2 volatile BYTE EP8FIFOBCL;  //! EP8 FIFO total byte count L
 178 xdata at 0xE6B3 volatile BYTE SUDPTRH;  //! Setup Data Pointer high address byte
 179 xdata at 0xE6B4 volatile BYTE SUDPTRL;  //! Setup Data Pointer low address byte
 180 xdata at 0xE6B5 volatile BYTE SUDPTRCTL;  //! Setup Data Pointer Auto Mode
 181 xdata at 0xE6B8 volatile BYTE SETUPDAT[8];  //! 8 bytes of SETUP data
 182
 183 // GPIF
 184
 185 xdata at 0xE6C0 volatile BYTE GPIFWFSELECT;  //! Waveform Selector
 186 xdata at 0xE6C1 volatile BYTE GPIFIDLECS;  //! GPIF Done, GPIF IDLE drive mode
 187 xdata at 0xE6C2 volatile BYTE GPIFIDLECTL;  //! Inactive Bus, CTL states
 188 xdata at 0xE6C3 volatile BYTE GPIFCTLCFG;  //! CTL OUT pin drive
 189 xdata at 0xE6C4 volatile BYTE GPIFADRH;  //! GPIF Address H
 190 xdata at 0xE6C5 volatile BYTE GPIFADRL;  //! GPIF Address L
 191
 192 xdata at 0xE6CE volatile BYTE GPIFTCB3;  //! GPIF Transaction Count Byte 3
 193 xdata at 0xE6CF volatile BYTE GPIFTCB2;  //! GPIF Transaction Count Byte 2
 194 xdata at 0xE6D0 volatile BYTE GPIFTCB1;  //! GPIF Transaction Count Byte 1
 195 xdata at 0xE6D1 volatile BYTE GPIFTCB0;  //! GPIF Transaction Count Byte 0
 196
 197 xdata at 0xE6D2 volatile BYTE EP2GPIFFLGSEL;  //! EP2 GPIF Flag select
 198 xdata at 0xE6D3 volatile BYTE EP2GPIFPFSTOP;  //! Stop GPIF EP2 transaction on prog. flag
 199 xdata at 0xE6D4 volatile BYTE EP2GPIFTRIG;  //! EP2 FIFO Trigger
 200 xdata at 0xE6DA volatile BYTE EP4GPIFFLGSEL;  //! EP4 GPIF Flag select
 201 xdata at 0xE6DB volatile BYTE EP4GPIFPFSTOP;  //! Stop GPIF EP4 transaction on prog. flag
 202 xdata at 0xE6DC volatile BYTE EP4GPIFTRIG;  //! EP4 FIFO Trigger
 203 xdata at 0xE6E2 volatile BYTE EP6GPIFFLGSEL;  //! EP6 GPIF Flag select
 204 xdata at 0xE6E3 volatile BYTE EP6GPIFPFSTOP;  //! Stop GPIF EP6 transaction on prog. flag
 205 xdata at 0xE6E4 volatile BYTE EP6GPIFTRIG;  //! EP6 FIFO Trigger
 206 xdata at 0xE6EA volatile BYTE EP8GPIFFLGSEL;  //! EP8 GPIF Flag select
 207 xdata at 0xE6EB volatile BYTE EP8GPIFPFSTOP;  //! Stop GPIF EP8 transaction on prog. flag
 208 xdata at 0xE6EC volatile BYTE EP8GPIFTRIG;  //! EP8 FIFO Trigger
 209 xdata at 0xE6F0 volatile BYTE XGPIFSGLDATH;  //! GPIF Data H (16-bit mode only)
 210 xdata at 0xE6F1 volatile BYTE XGPIFSGLDATLX;  //! Read/Write GPIF Data L & trigger transac
 211 xdata at 0xE6F2 volatile BYTE XGPIFSGLDATLNOX;  //! Read GPIF Data L, no transac trigger
 212 xdata at 0xE6F3 volatile BYTE GPIFREADYCFG;  //! Internal RDY,Sync/Async, RDY5CFG
 213 xdata at 0xE6F4 volatile BYTE GPIFREADYSTAT;  //! RDY pin states
 214 xdata at 0xE6F5 volatile BYTE GPIFABORT;  //! Abort GPIF cycles
 215
 216 // UDMA
 217
 218 xdata at 0xE6C6 volatile BYTE FLOWSTATE; //!Defines GPIF flow state
 219 xdata at 0xE6C7 volatile BYTE FLOWLOGIC; //!Defines flow/hold decision criteria
 220 xdata at 0xE6C8 volatile BYTE FLOWEQ0CTL; //!CTL states during active flow state
 221 xdata at 0xE6C9 volatile BYTE FLOWEQ1CTL; //!CTL states during hold flow state
 222 xdata at 0xE6CA volatile BYTE FLOWHOLDOFF;
 223 xdata at 0xE6CB volatile BYTE FLOWSTB; //!CTL/RDY Signal to use as master data strobe
 224 xdata at 0xE6CC volatile BYTE FLOWSTBEDGE; //!Defines active master strobe edge
 225 xdata at 0xE6CD volatile BYTE FLOWSTBHPERIOD; //!Half Period of output master strobe
 226 xdata at 0xE60C volatile BYTE GPIFHOLDAMOUNT; //!Data delay shift
 227 xdata at 0xE67D volatile BYTE UDMACRCH; //!CRC Upper byte
 228 xdata at 0xE67E volatile BYTE UDMACRCL; //!CRC Lower byte
 229 xdata at 0xE67F volatile BYTE UDMACRCQUAL; //!UDMA In only, host terminated use only
 230
 231 // Endpoint Buffers
 232
 233 xdata at 0xE740 volatile BYTE EP0BUF[64];  //! EP0 IN-OUT buffer
 234 xdata at 0xE780 volatile BYTE EP1OUTBUF[64];  //! EP1-OUT buffer
 235 xdata at 0xE7C0 volatile BYTE EP1INBUF[64];  //! EP1-IN buffer
 236 xdata at 0xF000 volatile BYTE EP2FIFOBUF[1024];  //! 512/1024-byte EP2 buffer (IN or OUT)
 237 xdata at 0xF400 volatile BYTE EP4FIFOBUF[1024];  //! 512 byte EP4 buffer (IN or OUT)
 238 xdata at 0xF800 volatile BYTE EP6FIFOBUF[1024];  //! 512/1024-byte EP6 buffer (IN or OUT)
 239 xdata at 0xFC00 volatile BYTE EP8FIFOBUF[1024];  //! 512 byte EP8 buffer (IN or OUT)
 240
 241 // Error Correction Code (ECC) Registers (FX2LP/FX1 only)
 242
 243 xdata at 0xE628 volatile BYTE ECCCFG;  //! ECC Configuration
 244 xdata at 0xE629 volatile BYTE ECCRESET;  //! ECC Reset
 245 xdata at 0xE62A volatile BYTE ECC1B0;  //! ECC1 Byte 0
 246 xdata at 0xE62B volatile BYTE ECC1B1;  //! ECC1 Byte 1
 247 xdata at 0xE62C volatile BYTE ECC1B2;  //! ECC1 Byte 2
 248 xdata at 0xE62D volatile BYTE ECC2B0;  //! ECC2 Byte 0
 249 xdata at 0xE62E volatile BYTE ECC2B1;  //! ECC2 Byte 1
 250 xdata at 0xE62F volatile BYTE ECC2B2;  //! ECC2 Byte 2
 251
 252 // Feature Registers  (FX2LP/FX1 only)
 253 xdata at 0xE50D volatile BYTE GPCR2;  //! Chip Features
 254
 255 /**
 256  * SFRs below
 257  *  According to TRM 15.2, only rows 0 and 8 of the SFRs are bit addressible
 258  *  row 0: IOA, IOB, IOC, IOD, SCON1, PSW, ACC, B
 259  *  row 8: TCON, SCON0, IE, IP, T2CON, IECON, EIE, EIP
 260  *
 261  *  All others have to move a byte to the SRF address
 262  **/
 263
 264 sfr at 0x80 IOA;
 265          /*  IOA  */
 266          sbit at 0x80 + 0 PA0;
 267          sbit at 0x80 + 1 PA1;
 268          sbit at 0x80 + 2 PA2;
 269          sbit at 0x80 + 3 PA3;
 270          sbit at 0x80 + 4 PA4;
 271          sbit at 0x80 + 5 PA5;
 272          sbit at 0x80 + 6 PA6;
 273          sbit at 0x80 + 7 PA7;
 274 sfr at 0x81 SP;
 275 sfr at 0x82 DPL;
 276 sfr at 0x83 DPH;
 277 sfr at 0x84 DPL1;
 278 sfr at 0x85 DPH1;
 279 sfr at 0x86 DPS;
 280 sfr at 0x87 PCON;
 281 sfr at 0x88 TCON;
 282          /*  TCON  */
 283          sbit at 0x88+0 IT0;
 284          sbit at 0x88+1 IE0;
 285          sbit at 0x88+2 IT1;
 286          sbit at 0x88+3 IE1;
 287          sbit at 0x88+4 TR0;
 288          sbit at 0x88+5 TF0;
 289          sbit at 0x88+6 TR1;
 290          sbit at 0x88+7 TF1;
 291 sfr at 0x89 TMOD;
 292 sfr at 0x8A TL0;
 293 sfr at 0x8B TL1;
 294 sfr at 0x8C TH0;
 295 sfr at 0x8D TH1;
 296 sfr at 0x8E CKCON;
 297 sfr at 0x90 IOB;
 298          /*  IOB  */
 299          sbit at 0x90 + 0 PB0;
 300          sbit at 0x90 + 1 PB1;
 301          sbit at 0x90 + 2 PB2;
 302          sbit at 0x90 + 3 PB3;
 303          sbit at 0x90 + 4 PB4;
 304          sbit at 0x90 + 5 PB5;
 305          sbit at 0x90 + 6 PB6;
 306          sbit at 0x90 + 7 PB7;
 307 sfr at 0x91 EXIF;
 308
 309 //sfr at 0x92 MPAGE;
 310 sfr at 0x92 _XPAGE; // same as MPAGE for pdata sfr access w/ sdcc
 311 sfr at 0x98 SCON0;
 312          /*  SCON0  */
 313          sbit at 0x98+0 RI;
 314          sbit at 0x98+1 TI;
 315          sbit at 0x98+2 RB8;
 316          sbit at 0x98+3 TB8;
 317          sbit at 0x98+4 REN;
 318          sbit at 0x98+5 SM2;
 319          sbit at 0x98+6 SM1;
 320          sbit at 0x98+7 SM0;
 321 sfr at 0x99 SBUF0;
 322
 323 sfr at 0x9A AUTOPTRH1;
 324 sfr at 0x9B AUTOPTRL1;
 325 sfr at 0x9D AUTOPTRH2;
 326 sfr at 0x9E AUTOPTRL2;
 327
 328 sfr at 0xA0 IOC;
 329          /*  IOC  */
 330          sbit at 0xA0 + 0 PC0;
 331          sbit at 0xA0 + 1 PC1;
 332          sbit at 0xA0 + 2 PC2;
 333          sbit at 0xA0 + 3 PC3;
 334          sbit at 0xA0 + 4 PC4;
 335          sbit at 0xA0 + 5 PC5;
 336          sbit at 0xA0 + 6 PC6;
 337          sbit at 0xA0 + 7 PC7;
 338 sfr at 0xA1 INT2CLR;
 339 sfr at 0xA2 INT4CLR;
 340
 341 sfr at 0xA8 IE;
 342          /*  IE  */
 343          sbit at 0xA8+0 EX0;
 344          sbit at 0xA8+1 ET0;
 345          sbit at 0xA8+2 EX1;
 346          sbit at 0xA8+3 ET1;
 347          sbit at 0xA8+4 ES0;
 348          sbit at 0xA8+5 ET2;
 349          sbit at 0xA8+6 ES1;
 350          sbit at 0xA8+7 EA;
 351
 352 sfr at 0xAA EP2468STAT;
 353 sfr at 0xAB EP24FIFOFLGS;
 354 sfr at 0xAC EP68FIFOFLGS;
 355 sfr at 0xAF AUTOPTRSETUP;
 356 sfr at 0xB0 IOD;
 357          /*  IOD  */
 358          sbit at 0xB0 + 0 PD0;
 359          sbit at 0xB0 + 1 PD1;
 360          sbit at 0xB0 + 2 PD2;
 361          sbit at 0xB0 + 3 PD3;
 362          sbit at 0xB0 + 4 PD4;
 363          sbit at 0xB0 + 5 PD5;
 364          sbit at 0xB0 + 6 PD6;
 365          sbit at 0xB0 + 7 PD7;
 366 sfr at 0xB1 IOE;
 367 sfr at 0xB2 OEA;
 368 sfr at 0xB3 OEB;
 369 sfr at 0xB4 OEC;
 370 sfr at 0xB5 OED;
 371 sfr at 0xB6 OEE;
 372
 373 sfr at 0xB8 IP;
 374          /*  IP  */
 375          sbit at 0xB8+0 PX0;
 376          sbit at 0xB8+1 PT0;
 377          sbit at 0xB8+2 PX1;
 378          sbit at 0xB8+3 PT1;
 379          sbit at 0xB8+4 PS0;
 380          sbit at 0xB8+5 PT2;
 381          sbit at 0xB8+6 PS1;
 382
 383 sfr at 0xBA EP01STAT;
 384 sfr at 0xBB GPIFTRIG;
 385
 386 sfr at 0xBD GPIFSGLDATH;
 387 sfr at 0xBE GPIFSGLDATLX;
 388 sfr at 0xBF GPIFSGLDATLNOX;
 389
 390 sfr at 0xC0 SCON1;
 391          /*  SCON1  */
 392          sbit at 0xC0+0 RI1;
 393          sbit at 0xC0+1 TI1;
 394          sbit at 0xC0+2 RB81;
 395          sbit at 0xC0+3 TB81;
 396          sbit at 0xC0+4 REN1;
 397          sbit at 0xC0+5 SM21;
 398          sbit at 0xC0+6 SM11;
 399          sbit at 0xC0+7 SM01;
 400 sfr at 0xC1 SBUF1;
 401 sfr at 0xC8 T2CON;
 402          /*  T2CON  */
 403          sbit at 0xC8+0 CP_RL2;
 404          sbit at 0xC8+1 C_T2;
 405          sbit at 0xC8+2 TR2;
 406          sbit at 0xC8+3 EXEN2;
 407          sbit at 0xC8+4 TCLK;
 408          sbit at 0xC8+5 RCLK;
 409          sbit at 0xC8+6 EXF2;
 410          sbit at 0xC8+7 TF2;
 411 sfr at 0xCA RCAP2L;
 412 sfr at 0xCB RCAP2H;
 413 sfr at 0xCC TL2;
 414 sfr at 0xCD TH2;
 415 sfr at 0xD0 PSW;
 416          /*  PSW  */
 417          sbit at 0xD0+0 P;
 418          sbit at 0xD0+1 FL;
 419          sbit at 0xD0+2 OV;
 420          sbit at 0xD0+3 RS0;
 421          sbit at 0xD0+4 RS1;
 422          sbit at 0xD0+5 F0;
 423          sbit at 0xD0+6 AC;
 424          sbit at 0xD0+7 CY;
 425 sfr at 0xD8 EICON; // Was WDCON in DS80C320; Bit Values differ from Reg320
 426          /*  EICON  */
 427          sbit at 0xD8+3 INT6;
 428          sbit at 0xD8+4 RESI;
 429          sbit at 0xD8+5 ERESI;
 430          sbit at 0xD8+7 SMOD1;
 431 sfr at 0xE0 ACC;
 432 sfr at 0xE8 EIE; // EIE Bit Values differ from Reg320
 433          /*  EIE  */
 434          sbit at 0xE8+0 EUSB;
 435          sbit at 0xE8+1 EI2C;
 436          sbit at 0xE8+2 EIEX4;
 437          sbit at 0xE8+3 EIEX5;
 438          sbit at 0xE8+4 EIEX6;
 439 sfr at 0xF0 B;
 440 sfr at 0xF8 EIP; // EIP Bit Values differ from Reg320
 441          /*  EIP  */
 442          sbit at 0xF8+0 PUSB;
 443          sbit at 0xF8+1 PI2C;
 444          sbit at 0xF8+2 EIPX4;
 445          sbit at 0xF8+3 EIPX5;
 446          sbit at 0xF8+4 EIPX6;
 447
 448
 449 /* CPU Control & Status Register (CPUCS) */
 450 #define bmPRTCSTB    bmBIT5
 451 #define bmCLKSPD     (bmBIT4 | bmBIT3)
 452 #define bmCLKSPD1    bmBIT4
 453 #define bmCLKSPD0    bmBIT3
 454 #define bmCLKINV     bmBIT2
 455 #define bmCLKOE      bmBIT1
 456 #define bm8051RES    bmBIT0
 457 /* Port Alternate Configuration Registers */
 458 /* Port A (PORTACFG) */
 459 #define bmFLAGD      bmBIT7
 460 #define bmINT1       bmBIT1
 461 #define bmINT0       bmBIT0
 462 /* Port C (PORTCCFG) */
 463 #define bmGPIFA7     bmBIT7
 464 #define bmGPIFA6     bmBIT6
 465 #define bmGPIFA5     bmBIT5
 466 #define bmGPIFA4     bmBIT4
 467 #define bmGPIFA3     bmBIT3
 468 #define bmGPIFA2     bmBIT2
 469 #define bmGPIFA1     bmBIT1
 470 #define bmGPIFA0     bmBIT0
 471 /* Port E (PORTECFG) */
 472 #define bmGPIFA8     bmBIT7
 473 #define bmT2EX       bmBIT6
 474 #define bmINT6       bmBIT5
 475 #define bmRXD1OUT    bmBIT4
 476 #define bmRXD0OUT    bmBIT3
 477 #define bmT2OUT      bmBIT2
 478 #define bmT1OUT      bmBIT1
 479 #define bmT0OUT      bmBIT0
 480
 481 /* I2C Control & Status Register (I2CS) */
 482 #define bmSTART      bmBIT7
 483 #define bmSTOP       bmBIT6
 484 #define bmLASTRD     bmBIT5
 485 #define bmID         (bmBIT4 | bmBIT3)
 486 #define bmBERR       bmBIT2
 487 #define bmACK        bmBIT1
 488 #define bmDONE       bmBIT0
 489 /* I2C Control Register (I2CTL) */
 490 #define bmSTOPIE     bmBIT1
 491 #define bm400KHZ     bmBIT0
 492 /* Interrupt 2 (USB) Autovector Register (INT2IVEC) */
 493 #define bmIV4        bmBIT6
 494 #define bmIV3        bmBIT5
 495 #define bmIV2        bmBIT4
 496 #define bmIV1        bmBIT3
 497 #define bmIV0        bmBIT2
 498 /* USB Interrupt Request & Enable Registers (USBIE/USBIRQ) */
 499 #define bmEP0ACK     bmBIT6
 500 #define bmHSGRANT    bmBIT5
 501 #define bmURES       bmBIT4
 502 #define bmSUSP       bmBIT3
 503 #define bmSUTOK      bmBIT2
 504 #define bmSOF        bmBIT1
 505 #define bmSUDAV      bmBIT0
 506 /* USBERRIE/IRQ */
 507 #define bmERRLIMIT  bmBIT0
 508 #define bmISOEP2    bmBIT4
 509 #define bmISOEP4    bmBIT5
 510 #define bmISOEP6    bmBIT6
 511 #define bmISOEP8    bmBIT7
 512
 513 /* Endpoint Interrupt & Enable Registers (EPIE/EPIRQ) */
 514 #define bmEP0IN     bmBIT0
 515 #define bmEP0OUT    bmBIT1
 516 #define bmEP1IN     bmBIT2
 517 #define bmEP1OUT    bmBIT3
 518 #define bmEP2       bmBIT4
 519 #define bmEP4       bmBIT5
 520 #define bmEP6       bmBIT6
 521 #define bmEP8       bmBIT7
 522 /* Breakpoint register (BREAKPT) */
 523 #define bmBREAK      bmBIT3
 524 #define bmBPPULSE    bmBIT2
 525 #define bmBPEN       bmBIT1
 526 /* Interrupt 2 & 4 Setup (INTSETUP) */
 527 #define bmAV2EN      bmBIT3
 528 #define INT4IN       bmBIT1
 529 #define bmAV4EN      bmBIT0
 530 /* USB Control & Status Register (USBCS) */
 531 #define bmHSM        bmBIT7
 532 #define bmDISCON     bmBIT3
 533 #define bmNOSYNSOF   bmBIT2
 534 #define bmRENUM      bmBIT1
 535 #define bmSIGRESUME  bmBIT0
 536 /* Wakeup Control and Status Register (WAKEUPCS) */
 537 #define bmWU2        bmBIT7
 538 #define bmWU         bmBIT6
 539 #define bmWU2POL     bmBIT5
 540 #define bmWUPOL      bmBIT4
 541 #define bmDPEN       bmBIT2
 542 #define bmWU2EN      bmBIT1
 543 #define bmWUEN       bmBIT0
 544 /* End Point 0 Control & Status Register (EP0CS) */
 545 #define bmHSNAK      bmBIT7
 546 /* End Point 0-1 Control & Status Registers (EP0CS/EP1OUTCS/EP1INCS) */
 547 #define bmEPBUSY     bmBIT1
 548 #define bmEPSTALL    bmBIT0
 549 /* End Point 2-8 Control & Status Registers (EP2CS/EP4CS/EP6CS/EP8CS) */
 550 #define bmNPAK       (bmBIT6 | bmBIT5 | bmBIT4)
 551 #define bmEPFULL     bmBIT3
 552 #define bmEPEMPTY    bmBIT2
 553 /* Endpoint Status (EP2468STAT) SFR bits */
 554 #define bmEP8FULL    bmBIT7
 555 #define bmEP8EMPTY   bmBIT6
 556 #define bmEP6FULL    bmBIT5
 557 #define bmEP6EMPTY   bmBIT4
 558 #define bmEP4FULL    bmBIT3
 559 #define bmEP4EMPTY   bmBIT2
 560 #define bmEP2FULL    bmBIT1
 561 #define bmEP2EMPTY   bmBIT0
 562 /* Endpoint Config (EP[24]CFG) */
 563 #define bmBUF       (bmBIT0|bmBIT1)
 564 /* Endpoint Config (EP[2468]CFG) */
 565 #define bmSIZE      bmBIT3
 566 #define bmTYPE      (bmBIT4|bmBIT5)
 567 #define bmDIR       bmBIT6
 568 #define bmVALID     bmBIT7
 569 /* SETUP Data Pointer Auto Mode (SUDPTRCTL) */
 570 #define bmSDPAUTO    bmBIT0
 571 /* Endpoint Data Toggle Control (TOGCTL) */
 572 #define bmQUERYTOGGLE  bmBIT7
 573 #define bmSETTOGGLE    bmBIT6
 574 #define bmRESETTOGGLE  bmBIT5
 575 #define bmTOGCTLEPMASK bmBIT3 | bmBIT2 | bmBIT1 | bmBIT0
 576 /* IBN (In Bulk Nak) enable and request bits (IBNIE/IBNIRQ) */
 577 #define bmEP8IBN     bmBIT5
 578 #define bmEP6IBN     bmBIT4
 579 #define bmEP4IBN     bmBIT3
 580 #define bmEP2IBN     bmBIT2
 581 #define bmEP1IBN     bmBIT1
 582 #define bmEP0IBN     bmBIT0
 583
 584 /* PING-NAK enable and request bits (NAKIE/NAKIRQ) */
 585 #define bmEP8PING     bmBIT7
 586 #define bmEP6PING     bmBIT6
 587 #define bmEP4PING     bmBIT5
 588 #define bmEP2PING     bmBIT4
 589 #define bmEP1PING     bmBIT3
 590 #define bmEP0PING     bmBIT2
 591 #define bmIBN         bmBIT0
 592
 593 /* Interface Configuration bits (IFCONFIG) */
 594 #define bmIFCLKSRC    bmBIT7
 595 #define bm3048MHZ     bmBIT6
 596 #define bmIFCLKOE     bmBIT5
 597 #define bmIFCLKPOL    bmBIT4
 598 #define bmASYNC       bmBIT3
 599 #define bmGSTATE      bmBIT2
 600 #define bmIFCFG1      bmBIT1
 601 #define bmIFCFG0      bmBIT0
 602 #define bmIFCFGMASK   (bmIFCFG0 | bmIFCFG1)
 603 #define bmIFGPIF      bmIFCFG1
 604
 605 /* EP 2468 FIFO Configuration bits (EP2FIFOCFG,EP4FIFOCFG,EP6FIFOCFG,EP8FIFOCFG) */
 606 #define bmINFM       bmBIT6
 607 #define bmOEP        bmBIT5
 608 #define bmAUTOOUT    bmBIT4
 609 #define bmAUTOIN     bmBIT3
 610 #define bmZEROLENIN  bmBIT2
 611 #define bmWORDWIDE   bmBIT0
 612
 613 /* Chip Revision Control Bits (REVCTL) - used to ebable/disable revision specidic
 614    features */
 615 #define bmNOAUTOARM    bmBIT1
 616 #define bmSKIPCOMMIT   bmBIT0
 617
 618 /* Fifo Reset bits (FIFORESET) */
 619 #define bmNAKALL       bmBIT7
 620
 621 /* Chip Feature Register (GPCR2) */
 622 #define bmFULLSPEEDONLY    bmBIT4
 623
 624 #endif   /* FX2REGS_H */