1 /* structural Verilog generated by gnetlist */
2 /* WARNING: This is a generated file, edits */
3 /* made here will be lost next time */
4 /* you run gnetlist! */
5 /* Id ..........$Id$ */
6 /* Source.......$Source$ */
7 /* Revision.....$Revision$ */
8 /* Author.......$Author$ */
14 /* Port directions begin here */
17 /* Wires from the design */
26 /* continuous assignments */
28 /* Package instantiations */
33 \cascade-transformer T1 (
48 \cascade-defaults DEF1 (
58 \cascade-source SOURCE (
62 \cascade-defaults-top DEFAULTS (