arch/sh/kernel/timers/timer-tmu.c

   1 /*
   2  * arch/sh/kernel/timers/timer-tmu.c - TMU Timer Support
   3  *
   4  *  Copyright (C) 2005  Paul Mundt
   5  *
   6  * TMU handling code hacked out of arch/sh/kernel/time.c
   7  *
   8  *  Copyright (C) 1999  Tetsuya Okada & Niibe Yutaka
   9  *  Copyright (C) 2000  Philipp Rumpf <prumpf@tux.org>
  10  *  Copyright (C) 2002, 2003, 2004  Paul Mundt
  11  *  Copyright (C) 2002  M. R. Brown  <mrbrown@linux-sh.org>
  12  *
  13  * This file is subject to the terms and conditions of the GNU General Public
  14  * License.  See the file "COPYING" in the main directory of this archive
  15  * for more details.
  16  */
  17 #include <linux/init.h>
  18 #include <linux/kernel.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/seqlock.h>
  22 #include <asm/timer.h>
  23 #include <asm/rtc.h>
  24 #include <asm/io.h>
  25 #include <asm/irq.h>
  26 #include <asm/clock.h>
  27
  28 #define TMU_TOCR_INIT   0x00
  29 #define TMU0_TCR_INIT   0x0020
  30 #define TMU_TSTR_INIT   1
  31
  32 #define TMU0_TCR_CALIB  0x0000
  33
  34 static DEFINE_SPINLOCK(tmu0_lock);
  35
  36 static unsigned long tmu_timer_get_offset(void)
  37 {
  38         int count;
  39         unsigned long flags;
  40
  41         static int count_p = 0x7fffffff;    /* for the first call after boot */
  42         static unsigned long jiffies_p = 0;
  43
  44         /*
  45          * cache volatile jiffies temporarily; we have IRQs turned off.
  46          */
  47         unsigned long jiffies_t;
  48
  49         spin_lock_irqsave(&tmu0_lock, flags);
  50         /* timer count may underflow right here */
  51         count = ctrl_inl(TMU0_TCNT);    /* read the latched count */
  52
  53         jiffies_t = jiffies;
  54
  55         /*
  56          * avoiding timer inconsistencies (they are rare, but they happen)...
  57          * there is one kind of problem that must be avoided here:
  58          *  1. the timer counter underflows
  59          */
  60
  61         if (jiffies_t == jiffies_p) {
  62                 if (count > count_p) {
  63                         /* the nutcase */
  64                         if (ctrl_inw(TMU0_TCR) & 0x100) { /* Check UNF bit */
  65                                 count -= LATCH;
  66                         } else {
  67                                 printk("%s (): hardware timer problem?\n",
  68                                        __FUNCTION__);
  69                         }
  70                 }
  71         } else
  72                 jiffies_p = jiffies_t;
  73
  74         count_p = count;
  75         spin_unlock_irqrestore(&tmu0_lock, flags);
  76
  77         count = ((LATCH-1) - count) * TICK_SIZE;
  78         count = (count + LATCH/2) / LATCH;
  79
  80         return count;
  81 }
  82
  83 static irqreturn_t tmu_timer_interrupt(int irq, void *dev_id,
  84                                        struct pt_regs *regs)
  85 {
  86         unsigned long timer_status;
  87
  88         /* Clear UNF bit */
  89         timer_status = ctrl_inw(TMU0_TCR);
  90         timer_status &= ~0x100;
  91         ctrl_outw(timer_status, TMU0_TCR);
  92
  93         /*
  94          * Here we are in the timer irq handler. We just have irqs locally
  95          * disabled but we don't know if the timer_bh is running on the other
  96          * CPU. We need to avoid to SMP race with it. NOTE: we don' t need
  97          * the irq version of write_lock because as just said we have irq
  98          * locally disabled. -arca
  99          */
 100         write_seqlock(&xtime_lock);
 101         handle_timer_tick(regs);
 102         write_sequnlock(&xtime_lock);
 103
 104         return IRQ_HANDLED;
 105 }
 106
 107 static struct irqaction tmu_irq = {
 108         .name           = "timer",
 109         .handler        = tmu_timer_interrupt,
 110         .flags          = IRQF_DISABLED,
 111         .mask           = CPU_MASK_NONE,
 112 };
 113
 114 /*
 115  * Hah!  We'll see if this works (switching from usecs to nsecs).
 116  */
 117 static unsigned long tmu_timer_get_frequency(void)
 118 {
 119         u32 freq;
 120         struct timespec ts1, ts2;
 121         unsigned long diff_nsec;
 122         unsigned long factor;
 123
 124         /* Setup the timer:  We don't want to generate interrupts, just
 125          * have it count down at its natural rate.
 126          */
 127         ctrl_outb(0, TMU_TSTR);
 128 #if !defined(CONFIG_CPU_SUBTYPE_SH7300) && !defined(CONFIG_CPU_SUBTYPE_SH7760)
 129         ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
 130 #endif
 131         ctrl_outw(TMU0_TCR_CALIB, TMU0_TCR);
 132         ctrl_outl(0xffffffff, TMU0_TCOR);
 133         ctrl_outl(0xffffffff, TMU0_TCNT);
 134
 135         rtc_get_time(&ts2);
 136
 137         do {
 138                 rtc_get_time(&ts1);
 139         } while (ts1.tv_nsec == ts2.tv_nsec && ts1.tv_sec == ts2.tv_sec);
 140
 141         /* actually start the timer */
 142         ctrl_outb(TMU_TSTR_INIT, TMU_TSTR);
 143
 144         do {
 145                 rtc_get_time(&ts2);
 146         } while (ts1.tv_nsec == ts2.tv_nsec && ts1.tv_sec == ts2.tv_sec);
 147
 148         freq = 0xffffffff - ctrl_inl(TMU0_TCNT);
 149         if (ts2.tv_nsec < ts1.tv_nsec) {
 150                 ts2.tv_nsec += 1000000000;
 151                 ts2.tv_sec--;
 152         }
 153
 154         diff_nsec = (ts2.tv_sec - ts1.tv_sec) * 1000000000 + (ts2.tv_nsec - ts1.tv_nsec);
 155
 156         /* this should work well if the RTC has a precision of n Hz, where
 157          * n is an integer.  I don't think we have to worry about the other
 158          * cases. */
 159         factor = (1000000000 + diff_nsec/2) / diff_nsec;
 160
 161         if (factor * diff_nsec > 1100000000 ||
 162             factor * diff_nsec <  900000000)
 163                 panic("weird RTC (diff_nsec %ld)", diff_nsec);
 164
 165         return freq * factor;
 166 }
 167
 168 static void tmu_clk_init(struct clk *clk)
 169 {
 170         u8 divisor = TMU0_TCR_INIT & 0x7;
 171         ctrl_outw(TMU0_TCR_INIT, TMU0_TCR);
 172         clk->rate = clk->parent->rate / (4 << (divisor << 1));
 173 }
 174
 175 static void tmu_clk_recalc(struct clk *clk)
 176 {
 177         u8 divisor = ctrl_inw(TMU0_TCR) & 0x7;
 178         clk->rate = clk->parent->rate / (4 << (divisor << 1));
 179 }
 180
 181 static struct clk_ops tmu_clk_ops = {
 182         .init           = tmu_clk_init,
 183         .recalc         = tmu_clk_recalc,
 184 };
 185
 186 static struct clk tmu0_clk = {
 187         .name           = "tmu0_clk",
 188         .ops            = &tmu_clk_ops,
 189 };
 190
 191 static int tmu_timer_init(void)
 192 {
 193         unsigned long interval;
 194
 195         setup_irq(TIMER_IRQ, &tmu_irq);
 196
 197         tmu0_clk.parent = clk_get("module_clk");
 198
 199         /* Start TMU0 */
 200         ctrl_outb(0, TMU_TSTR);
 201 #if !defined(CONFIG_CPU_SUBTYPE_SH7300) && !defined(CONFIG_CPU_SUBTYPE_SH7760)
 202         ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
 203 #endif
 204
 205         clk_register(&tmu0_clk);
 206         clk_enable(&tmu0_clk);
 207
 208         interval = (clk_get_rate(&tmu0_clk) + HZ / 2) / HZ;
 209         printk(KERN_INFO "Interval = %ld\n", interval);
 210
 211         ctrl_outl(interval, TMU0_TCOR);
 212         ctrl_outl(interval, TMU0_TCNT);
 213
 214         ctrl_outb(TMU_TSTR_INIT, TMU_TSTR);
 215
 216         return 0;
 217 }
 218
 219 struct sys_timer_ops tmu_timer_ops = {
 220         .init           = tmu_timer_init,
 221         .get_frequency  = tmu_timer_get_frequency,
 222         .get_offset     = tmu_timer_get_offset,
 223 };
 224
 225 struct sys_timer tmu_timer = {
 226         .name   = "tmu",
 227         .ops    = &tmu_timer_ops,
 228 };
 229