arch/x86_64/kernel/i8259.c

   1 #include <linux/linkage.h>
   2 #include <linux/errno.h>
   3 #include <linux/signal.h>
   4 #include <linux/sched.h>
   5 #include <linux/ioport.h>
   6 #include <linux/interrupt.h>
   7 #include <linux/timex.h>
   8 #include <linux/slab.h>
   9 #include <linux/random.h>
  10 #include <linux/smp_lock.h>
  11 #include <linux/init.h>
  12 #include <linux/kernel_stat.h>
  13 #include <linux/sysdev.h>
  14 #include <linux/bitops.h>
  15
  16 #include <asm/acpi.h>
  17 #include <asm/atomic.h>
  18 #include <asm/system.h>
  19 #include <asm/io.h>
  20 #include <asm/hw_irq.h>
  21 #include <asm/pgtable.h>
  22 #include <asm/delay.h>
  23 #include <asm/desc.h>
  24 #include <asm/apic.h>
  25
  26 /*
  27  * Common place to define all x86 IRQ vectors
  28  *
  29  * This builds up the IRQ handler stubs using some ugly macros in irq.h
  30  *
  31  * These macros create the low-level assembly IRQ routines that save
  32  * register context and call do_IRQ(). do_IRQ() then does all the
  33  * operations that are needed to keep the AT (or SMP IOAPIC)
  34  * interrupt-controller happy.
  35  */
  36
  37 #define BI(x,y) \
  38         BUILD_IRQ(x##y)
  39
  40 #define BUILD_16_IRQS(x) \
  41         BI(x,0) BI(x,1) BI(x,2) BI(x,3) \
  42         BI(x,4) BI(x,5) BI(x,6) BI(x,7) \
  43         BI(x,8) BI(x,9) BI(x,a) BI(x,b) \
  44         BI(x,c) BI(x,d) BI(x,e) BI(x,f)
  45
  46 #define BUILD_15_IRQS(x) \
  47         BI(x,0) BI(x,1) BI(x,2) BI(x,3) \
  48         BI(x,4) BI(x,5) BI(x,6) BI(x,7) \
  49         BI(x,8) BI(x,9) BI(x,a) BI(x,b) \
  50         BI(x,c) BI(x,d) BI(x,e)
  51
  52 /*
  53  * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
  54  * (these are usually mapped to vectors 0x20-0x2f)
  55  */
  56 BUILD_16_IRQS(0x0)
  57
  58 #ifdef CONFIG_X86_LOCAL_APIC
  59 /*
  60  * The IO-APIC gives us many more interrupt sources. Most of these
  61  * are unused but an SMP system is supposed to have enough memory ...
  62  * sometimes (mostly wrt. hw bugs) we get corrupted vectors all
  63  * across the spectrum, so we really want to be prepared to get all
  64  * of these. Plus, more powerful systems might have more than 64
  65  * IO-APIC registers.
  66  *
  67  * (these are usually mapped into the 0x30-0xff vector range)
  68  */
  69                    BUILD_16_IRQS(0x1) BUILD_16_IRQS(0x2) BUILD_16_IRQS(0x3)
  70 BUILD_16_IRQS(0x4) BUILD_16_IRQS(0x5) BUILD_16_IRQS(0x6) BUILD_16_IRQS(0x7)
  71 BUILD_16_IRQS(0x8) BUILD_16_IRQS(0x9) BUILD_16_IRQS(0xa) BUILD_16_IRQS(0xb)
  72 BUILD_16_IRQS(0xc) BUILD_16_IRQS(0xd)
  73
  74 #ifdef CONFIG_PCI_MSI
  75         BUILD_15_IRQS(0xe)
  76 #endif
  77
  78 #endif
  79
  80 #undef BUILD_16_IRQS
  81 #undef BUILD_15_IRQS
  82 #undef BI
  83
  84
  85 #define IRQ(x,y) \
  86         IRQ##x##y##_interrupt
  87
  88 #define IRQLIST_16(x) \
  89         IRQ(x,0), IRQ(x,1), IRQ(x,2), IRQ(x,3), \
  90         IRQ(x,4), IRQ(x,5), IRQ(x,6), IRQ(x,7), \
  91         IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \
  92         IRQ(x,c), IRQ(x,d), IRQ(x,e), IRQ(x,f)
  93
  94 #define IRQLIST_15(x) \
  95         IRQ(x,0), IRQ(x,1), IRQ(x,2), IRQ(x,3), \
  96         IRQ(x,4), IRQ(x,5), IRQ(x,6), IRQ(x,7), \
  97         IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \
  98         IRQ(x,c), IRQ(x,d), IRQ(x,e)
  99
 100 void (*interrupt[NR_IRQS])(void) = {
 101         IRQLIST_16(0x0),
 102
 103 #ifdef CONFIG_X86_IO_APIC
 104                          IRQLIST_16(0x1), IRQLIST_16(0x2), IRQLIST_16(0x3),
 105         IRQLIST_16(0x4), IRQLIST_16(0x5), IRQLIST_16(0x6), IRQLIST_16(0x7),
 106         IRQLIST_16(0x8), IRQLIST_16(0x9), IRQLIST_16(0xa), IRQLIST_16(0xb),
 107         IRQLIST_16(0xc), IRQLIST_16(0xd)
 108
 109 #ifdef CONFIG_PCI_MSI
 110         , IRQLIST_15(0xe)
 111 #endif
 112
 113 #endif
 114 };
 115
 116 #undef IRQ
 117 #undef IRQLIST_16
 118 #undef IRQLIST_14
 119
 120 /*
 121  * This is the 'legacy' 8259A Programmable Interrupt Controller,
 122  * present in the majority of PC/AT boxes.
 123  * plus some generic x86 specific things if generic specifics makes
 124  * any sense at all.
 125  * this file should become arch/i386/kernel/irq.c when the old irq.c
 126  * moves to arch independent land
 127  */
 128
 129 DEFINE_SPINLOCK(i8259A_lock);
 130
 131 static void end_8259A_irq (unsigned int irq)
 132 {
 133         if (irq > 256) {
 134                 char var;
 135                 printk("return %p stack %p ti %p\n", __builtin_return_address(0), &var, task_thread_info(current));
 136
 137                 BUG();
 138         }
 139
 140         if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)) &&
 141             irq_desc[irq].action)
 142                 enable_8259A_irq(irq);
 143 }
 144
 145 #define shutdown_8259A_irq      disable_8259A_irq
 146
 147 static void mask_and_ack_8259A(unsigned int);
 148
 149 static unsigned int startup_8259A_irq(unsigned int irq)
 150 {
 151         enable_8259A_irq(irq);
 152         return 0; /* never anything pending */
 153 }
 154
 155 static struct hw_interrupt_type i8259A_irq_type = {
 156         .typename = "XT-PIC",
 157         .startup = startup_8259A_irq,
 158         .shutdown = shutdown_8259A_irq,
 159         .enable = enable_8259A_irq,
 160         .disable = disable_8259A_irq,
 161         .ack = mask_and_ack_8259A,
 162         .end = end_8259A_irq,
 163 };
 164
 165 /*
 166  * 8259A PIC functions to handle ISA devices:
 167  */
 168
 169 /*
 170  * This contains the irq mask for both 8259A irq controllers,
 171  */
 172 static unsigned int cached_irq_mask = 0xffff;
 173
 174 #define __byte(x,y)     (((unsigned char *)&(y))[x])
 175 #define cached_21       (__byte(0,cached_irq_mask))
 176 #define cached_A1       (__byte(1,cached_irq_mask))
 177
 178 /*
 179  * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
 180  * boards the timer interrupt is not really connected to any IO-APIC pin,
 181  * it's fed to the master 8259A's IR0 line only.
 182  *
 183  * Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
 184  * this 'mixed mode' IRQ handling costs nothing because it's only used
 185  * at IRQ setup time.
 186  */
 187 unsigned long io_apic_irqs;
 188
 189 void disable_8259A_irq(unsigned int irq)
 190 {
 191         unsigned int mask = 1 << irq;
 192         unsigned long flags;
 193
 194         spin_lock_irqsave(&i8259A_lock, flags);
 195         cached_irq_mask |= mask;
 196         if (irq & 8)
 197                 outb(cached_A1,0xA1);
 198         else
 199                 outb(cached_21,0x21);
 200         spin_unlock_irqrestore(&i8259A_lock, flags);
 201 }
 202
 203 void enable_8259A_irq(unsigned int irq)
 204 {
 205         unsigned int mask = ~(1 << irq);
 206         unsigned long flags;
 207
 208         spin_lock_irqsave(&i8259A_lock, flags);
 209         cached_irq_mask &= mask;
 210         if (irq & 8)
 211                 outb(cached_A1,0xA1);
 212         else
 213                 outb(cached_21,0x21);
 214         spin_unlock_irqrestore(&i8259A_lock, flags);
 215 }
 216
 217 int i8259A_irq_pending(unsigned int irq)
 218 {
 219         unsigned int mask = 1<<irq;
 220         unsigned long flags;
 221         int ret;
 222
 223         spin_lock_irqsave(&i8259A_lock, flags);
 224         if (irq < 8)
 225                 ret = inb(0x20) & mask;
 226         else
 227                 ret = inb(0xA0) & (mask >> 8);
 228         spin_unlock_irqrestore(&i8259A_lock, flags);
 229
 230         return ret;
 231 }
 232
 233 void make_8259A_irq(unsigned int irq)
 234 {
 235         disable_irq_nosync(irq);
 236         io_apic_irqs &= ~(1<<irq);
 237         irq_desc[irq].chip = &i8259A_irq_type;
 238         enable_irq(irq);
 239 }
 240
 241 /*
 242  * This function assumes to be called rarely. Switching between
 243  * 8259A registers is slow.
 244  * This has to be protected by the irq controller spinlock
 245  * before being called.
 246  */
 247 static inline int i8259A_irq_real(unsigned int irq)
 248 {
 249         int value;
 250         int irqmask = 1<<irq;
 251
 252         if (irq < 8) {
 253                 outb(0x0B,0x20);                /* ISR register */
 254                 value = inb(0x20) & irqmask;
 255                 outb(0x0A,0x20);                /* back to the IRR register */
 256                 return value;
 257         }
 258         outb(0x0B,0xA0);                /* ISR register */
 259         value = inb(0xA0) & (irqmask >> 8);
 260         outb(0x0A,0xA0);                /* back to the IRR register */
 261         return value;
 262 }
 263
 264 /*
 265  * Careful! The 8259A is a fragile beast, it pretty
 266  * much _has_ to be done exactly like this (mask it
 267  * first, _then_ send the EOI, and the order of EOI
 268  * to the two 8259s is important!
 269  */
 270 static void mask_and_ack_8259A(unsigned int irq)
 271 {
 272         unsigned int irqmask = 1 << irq;
 273         unsigned long flags;
 274
 275         spin_lock_irqsave(&i8259A_lock, flags);
 276         /*
 277          * Lightweight spurious IRQ detection. We do not want
 278          * to overdo spurious IRQ handling - it's usually a sign
 279          * of hardware problems, so we only do the checks we can
 280          * do without slowing down good hardware unnecessarily.
 281          *
 282          * Note that IRQ7 and IRQ15 (the two spurious IRQs
 283          * usually resulting from the 8259A-1|2 PICs) occur
 284          * even if the IRQ is masked in the 8259A. Thus we
 285          * can check spurious 8259A IRQs without doing the
 286          * quite slow i8259A_irq_real() call for every IRQ.
 287          * This does not cover 100% of spurious interrupts,
 288          * but should be enough to warn the user that there
 289          * is something bad going on ...
 290          */
 291         if (cached_irq_mask & irqmask)
 292                 goto spurious_8259A_irq;
 293         cached_irq_mask |= irqmask;
 294
 295 handle_real_irq:
 296         if (irq & 8) {
 297                 inb(0xA1);              /* DUMMY - (do we need this?) */
 298                 outb(cached_A1,0xA1);
 299                 outb(0x60+(irq&7),0xA0);/* 'Specific EOI' to slave */
 300                 outb(0x62,0x20);        /* 'Specific EOI' to master-IRQ2 */
 301         } else {
 302                 inb(0x21);              /* DUMMY - (do we need this?) */
 303                 outb(cached_21,0x21);
 304                 outb(0x60+irq,0x20);    /* 'Specific EOI' to master */
 305         }
 306         spin_unlock_irqrestore(&i8259A_lock, flags);
 307         return;
 308
 309 spurious_8259A_irq:
 310         /*
 311          * this is the slow path - should happen rarely.
 312          */
 313         if (i8259A_irq_real(irq))
 314                 /*
 315                  * oops, the IRQ _is_ in service according to the
 316                  * 8259A - not spurious, go handle it.
 317                  */
 318                 goto handle_real_irq;
 319
 320         {
 321                 static int spurious_irq_mask;
 322                 /*
 323                  * At this point we can be sure the IRQ is spurious,
 324                  * lets ACK and report it. [once per IRQ]
 325                  */
 326                 if (!(spurious_irq_mask & irqmask)) {
 327                         printk(KERN_DEBUG "spurious 8259A interrupt: IRQ%d.\n", irq);
 328                         spurious_irq_mask |= irqmask;
 329                 }
 330                 atomic_inc(&irq_err_count);
 331                 /*
 332                  * Theoretically we do not have to handle this IRQ,
 333                  * but in Linux this does not cause problems and is
 334                  * simpler for us.
 335                  */
 336                 goto handle_real_irq;
 337         }
 338 }
 339
 340 void init_8259A(int auto_eoi)
 341 {
 342         unsigned long flags;
 343
 344         spin_lock_irqsave(&i8259A_lock, flags);
 345
 346         outb(0xff, 0x21);       /* mask all of 8259A-1 */
 347         outb(0xff, 0xA1);       /* mask all of 8259A-2 */
 348
 349         /*
 350          * outb_p - this has to work on a wide range of PC hardware.
 351          */
 352         outb_p(0x11, 0x20);     /* ICW1: select 8259A-1 init */
 353         outb_p(0x20 + 0, 0x21); /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
 354         outb_p(0x04, 0x21);     /* 8259A-1 (the master) has a slave on IR2 */
 355         if (auto_eoi)
 356                 outb_p(0x03, 0x21);     /* master does Auto EOI */
 357         else
 358                 outb_p(0x01, 0x21);     /* master expects normal EOI */
 359
 360         outb_p(0x11, 0xA0);     /* ICW1: select 8259A-2 init */
 361         outb_p(0x20 + 8, 0xA1); /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
 362         outb_p(0x02, 0xA1);     /* 8259A-2 is a slave on master's IR2 */
 363         outb_p(0x01, 0xA1);     /* (slave's support for AEOI in flat mode
 364                                     is to be investigated) */
 365
 366         if (auto_eoi)
 367                 /*
 368                  * in AEOI mode we just have to mask the interrupt
 369                  * when acking.
 370                  */
 371                 i8259A_irq_type.ack = disable_8259A_irq;
 372         else
 373                 i8259A_irq_type.ack = mask_and_ack_8259A;
 374
 375         udelay(100);            /* wait for 8259A to initialize */
 376
 377         outb(cached_21, 0x21);  /* restore master IRQ mask */
 378         outb(cached_A1, 0xA1);  /* restore slave IRQ mask */
 379
 380         spin_unlock_irqrestore(&i8259A_lock, flags);
 381 }
 382
 383 static char irq_trigger[2];
 384 /**
 385  * ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
 386  */
 387 static void restore_ELCR(char *trigger)
 388 {
 389         outb(trigger[0], 0x4d0);
 390         outb(trigger[1], 0x4d1);
 391 }
 392
 393 static void save_ELCR(char *trigger)
 394 {
 395         /* IRQ 0,1,2,8,13 are marked as reserved */
 396         trigger[0] = inb(0x4d0) & 0xF8;
 397         trigger[1] = inb(0x4d1) & 0xDE;
 398 }
 399
 400 static int i8259A_resume(struct sys_device *dev)
 401 {
 402         init_8259A(0);
 403         restore_ELCR(irq_trigger);
 404         return 0;
 405 }
 406
 407 static int i8259A_suspend(struct sys_device *dev, pm_message_t state)
 408 {
 409         save_ELCR(irq_trigger);
 410         return 0;
 411 }
 412
 413 static int i8259A_shutdown(struct sys_device *dev)
 414 {
 415         /* Put the i8259A into a quiescent state that
 416          * the kernel initialization code can get it
 417          * out of.
 418          */
 419         outb(0xff, 0x21);       /* mask all of 8259A-1 */
 420         outb(0xff, 0xA1);       /* mask all of 8259A-1 */
 421         return 0;
 422 }
 423
 424 static struct sysdev_class i8259_sysdev_class = {
 425         set_kset_name("i8259"),
 426         .suspend = i8259A_suspend,
 427         .resume = i8259A_resume,
 428         .shutdown = i8259A_shutdown,
 429 };
 430
 431 static struct sys_device device_i8259A = {
 432         .id     = 0,
 433         .cls    = &i8259_sysdev_class,
 434 };
 435
 436 static int __init i8259A_init_sysfs(void)
 437 {
 438         int error = sysdev_class_register(&i8259_sysdev_class);
 439         if (!error)
 440                 error = sysdev_register(&device_i8259A);
 441         return error;
 442 }
 443
 444 device_initcall(i8259A_init_sysfs);
 445
 446 /*
 447  * IRQ2 is cascade interrupt to second interrupt controller
 448  */
 449
 450 static struct irqaction irq2 = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL};
 451
 452 void __init init_ISA_irqs (void)
 453 {
 454         int i;
 455
 456 #ifdef CONFIG_X86_LOCAL_APIC
 457         init_bsp_APIC();
 458 #endif
 459         init_8259A(0);
 460
 461         for (i = 0; i < NR_IRQS; i++) {
 462                 irq_desc[i].status = IRQ_DISABLED;
 463                 irq_desc[i].action = NULL;
 464                 irq_desc[i].depth = 1;
 465
 466                 if (i < 16) {
 467                         /*
 468                          * 16 old-style INTA-cycle interrupts:
 469                          */
 470                         irq_desc[i].chip = &i8259A_irq_type;
 471                 } else {
 472                         /*
 473                          * 'high' PCI IRQs filled in on demand
 474                          */
 475                         irq_desc[i].chip = &no_irq_type;
 476                 }
 477         }
 478 }
 479
 480 void apic_timer_interrupt(void);
 481 void spurious_interrupt(void);
 482 void error_interrupt(void);
 483 void reschedule_interrupt(void);
 484 void call_function_interrupt(void);
 485 void invalidate_interrupt0(void);
 486 void invalidate_interrupt1(void);
 487 void invalidate_interrupt2(void);
 488 void invalidate_interrupt3(void);
 489 void invalidate_interrupt4(void);
 490 void invalidate_interrupt5(void);
 491 void invalidate_interrupt6(void);
 492 void invalidate_interrupt7(void);
 493 void thermal_interrupt(void);
 494 void threshold_interrupt(void);
 495 void i8254_timer_resume(void);
 496
 497 static void setup_timer_hardware(void)
 498 {
 499         outb_p(0x34,0x43);              /* binary, mode 2, LSB/MSB, ch 0 */
 500         udelay(10);
 501         outb_p(LATCH & 0xff , 0x40);    /* LSB */
 502         udelay(10);
 503         outb(LATCH >> 8 , 0x40);        /* MSB */
 504 }
 505
 506 static int timer_resume(struct sys_device *dev)
 507 {
 508         setup_timer_hardware();
 509         return 0;
 510 }
 511
 512 void i8254_timer_resume(void)
 513 {
 514         setup_timer_hardware();
 515 }
 516
 517 static struct sysdev_class timer_sysclass = {
 518         set_kset_name("timer_pit"),
 519         .resume         = timer_resume,
 520 };
 521
 522 static struct sys_device device_timer = {
 523         .id             = 0,
 524         .cls            = &timer_sysclass,
 525 };
 526
 527 static int __init init_timer_sysfs(void)
 528 {
 529         int error = sysdev_class_register(&timer_sysclass);
 530         if (!error)
 531                 error = sysdev_register(&device_timer);
 532         return error;
 533 }
 534
 535 device_initcall(init_timer_sysfs);
 536
 537 void __init init_IRQ(void)
 538 {
 539         int i;
 540
 541         init_ISA_irqs();
 542         /*
 543          * Cover the whole vector space, no vector can escape
 544          * us. (some of these will be overridden and become
 545          * 'special' SMP interrupts)
 546          */
 547         for (i = 0; i < (NR_VECTORS - FIRST_EXTERNAL_VECTOR); i++) {
 548                 int vector = FIRST_EXTERNAL_VECTOR + i;
 549                 if (i >= NR_IRQS)
 550                         break;
 551                 if (vector != IA32_SYSCALL_VECTOR)
 552                         set_intr_gate(vector, interrupt[i]);
 553         }
 554
 555 #ifdef CONFIG_SMP
 556         /*
 557          * IRQ0 must be given a fixed assignment and initialized,
 558          * because it's used before the IO-APIC is set up.
 559          */
 560         set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]);
 561
 562         /*
 563          * The reschedule interrupt is a CPU-to-CPU reschedule-helper
 564          * IPI, driven by wakeup.
 565          */
 566         set_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
 567
 568         /* IPIs for invalidation */
 569         set_intr_gate(INVALIDATE_TLB_VECTOR_START+0, invalidate_interrupt0);
 570         set_intr_gate(INVALIDATE_TLB_VECTOR_START+1, invalidate_interrupt1);
 571         set_intr_gate(INVALIDATE_TLB_VECTOR_START+2, invalidate_interrupt2);
 572         set_intr_gate(INVALIDATE_TLB_VECTOR_START+3, invalidate_interrupt3);
 573         set_intr_gate(INVALIDATE_TLB_VECTOR_START+4, invalidate_interrupt4);
 574         set_intr_gate(INVALIDATE_TLB_VECTOR_START+5, invalidate_interrupt5);
 575         set_intr_gate(INVALIDATE_TLB_VECTOR_START+6, invalidate_interrupt6);
 576         set_intr_gate(INVALIDATE_TLB_VECTOR_START+7, invalidate_interrupt7);
 577
 578         /* IPI for generic function call */
 579         set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
 580 #endif
 581         set_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
 582         set_intr_gate(THRESHOLD_APIC_VECTOR, threshold_interrupt);
 583
 584 #ifdef CONFIG_X86_LOCAL_APIC
 585         /* self generated IPI for local APIC timer */
 586         set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
 587
 588         /* IPI vectors for APIC spurious and error interrupts */
 589         set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
 590         set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
 591 #endif
 592
 593         /*
 594          * Set the clock to HZ Hz, we already have a valid
 595          * vector now:
 596          */
 597         setup_timer_hardware();
 598
 599         if (!acpi_ioapic)
 600                 setup_irq(2, &irq2);
 601 }