include/arch.h

   1 /*
   2  * (C) Copyright 2007-2011  Josef 'Jeff' Sipek <jeffpc@josefsipek.net>
   3  *
   4  * This file is released under the GPLv2.  See the COPYING file for more
   5  * details.
   6  */
   7
   8 #ifndef __ARCH_H
   9 #define __ARCH_H
  10
  11 /*
  12  * PSW and PSW handling
  13  */
  14 struct psw {
  15         u8 _zero0:1,
  16            r:1,                 /* PER Mask (R)                 */
  17            _zero1:3,
  18            t:1,                 /* DAT Mode (T)                 */
  19            io:1,                /* I/O Mask (IO)                */
  20            ex:1;                /* External Mask (EX)           */
  21
  22         u8 key:4,               /* Key                          */
  23            fmt:1,               /* 1 on 390, 0 on z             */
  24            m:1,                 /* Machine-Check Mask (M)       */
  25            w:1,                 /* Wait State (W)               */
  26            p:1;                 /* Problem State (P)            */
  27
  28         u8 as:2,                /* Address-Space Control (AS)   */
  29            cc:2,                /* Condition Code (CC)          */
  30            prog_mask:4;         /* Program Mask                 */
  31
  32         u8 _zero2:7,
  33            ea:1;                /* Extended Addressing (EA)     */
  34
  35         u32 ba:1,               /* Basic Addressing (BA)        */
  36             ptr31:31;
  37
  38         u64 ptr;
  39 } __attribute__((packed,aligned(8)));
  40
  41 static inline void lpswe(struct psw *psw)
  42 {
  43         asm volatile(
  44                 "       lpswe   %0\n"
  45         : /* output */
  46         : /* input */
  47           "m" (*psw)
  48         );
  49 }
  50
  51 /*
  52  * Control Register handling
  53  */
  54 #define set_cr(cr, val)                                         \
  55         do {                                                    \
  56                 u64 lval = (val);                               \
  57                 asm volatile(                                   \
  58                         "lctlg  %1,%1,%0\n"                     \
  59                 : /* output */                                  \
  60                 : /* input */                                   \
  61                   "m" (lval),                                   \
  62                   "i" (cr)                                      \
  63                 );                                              \
  64         } while(0)
  65
  66 #define get_cr(cr)                                              \
  67         ({                                                      \
  68                 u64 reg;                                        \
  69                                                                 \
  70                 asm volatile(                                   \
  71                         "stctg  %1,%1,%0\n"                     \
  72                 : /* output */                                  \
  73                   "=m" (reg)                                    \
  74                 : /* input */                                   \
  75                   "i" (cr)                                      \
  76                 );                                              \
  77                 reg;                                            \
  78          })
  79
  80 /*
  81  * Machine Check Interrupt related structs & locations
  82  */
  83 struct mch_int_code {
  84         u8 sd:1,                /* System Damage */
  85            pd:1,                /* Instruction-processing damage */
  86            sr:1,                /* System recovery */
  87            _pad0:1,
  88            cd:1,                /* Timing-facility damage */
  89            ed:1,                /* External damage */
  90            _pad1:1,
  91            dg:1;                /* Degradation */
  92         u8 w:1,                 /* Warning */
  93            cp:1,                /* Channel report pending */
  94            sp:1,                /* Service-processor damage */
  95            ck:1,                /* Channel-subsystem damage */
  96            _pad2:2,
  97            b:1,                 /* Backed up */
  98            _pad3:1;
  99         u8 se:1,                /* Storage error uncorrected */
 100            sc:1,                /* Storage error corrected */
 101            ke:1,                /* Storage-key error uncorrected */
 102            ds:1,                /* Storage degradation */
 103            wp:1,                /* PSW-MWP validity */
 104            ms:1,                /* PSW mask and key validity */
 105            pm:1,                /* PSW program-mask and condition-code validity */
 106            ia:1;                /* PSW-instruction-address validity */
 107         u8 fa:1,                /* Failing-storage-address validity */
 108            _pad4:1,
 109            ec:1,                /* External-damage-code */
 110            fp:1,                /* Floating-point-register validity */
 111            gr:1,                /* General-register validity */
 112            cr:1,                /* Control-register validity */
 113            _pad5:1,
 114            st:1;                /* Storage logical validity */
 115         u8 ie:1,                /* Indirect storage error */
 116            ar:1,                /* Access-register validity */
 117            da:1,                /* Delayed-access exception */
 118            _pad6:5;
 119         u8 _pad7:2,
 120            pr:1,                /* TOD-programable-register validity */
 121            fc:1,                /* Floating-point-control-register validity */
 122            ap:1,                /* Ancilary report */
 123            _pad8:1,
 124            ct:1,                /* CPU-timer validity */
 125            cc:1;                /* Clock-comparator validity */
 126         u8 _pad9;
 127         u8 _pad10;
 128 } __attribute__((packed));
 129
 130 #define MCH_INT_OLD_PSW ((void*) 0x160)
 131 #define MCH_INT_NEW_PSW ((void*) 0x1e0)
 132 #define MCH_INT_CODE    ((struct mch_int_code*) 0xe8)
 133
 134 #endif