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Set blackbox file handler to NULL after closing file
[inav.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Inc / stm32h7xx_ll_rcc.h
blob65c28f7d4752b17ffcf6d4ea59508b968c6f53fb
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_rcc.h
4 * @author MCD Application Team
5 * @version $VERSION$
6 * @date $DATE$
7 * @brief Header file of RCC LL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
12 * All rights reserved.</center></h2>
13 *
14 * This software component is licensed by ST under BSD 3-Clause license,
15 * the "License"; You may not use this file except in compliance with the
16 * License. You may obtain a copy of the License at:
17 * opensource.org/licenses/BSD-3-Clause
18 *
19 ******************************************************************************
20 */
21
22 /* Define to prevent recursive inclusion -------------------------------------*/
23 #ifndef STM32H7xx_LL_RCC_H
24 #define STM32H7xx_LL_RCC_H
25
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29
30 /* Includes ------------------------------------------------------------------*/
31 #include "stm32h7xx.h"
32 #include <math.h>
33
34 /** @addtogroup STM32H7xx_LL_Driver
35 * @{
36 */
37
38 #if defined(RCC)
39
40 /** @defgroup RCC_LL RCC
41 * @{
42 */
43
44 /* Private types -------------------------------------------------------------*/
45 /* Private variables ---------------------------------------------------------*/
46 /** @defgroup RCC_LL_Private_Variables RCC Private Variables
47 * @{
48 */
49 extern const uint8_t LL_RCC_PrescTable[16];
50
51 /**
52 * @}
53 */
54 /* Private constants ---------------------------------------------------------*/
55 /* Private macros ------------------------------------------------------------*/
56 #if !defined(UNUSED)
57 #define UNUSED(x) ((void)(x))
58 #endif
59
60 /* 32 24 16 8 0
61 --------------------------------------------------------
62 | Mask | ClkSource | Bit | Register |
63 | | Config | Position | Offset |
64 --------------------------------------------------------*/
65
66 #if defined(RCC_VER_2_0)
67 /* Clock source register offset Vs CDCCIPR regsiter */
68 #define CDCCIP 0x0UL
69 #define CDCCIP1 0x4UL
70 #define CDCCIP2 0x8UL
71 #define SRDCCIP 0xCUL
72 #else
73 /* Clock source register offset Vs D1CCIPR regsiter */
74 #define D1CCIP 0x0UL
75 #define D2CCIP1 0x4UL
76 #define D2CCIP2 0x8UL
77 #define D3CCIP 0xCUL
78 #endif /* RCC_VER_2_0 */
79
80 #define LL_RCC_REG_SHIFT 0U
81 #define LL_RCC_POS_SHIFT 8U
82 #define LL_RCC_CONFIG_SHIFT 16U
83 #define LL_RCC_MASK_SHIFT 24U
84
85 #define LL_CLKSOURCE_SHIFT(__CLKSOURCE__) (((__CLKSOURCE__) >> LL_RCC_POS_SHIFT ) & 0x1FUL)
86
87 #define LL_CLKSOURCE_MASK(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_MASK_SHIFT ) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))
88
89 #define LL_CLKSOURCE_CONFIG(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_CONFIG_SHIFT) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))
90
91 #define LL_CLKSOURCE_REG(__CLKSOURCE__) (((__CLKSOURCE__) >> LL_RCC_REG_SHIFT ) & 0xFFUL)
92
93 #define LL_CLKSOURCE(__REG__, __MSK__, __POS__, __CLK__) ((uint32_t)((((__MSK__) >> (__POS__)) << LL_RCC_MASK_SHIFT) | \
94 (( __POS__ ) << LL_RCC_POS_SHIFT) | \
95 (( __REG__ ) << LL_RCC_REG_SHIFT) | \
96 (((__CLK__) >> (__POS__)) << LL_RCC_CONFIG_SHIFT)))
97
98 #if defined(USE_FULL_LL_DRIVER)
99 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
100 * @{
101 */
102 /**
103 * @}
104 */
105 #endif /*USE_FULL_LL_DRIVER*/
106 /* Exported types ------------------------------------------------------------*/
107 #if defined(USE_FULL_LL_DRIVER)
108 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
109 * @{
110 */
111
112 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
113 * @{
114 */
115
116 /**
117 * @brief RCC Clocks Frequency Structure
118 */
119 typedef struct
120 {
121 uint32_t SYSCLK_Frequency;
122 uint32_t CPUCLK_Frequency;
123 uint32_t HCLK_Frequency;
124 uint32_t PCLK1_Frequency;
125 uint32_t PCLK2_Frequency;
126 uint32_t PCLK3_Frequency;
127 uint32_t PCLK4_Frequency;
128 } LL_RCC_ClocksTypeDef;
129
130 /**
131 * @}
132 */
133
134 /**
135 * @brief PLL Clocks Frequency Structure
136 */
137 typedef struct
138 {
139 uint32_t PLL_P_Frequency;
140 uint32_t PLL_Q_Frequency;
141 uint32_t PLL_R_Frequency;
142 } LL_PLL_ClocksTypeDef;
143
144 /**
145 * @}
146 */
147
148 #endif /* USE_FULL_LL_DRIVER */
149
150 /* Exported constants --------------------------------------------------------*/
151 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
152 * @{
153 */
154
155 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
156 * @brief Defines used to adapt values of different oscillators
157 * @note These values could be modified in the user environment according to
158 * HW set-up.
159 * @{
160 */
161 #if !defined (HSE_VALUE)
162 #if defined(RCC_VER_X)
163 #define HSE_VALUE 25000000U /*!< Value of the HSE oscillator in Hz */
164 #else
165 #define HSE_VALUE 24000000U /*!< Value of the HSE oscillator in Hz */
166 #endif /* RCC_VER_X */
167 #endif /* HSE_VALUE */
168
169 #if !defined (HSI_VALUE)
170 #define HSI_VALUE 64000000U /*!< Value of the HSI oscillator in Hz */
171 #endif /* HSI_VALUE */
172
173 #if !defined (CSI_VALUE)
174 #define CSI_VALUE 4000000U /*!< Value of the CSI oscillator in Hz */
175 #endif /* CSI_VALUE */
176
177 #if !defined (LSE_VALUE)
178 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
179 #endif /* LSE_VALUE */
180
181 #if !defined (LSI_VALUE)
182 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
183 #endif /* LSI_VALUE */
184
185 #if !defined (EXTERNAL_CLOCK_VALUE)
186 #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */
187 #endif /* EXTERNAL_CLOCK_VALUE */
188
189 #if !defined (HSI48_VALUE)
190 #define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */
191 #endif /* HSI48_VALUE */
192
193 /**
194 * @}
195 */
196
197 /** @defgroup RCC_LL_EC_HSIDIV HSI oscillator divider
198 * @{
199 */
200 #define LL_RCC_HSI_DIV1 RCC_CR_HSIDIV_1
201 #define LL_RCC_HSI_DIV2 RCC_CR_HSIDIV_2
202 #define LL_RCC_HSI_DIV4 RCC_CR_HSIDIV_4
203 #define LL_RCC_HSI_DIV8 RCC_CR_HSIDIV_8
204 /**
205 * @}
206 */
207
208 /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
209 * @{
210 */
211 #define LL_RCC_LSEDRIVE_LOW (uint32_t)(0x00000000U)
212 #define LL_RCC_LSEDRIVE_MEDIUMLOW (uint32_t)(RCC_BDCR_LSEDRV_0)
213 #define LL_RCC_LSEDRIVE_MEDIUMHIGH (uint32_t)(RCC_BDCR_LSEDRV_1)
214 #define LL_RCC_LSEDRIVE_HIGH (uint32_t)(RCC_BDCR_LSEDRV)
215 /**
216 * @}
217 */
218
219 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
220 * @{
221 */
222 #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI
223 #define LL_RCC_SYS_CLKSOURCE_CSI RCC_CFGR_SW_CSI
224 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE
225 #define LL_RCC_SYS_CLKSOURCE_PLL1 RCC_CFGR_SW_PLL1
226 /**
227 * @}
228 */
229
230 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
231 * @{
232 */
233 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
234 #define LL_RCC_SYS_CLKSOURCE_STATUS_CSI RCC_CFGR_SWS_CSI /*!< CSI used as system clock */
235 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
236 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL1 RCC_CFGR_SWS_PLL1 /*!< PLL1 used as system clock */
237 /**
238 * @}
239 */
240
241 /** @defgroup RCC_LL_EC_SYSWAKEUP_CLKSOURCE System wakeup clock source
242 * @{
243 */
244 #define LL_RCC_SYSWAKEUP_CLKSOURCE_HSI (uint32_t)(0x00000000U)
245 #define LL_RCC_SYSWAKEUP_CLKSOURCE_CSI (uint32_t)(RCC_CFGR_STOPWUCK)
246 /**
247 * @}
248 */
249
250 /** @defgroup RCC_LL_EC_KERWAKEUP_CLKSOURCE Kernel wakeup clock source
251 * @{
252 */
253 #define LL_RCC_KERWAKEUP_CLKSOURCE_HSI (uint32_t)(0x00000000U)
254 #define LL_RCC_KERWAKEUP_CLKSOURCE_CSI (uint32_t)(RCC_CFGR_STOPKERWUCK)
255 /**
256 * @}
257 */
258
259 /** @defgroup RCC_LL_EC_SYSCLK_DIV System prescaler
260 * @{
261 */
262 #if defined(RCC_D1CFGR_D1CPRE_DIV1)
263 #define LL_RCC_SYSCLK_DIV_1 RCC_D1CFGR_D1CPRE_DIV1
264 #define LL_RCC_SYSCLK_DIV_2 RCC_D1CFGR_D1CPRE_DIV2
265 #define LL_RCC_SYSCLK_DIV_4 RCC_D1CFGR_D1CPRE_DIV4
266 #define LL_RCC_SYSCLK_DIV_8 RCC_D1CFGR_D1CPRE_DIV8
267 #define LL_RCC_SYSCLK_DIV_16 RCC_D1CFGR_D1CPRE_DIV16
268 #define LL_RCC_SYSCLK_DIV_64 RCC_D1CFGR_D1CPRE_DIV64
269 #define LL_RCC_SYSCLK_DIV_128 RCC_D1CFGR_D1CPRE_DIV128
270 #define LL_RCC_SYSCLK_DIV_256 RCC_D1CFGR_D1CPRE_DIV256
271 #define LL_RCC_SYSCLK_DIV_512 RCC_D1CFGR_D1CPRE_DIV512
272 #else
273 #define LL_RCC_SYSCLK_DIV_1 RCC_CDCFGR1_CDCPRE_DIV1
274 #define LL_RCC_SYSCLK_DIV_2 RCC_CDCFGR1_CDCPRE_DIV2
275 #define LL_RCC_SYSCLK_DIV_4 RCC_CDCFGR1_CDCPRE_DIV4
276 #define LL_RCC_SYSCLK_DIV_8 RCC_CDCFGR1_CDCPRE_DIV8
277 #define LL_RCC_SYSCLK_DIV_16 RCC_CDCFGR1_CDCPRE_DIV16
278 #define LL_RCC_SYSCLK_DIV_64 RCC_CDCFGR1_CDCPRE_DIV64
279 #define LL_RCC_SYSCLK_DIV_128 RCC_CDCFGR1_CDCPRE_DIV128
280 #define LL_RCC_SYSCLK_DIV_256 RCC_CDCFGR1_CDCPRE_DIV256
281 #define LL_RCC_SYSCLK_DIV_512 RCC_CDCFGR1_CDCPRE_DIV512
282 #endif /* RCC_D1CFGR_D1CPRE_DIV1 */
283 /**
284 * @}
285 */
286
287 /** @defgroup RCC_LL_EC_AHB_DIV AHB prescaler
288 * @{
289 */
290 #if defined(RCC_D1CFGR_HPRE_DIV1)
291 #define LL_RCC_AHB_DIV_1 RCC_D1CFGR_HPRE_DIV1
292 #define LL_RCC_AHB_DIV_2 RCC_D1CFGR_HPRE_DIV2
293 #define LL_RCC_AHB_DIV_4 RCC_D1CFGR_HPRE_DIV4
294 #define LL_RCC_AHB_DIV_8 RCC_D1CFGR_HPRE_DIV8
295 #define LL_RCC_AHB_DIV_16 RCC_D1CFGR_HPRE_DIV16
296 #define LL_RCC_AHB_DIV_64 RCC_D1CFGR_HPRE_DIV64
297 #define LL_RCC_AHB_DIV_128 RCC_D1CFGR_HPRE_DIV128
298 #define LL_RCC_AHB_DIV_256 RCC_D1CFGR_HPRE_DIV256
299 #define LL_RCC_AHB_DIV_512 RCC_D1CFGR_HPRE_DIV512
300 #else
301 #define LL_RCC_AHB_DIV_1 RCC_CDCFGR1_HPRE_DIV1
302 #define LL_RCC_AHB_DIV_2 RCC_CDCFGR1_HPRE_DIV2
303 #define LL_RCC_AHB_DIV_4 RCC_CDCFGR1_HPRE_DIV4
304 #define LL_RCC_AHB_DIV_8 RCC_CDCFGR1_HPRE_DIV8
305 #define LL_RCC_AHB_DIV_16 RCC_CDCFGR1_HPRE_DIV16
306 #define LL_RCC_AHB_DIV_64 RCC_CDCFGR1_HPRE_DIV64
307 #define LL_RCC_AHB_DIV_128 RCC_CDCFGR1_HPRE_DIV128
308 #define LL_RCC_AHB_DIV_256 RCC_CDCFGR1_HPRE_DIV256
309 #define LL_RCC_AHB_DIV_512 RCC_CDCFGR1_HPRE_DIV512
310 #endif /* RCC_D1CFGR_HPRE_DIV1 */
311 /**
312 * @}
313 */
314
315 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
316 * @{
317 */
318 #if defined(RCC_D2CFGR_D2PPRE1_DIV1)
319 #define LL_RCC_APB1_DIV_1 RCC_D2CFGR_D2PPRE1_DIV1
320 #define LL_RCC_APB1_DIV_2 RCC_D2CFGR_D2PPRE1_DIV2
321 #define LL_RCC_APB1_DIV_4 RCC_D2CFGR_D2PPRE1_DIV4
322 #define LL_RCC_APB1_DIV_8 RCC_D2CFGR_D2PPRE1_DIV8
323 #define LL_RCC_APB1_DIV_16 RCC_D2CFGR_D2PPRE1_DIV16
324 #else
325 #define LL_RCC_APB1_DIV_1 RCC_CDCFGR2_CDPPRE1_DIV1
326 #define LL_RCC_APB1_DIV_2 RCC_CDCFGR2_CDPPRE1_DIV2
327 #define LL_RCC_APB1_DIV_4 RCC_CDCFGR2_CDPPRE1_DIV4
328 #define LL_RCC_APB1_DIV_8 RCC_CDCFGR2_CDPPRE1_DIV8
329 #define LL_RCC_APB1_DIV_16 RCC_CDCFGR2_CDPPRE1_DIV16
330 #endif /* RCC_D2CFGR_D2PPRE1_DIV1 */
331 /**
332 * @}
333 */
334
335 /** @defgroup RCC_LL_EC_APB2_DIV APB low-speed prescaler (APB2)
336 * @{
337 */
338 #if defined(RCC_D2CFGR_D2PPRE2_DIV1)
339 #define LL_RCC_APB2_DIV_1 RCC_D2CFGR_D2PPRE2_DIV1
340 #define LL_RCC_APB2_DIV_2 RCC_D2CFGR_D2PPRE2_DIV2
341 #define LL_RCC_APB2_DIV_4 RCC_D2CFGR_D2PPRE2_DIV4
342 #define LL_RCC_APB2_DIV_8 RCC_D2CFGR_D2PPRE2_DIV8
343 #define LL_RCC_APB2_DIV_16 RCC_D2CFGR_D2PPRE2_DIV16
344 #else
345 #define LL_RCC_APB2_DIV_1 RCC_CDCFGR2_CDPPRE2_DIV1
346 #define LL_RCC_APB2_DIV_2 RCC_CDCFGR2_CDPPRE2_DIV2
347 #define LL_RCC_APB2_DIV_4 RCC_CDCFGR2_CDPPRE2_DIV4
348 #define LL_RCC_APB2_DIV_8 RCC_CDCFGR2_CDPPRE2_DIV8
349 #define LL_RCC_APB2_DIV_16 RCC_CDCFGR2_CDPPRE2_DIV16
350 #endif /* RCC_D2CFGR_D2PPRE2_DIV1 */
351 /**
352 * @}
353 */
354
355 /** @defgroup RCC_LL_EC_APB3_DIV APB low-speed prescaler (APB3)
356 * @{
357 */
358 #if defined(RCC_D1CFGR_D1PPRE_DIV1)
359 #define LL_RCC_APB3_DIV_1 RCC_D1CFGR_D1PPRE_DIV1
360 #define LL_RCC_APB3_DIV_2 RCC_D1CFGR_D1PPRE_DIV2
361 #define LL_RCC_APB3_DIV_4 RCC_D1CFGR_D1PPRE_DIV4
362 #define LL_RCC_APB3_DIV_8 RCC_D1CFGR_D1PPRE_DIV8
363 #define LL_RCC_APB3_DIV_16 RCC_D1CFGR_D1PPRE_DIV16
364 #else
365 #define LL_RCC_APB3_DIV_1 RCC_CDCFGR1_CDPPRE_DIV1
366 #define LL_RCC_APB3_DIV_2 RCC_CDCFGR1_CDPPRE_DIV2
367 #define LL_RCC_APB3_DIV_4 RCC_CDCFGR1_CDPPRE_DIV4
368 #define LL_RCC_APB3_DIV_8 RCC_CDCFGR1_CDPPRE_DIV8
369 #define LL_RCC_APB3_DIV_16 RCC_CDCFGR1_CDPPRE_DIV16
370 #endif /* RCC_D1CFGR_D1PPRE_DIV1 */
371 /**
372 * @}
373 */
374
375 /** @defgroup RCC_LL_EC_APB4_DIV APB low-speed prescaler (APB4)
376 * @{
377 */
378 #if defined(RCC_D3CFGR_D3PPRE_DIV1)
379 #define LL_RCC_APB4_DIV_1 RCC_D3CFGR_D3PPRE_DIV1
380 #define LL_RCC_APB4_DIV_2 RCC_D3CFGR_D3PPRE_DIV2
381 #define LL_RCC_APB4_DIV_4 RCC_D3CFGR_D3PPRE_DIV4
382 #define LL_RCC_APB4_DIV_8 RCC_D3CFGR_D3PPRE_DIV8
383 #define LL_RCC_APB4_DIV_16 RCC_D3CFGR_D3PPRE_DIV16
384 #else
385 #define LL_RCC_APB4_DIV_1 RCC_SRDCFGR_SRDPPRE_DIV1
386 #define LL_RCC_APB4_DIV_2 RCC_SRDCFGR_SRDPPRE_DIV2
387 #define LL_RCC_APB4_DIV_4 RCC_SRDCFGR_SRDPPRE_DIV4
388 #define LL_RCC_APB4_DIV_8 RCC_SRDCFGR_SRDPPRE_DIV8
389 #define LL_RCC_APB4_DIV_16 RCC_SRDCFGR_SRDPPRE_DIV16
390 #endif /* RCC_D3CFGR_D3PPRE_DIV1 */
391 /**
392 * @}
393 */
394
395 /** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection
396 * @{
397 */
398 #define LL_RCC_MCO1SOURCE_HSI (uint32_t)((RCC_CFGR_MCO1>>16U) | 0x00000000U)
399 #define LL_RCC_MCO1SOURCE_LSE (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_0)
400 #define LL_RCC_MCO1SOURCE_HSE (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_1)
401 #define LL_RCC_MCO1SOURCE_PLL1QCLK (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0)
402 #define LL_RCC_MCO1SOURCE_HSI48 (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_2)
403 #define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)((RCC_CFGR_MCO2>>16U) | 0x00000000U)
404 #define LL_RCC_MCO2SOURCE_PLL2PCLK (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_0)
405 #define LL_RCC_MCO2SOURCE_HSE (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_1)
406 #define LL_RCC_MCO2SOURCE_PLL1PCLK (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0)
407 #define LL_RCC_MCO2SOURCE_CSI (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_2)
408 #define LL_RCC_MCO2SOURCE_LSI (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_2|RCC_CFGR_MCO2_0)
409 /**
410 * @}
411 */
412
413 /** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler
414 * @{
415 */
416 #define LL_RCC_MCO1_DIV_1 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0)
417 #define LL_RCC_MCO1_DIV_2 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1)
418 #define LL_RCC_MCO1_DIV_3 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1)
419 #define LL_RCC_MCO1_DIV_4 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2)
420 #define LL_RCC_MCO1_DIV_5 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
421 #define LL_RCC_MCO1_DIV_6 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
422 #define LL_RCC_MCO1_DIV_7 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
423 #define LL_RCC_MCO1_DIV_8 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_3)
424 #define LL_RCC_MCO1_DIV_9 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3)
425 #define LL_RCC_MCO1_DIV_10 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
426 #define LL_RCC_MCO1_DIV_11 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
427 #define LL_RCC_MCO1_DIV_12 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
428 #define LL_RCC_MCO1_DIV_13 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
429 #define LL_RCC_MCO1_DIV_14 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
430 #define LL_RCC_MCO1_DIV_15 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE)
431 #define LL_RCC_MCO2_DIV_1 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0)
432 #define LL_RCC_MCO2_DIV_2 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1)
433 #define LL_RCC_MCO2_DIV_3 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1)
434 #define LL_RCC_MCO2_DIV_4 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2)
435 #define LL_RCC_MCO2_DIV_5 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_2)
436 #define LL_RCC_MCO2_DIV_6 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2)
437 #define LL_RCC_MCO2_DIV_7 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2)
438 #define LL_RCC_MCO2_DIV_8 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_3)
439 #define LL_RCC_MCO2_DIV_9 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_3)
440 #define LL_RCC_MCO2_DIV_10 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_3)
441 #define LL_RCC_MCO2_DIV_11 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_3)
442 #define LL_RCC_MCO2_DIV_12 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)
443 #define LL_RCC_MCO2_DIV_13 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)
444 #define LL_RCC_MCO2_DIV_14 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)
445 #define LL_RCC_MCO2_DIV_15 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE)
446
447 /**
448 * @}
449 */
450
451 /** @defgroup RCC_LL_EC_RTC_HSEDIV HSE prescaler for RTC clock
452 * @{
453 */
454 #define LL_RCC_RTC_NOCLOCK (uint32_t)(0x00000000U)
455 #define LL_RCC_RTC_HSE_DIV_2 (uint32_t)(RCC_CFGR_RTCPRE_1)
456 #define LL_RCC_RTC_HSE_DIV_3 (uint32_t)(RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
457 #define LL_RCC_RTC_HSE_DIV_4 (uint32_t)(RCC_CFGR_RTCPRE_2)
458 #define LL_RCC_RTC_HSE_DIV_5 (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
459 #define LL_RCC_RTC_HSE_DIV_6 (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
460 #define LL_RCC_RTC_HSE_DIV_7 (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
461 #define LL_RCC_RTC_HSE_DIV_8 (uint32_t)(RCC_CFGR_RTCPRE_3)
462 #define LL_RCC_RTC_HSE_DIV_9 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
463 #define LL_RCC_RTC_HSE_DIV_10 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
464 #define LL_RCC_RTC_HSE_DIV_11 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
465 #define LL_RCC_RTC_HSE_DIV_12 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
466 #define LL_RCC_RTC_HSE_DIV_13 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
467 #define LL_RCC_RTC_HSE_DIV_14 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
468 #define LL_RCC_RTC_HSE_DIV_15 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
469 #define LL_RCC_RTC_HSE_DIV_16 (uint32_t)(RCC_CFGR_RTCPRE_4)
470 #define LL_RCC_RTC_HSE_DIV_17 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0)
471 #define LL_RCC_RTC_HSE_DIV_18 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1)
472 #define LL_RCC_RTC_HSE_DIV_19 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
473 #define LL_RCC_RTC_HSE_DIV_20 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2)
474 #define LL_RCC_RTC_HSE_DIV_21 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
475 #define LL_RCC_RTC_HSE_DIV_22 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
476 #define LL_RCC_RTC_HSE_DIV_23 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
477 #define LL_RCC_RTC_HSE_DIV_24 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3)
478 #define LL_RCC_RTC_HSE_DIV_25 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
479 #define LL_RCC_RTC_HSE_DIV_26 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
480 #define LL_RCC_RTC_HSE_DIV_27 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
481 #define LL_RCC_RTC_HSE_DIV_28 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
482 #define LL_RCC_RTC_HSE_DIV_29 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
483 #define LL_RCC_RTC_HSE_DIV_30 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
484 #define LL_RCC_RTC_HSE_DIV_31 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
485 #define LL_RCC_RTC_HSE_DIV_32 (uint32_t)(RCC_CFGR_RTCPRE_5)
486 #define LL_RCC_RTC_HSE_DIV_33 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_0)
487 #define LL_RCC_RTC_HSE_DIV_34 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_1)
488 #define LL_RCC_RTC_HSE_DIV_35 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
489 #define LL_RCC_RTC_HSE_DIV_36 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2)
490 #define LL_RCC_RTC_HSE_DIV_37 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
491 #define LL_RCC_RTC_HSE_DIV_38 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
492 #define LL_RCC_RTC_HSE_DIV_39 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
493 #define LL_RCC_RTC_HSE_DIV_40 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3)
494 #define LL_RCC_RTC_HSE_DIV_41 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
495 #define LL_RCC_RTC_HSE_DIV_42 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
496 #define LL_RCC_RTC_HSE_DIV_43 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
497 #define LL_RCC_RTC_HSE_DIV_44 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
498 #define LL_RCC_RTC_HSE_DIV_45 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
499 #define LL_RCC_RTC_HSE_DIV_46 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
500 #define LL_RCC_RTC_HSE_DIV_47 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
501 #define LL_RCC_RTC_HSE_DIV_48 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4)
502 #define LL_RCC_RTC_HSE_DIV_49 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0)
503 #define LL_RCC_RTC_HSE_DIV_50 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1)
504 #define LL_RCC_RTC_HSE_DIV_51 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
505 #define LL_RCC_RTC_HSE_DIV_52 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2)
506 #define LL_RCC_RTC_HSE_DIV_53 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
507 #define LL_RCC_RTC_HSE_DIV_54 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
508 #define LL_RCC_RTC_HSE_DIV_55 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
509 #define LL_RCC_RTC_HSE_DIV_56 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3)
510 #define LL_RCC_RTC_HSE_DIV_57 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
511 #define LL_RCC_RTC_HSE_DIV_58 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
512 #define LL_RCC_RTC_HSE_DIV_59 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
513 #define LL_RCC_RTC_HSE_DIV_60 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
514 #define LL_RCC_RTC_HSE_DIV_61 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
515 #define LL_RCC_RTC_HSE_DIV_62 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
516 #define LL_RCC_RTC_HSE_DIV_63 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
517 /**
518 * @}
519 */
520
521 /** @defgroup RCC_LL_EC_USARTx_CLKSOURCE Peripheral USART clock source selection
522 * @{
523 */
524 #if defined(RCC_D2CCIP2R_USART16SEL)
525 #define LL_RCC_USART16_CLKSOURCE_PCLK2 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, 0x00000000U)
526 #define LL_RCC_USART16_CLKSOURCE_PLL2Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0)
527 #define LL_RCC_USART16_CLKSOURCE_PLL3Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_1)
528 #define LL_RCC_USART16_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_1)
529 #define LL_RCC_USART16_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_2)
530 #define LL_RCC_USART16_CLKSOURCE_LSE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2)
531 #else
532 #define LL_RCC_USART16910_CLKSOURCE_PCLK2 LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, 0x00000000U)
533 #define LL_RCC_USART16910_CLKSOURCE_PLL2Q LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0)
534 #define LL_RCC_USART16910_CLKSOURCE_PLL3Q LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_1)
535 #define LL_RCC_USART16910_CLKSOURCE_HSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_1)
536 #define LL_RCC_USART16910_CLKSOURCE_CSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_2)
537 #define LL_RCC_USART16910_CLKSOURCE_LSE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_2)
538 /* Aliases */
539 #define LL_RCC_USART16_CLKSOURCE_PCLK2 LL_RCC_USART16910_CLKSOURCE_PCLK2
540 #define LL_RCC_USART16_CLKSOURCE_PLL2Q LL_RCC_USART16910_CLKSOURCE_PLL2Q
541 #define LL_RCC_USART16_CLKSOURCE_PLL3Q LL_RCC_USART16910_CLKSOURCE_PLL3Q
542 #define LL_RCC_USART16_CLKSOURCE_HSI LL_RCC_USART16910_CLKSOURCE_HSI
543 #define LL_RCC_USART16_CLKSOURCE_CSI LL_RCC_USART16910_CLKSOURCE_CSI
544 #define LL_RCC_USART16_CLKSOURCE_LSE LL_RCC_USART16910_CLKSOURCE_LSE
545 #endif /* RCC_D2CCIP2R_USART16SEL */
546 #if defined(RCC_D2CCIP2R_USART28SEL)
547 #define LL_RCC_USART234578_CLKSOURCE_PCLK1 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, 0x00000000U)
548 #define LL_RCC_USART234578_CLKSOURCE_PLL2Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0)
549 #define LL_RCC_USART234578_CLKSOURCE_PLL3Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_1)
550 #define LL_RCC_USART234578_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)
551 #define LL_RCC_USART234578_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_2)
552 #define LL_RCC_USART234578_CLKSOURCE_LSE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)
553 #else
554 #define LL_RCC_USART234578_CLKSOURCE_PCLK1 LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, 0x00000000U)
555 #define LL_RCC_USART234578_CLKSOURCE_PLL2Q LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0)
556 #define LL_RCC_USART234578_CLKSOURCE_PLL3Q LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_1)
557 #define LL_RCC_USART234578_CLKSOURCE_HSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_1)
558 #define LL_RCC_USART234578_CLKSOURCE_CSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_2)
559 #define LL_RCC_USART234578_CLKSOURCE_LSE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_2)
560 #endif /* RCC_D2CCIP2R_USART28SEL */
561 /**
562 * @}
563 */
564
565 /** @defgroup RCC_LL_EC_LPUARTx_CLKSOURCE Peripheral LPUART clock source selection
566 * @{
567 */
568 #if defined(RCC_D3CCIPR_LPUART1SEL)
569 #define LL_RCC_LPUART1_CLKSOURCE_PCLK4 (0x00000000U)
570 #define LL_RCC_LPUART1_CLKSOURCE_PLL2Q (RCC_D3CCIPR_LPUART1SEL_0)
571 #define LL_RCC_LPUART1_CLKSOURCE_PLL3Q (RCC_D3CCIPR_LPUART1SEL_1)
572 #define LL_RCC_LPUART1_CLKSOURCE_HSI (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_1)
573 #define LL_RCC_LPUART1_CLKSOURCE_CSI (RCC_D3CCIPR_LPUART1SEL_2)
574 #define LL_RCC_LPUART1_CLKSOURCE_LSE (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_2)
575 #else
576 #define LL_RCC_LPUART1_CLKSOURCE_PCLK4 (0x00000000U)
577 #define LL_RCC_LPUART1_CLKSOURCE_PLL2Q (RCC_SRDCCIPR_LPUART1SEL_0)
578 #define LL_RCC_LPUART1_CLKSOURCE_PLL3Q (RCC_SRDCCIPR_LPUART1SEL_1)
579 #define LL_RCC_LPUART1_CLKSOURCE_HSI (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_1)
580 #define LL_RCC_LPUART1_CLKSOURCE_CSI (RCC_SRDCCIPR_LPUART1SEL_2)
581 #define LL_RCC_LPUART1_CLKSOURCE_LSE (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_2)
582 #endif /* RCC_D3CCIPR_LPUART1SEL */
583 /**
584 * @}
585 */
586
587 /** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE Peripheral I2C clock source selection
588 * @{
589 */
590 #if defined (RCC_D2CCIP2R_I2C123SEL)
591 #define LL_RCC_I2C123_CLKSOURCE_PCLK1 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, 0x00000000U)
592 #define LL_RCC_I2C123_CLKSOURCE_PLL3R LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_0)
593 #define LL_RCC_I2C123_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_1)
594 #define LL_RCC_I2C123_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1)
595 #else
596 #define LL_RCC_I2C123_CLKSOURCE_PCLK1 LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, 0x00000000U)
597 #define LL_RCC_I2C123_CLKSOURCE_PLL3R LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_0)
598 #define LL_RCC_I2C123_CLKSOURCE_HSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_1)
599 #define LL_RCC_I2C123_CLKSOURCE_CSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_0 | RCC_CDCCIP2R_I2C123SEL_1)
600 #endif /* RCC_D2CCIP2R_I2C123SEL */
601 #if defined (RCC_D3CCIPR_I2C4SEL)
602 #define LL_RCC_I2C4_CLKSOURCE_PCLK4 LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, 0x00000000U)
603 #define LL_RCC_I2C4_CLKSOURCE_PLL3R LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, RCC_D3CCIPR_I2C4SEL_0)
604 #define LL_RCC_I2C4_CLKSOURCE_HSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, RCC_D3CCIPR_I2C4SEL_1)
605 #define LL_RCC_I2C4_CLKSOURCE_CSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, RCC_D3CCIPR_I2C4SEL_0 | RCC_D3CCIPR_I2C4SEL_1)
606 #else
607 #define LL_RCC_I2C4_CLKSOURCE_PCLK4 LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, 0x00000000U)
608 #define LL_RCC_I2C4_CLKSOURCE_PLL3R LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, RCC_SRDCCIPR_I2C4SEL_0)
609 #define LL_RCC_I2C4_CLKSOURCE_HSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, RCC_SRDCCIPR_I2C4SEL_1)
610 #define LL_RCC_I2C4_CLKSOURCE_CSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, RCC_SRDCCIPR_I2C4SEL_0 | RCC_SRDCCIPR_I2C4SEL_1)
611 #endif /* RCC_D3CCIPR_I2C4SEL */
612 /**
613 * @}
614 */
615
616 /** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE Peripheral LPTIM clock source selection
617 * @{
618 */
619 #if defined(RCC_D2CCIP2R_LPTIM1SEL)
620 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, 0x00000000U)
621 #define LL_RCC_LPTIM1_CLKSOURCE_PLL2P LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_0)
622 #define LL_RCC_LPTIM1_CLKSOURCE_PLL3R LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_1)
623 #define LL_RCC_LPTIM1_CLKSOURCE_LSE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_1)
624 #define LL_RCC_LPTIM1_CLKSOURCE_LSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_2)
625 #define LL_RCC_LPTIM1_CLKSOURCE_CLKP LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_2)
626 #else
627 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, 0x00000000U)
628 #define LL_RCC_LPTIM1_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_0)
629 #define LL_RCC_LPTIM1_CLKSOURCE_PLL3R LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_1)
630 #define LL_RCC_LPTIM1_CLKSOURCE_LSE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_1)
631 #define LL_RCC_LPTIM1_CLKSOURCE_LSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_2)
632 #define LL_RCC_LPTIM1_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_2)
633 #endif /* RCC_D2CCIP2R_LPTIM1SEL */
634 #if defined(RCC_D3CCIPR_LPTIM2SEL)
635 #define LL_RCC_LPTIM2_CLKSOURCE_PCLK4 LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, 0x00000000U)
636 #define LL_RCC_LPTIM2_CLKSOURCE_PLL2P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_0)
637 #define LL_RCC_LPTIM2_CLKSOURCE_PLL3R LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_1)
638 #define LL_RCC_LPTIM2_CLKSOURCE_LSE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_1)
639 #define LL_RCC_LPTIM2_CLKSOURCE_LSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_2)
640 #define LL_RCC_LPTIM2_CLKSOURCE_CLKP LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_2)
641 #else
642 #define LL_RCC_LPTIM2_CLKSOURCE_PCLK4 LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, 0x00000000U)
643 #define LL_RCC_LPTIM2_CLKSOURCE_PLL2P LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_0)
644 #define LL_RCC_LPTIM2_CLKSOURCE_PLL3R LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_1)
645 #define LL_RCC_LPTIM2_CLKSOURCE_LSE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_1)
646 #define LL_RCC_LPTIM2_CLKSOURCE_LSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_2)
647 #define LL_RCC_LPTIM2_CLKSOURCE_CLKP LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_2)
648 #endif /* RCC_D3CCIPR_LPTIM2SEL */
649 #if defined(RCC_D3CCIPR_LPTIM345SEL)
650 #define LL_RCC_LPTIM345_CLKSOURCE_PCLK4 LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, 0x00000000U)
651 #define LL_RCC_LPTIM345_CLKSOURCE_PLL2P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0)
652 #define LL_RCC_LPTIM345_CLKSOURCE_PLL3R LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_1)
653 #define LL_RCC_LPTIM345_CLKSOURCE_LSE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1)
654 #define LL_RCC_LPTIM345_CLKSOURCE_LSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_2)
655 #define LL_RCC_LPTIM345_CLKSOURCE_CLKP LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2)
656 #else
657 #define LL_RCC_LPTIM345_CLKSOURCE_PCLK4 LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, 0x00000000U)
658 #define LL_RCC_LPTIM345_CLKSOURCE_PLL2P LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0)
659 #define LL_RCC_LPTIM345_CLKSOURCE_PLL3R LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_1)
660 #define LL_RCC_LPTIM345_CLKSOURCE_LSE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_1)
661 #define LL_RCC_LPTIM345_CLKSOURCE_LSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_2)
662 #define LL_RCC_LPTIM345_CLKSOURCE_CLKP LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_2)
663 /* aliases*/
664 #define LL_RCC_LPTIM3_CLKSOURCE_PCLK4 LL_RCC_LPTIM345_CLKSOURCE_PCLK4
665 #define LL_RCC_LPTIM3_CLKSOURCE_PLL2P LL_RCC_LPTIM345_CLKSOURCE_PLL2P
666 #define LL_RCC_LPTIM3_CLKSOURCE_PLL3R LL_RCC_LPTIM345_CLKSOURCE_PLL3R
667 #define LL_RCC_LPTIM3_CLKSOURCE_LSE LL_RCC_LPTIM345_CLKSOURCE_LSE
668 #define LL_RCC_LPTIM3_CLKSOURCE_LSI LL_RCC_LPTIM345_CLKSOURCE_LSI
669 #define LL_RCC_LPTIM3_CLKSOURCE_CLKP LL_RCC_LPTIM345_CLKSOURCE_CLKP
670 #endif /* RCC_D3CCIPR_LPTIM345SEL */
671 /**
672 * @}
673 */
674
675 /** @defgroup RCC_LL_EC_SAIx_CLKSOURCE Peripheral SAI clock source selection
676 * @{
677 */
678 #if defined(RCC_D2CCIP1R_SAI1SEL)
679 #define LL_RCC_SAI1_CLKSOURCE_PLL1Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, 0x00000000U)
680 #define LL_RCC_SAI1_CLKSOURCE_PLL2P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, RCC_D2CCIP1R_SAI1SEL_0)
681 #define LL_RCC_SAI1_CLKSOURCE_PLL3P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, RCC_D2CCIP1R_SAI1SEL_1)
682 #define LL_RCC_SAI1_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, RCC_D2CCIP1R_SAI1SEL_0 | RCC_D2CCIP1R_SAI1SEL_1)
683 #define LL_RCC_SAI1_CLKSOURCE_CLKP LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, RCC_D2CCIP1R_SAI1SEL_2)
684 #else
685 #define LL_RCC_SAI1_CLKSOURCE_PLL1Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, 0x00000000U)
686 #define LL_RCC_SAI1_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, RCC_CDCCIP1R_SAI1SEL_0)
687 #define LL_RCC_SAI1_CLKSOURCE_PLL3P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, RCC_CDCCIP1R_SAI1SEL_1)
688 #define LL_RCC_SAI1_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, RCC_CDCCIP1R_SAI1SEL_0 | RCC_CDCCIP1R_SAI1SEL_1)
689 #define LL_RCC_SAI1_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, RCC_CDCCIP1R_SAI1SEL_2)
690 #endif
691 #if defined(SAI3)
692 #define LL_RCC_SAI23_CLKSOURCE_PLL1Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, 0x00000000U)
693 #define LL_RCC_SAI23_CLKSOURCE_PLL2P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_0)
694 #define LL_RCC_SAI23_CLKSOURCE_PLL3P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_1)
695 #define LL_RCC_SAI23_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1)
696 #define LL_RCC_SAI23_CLKSOURCE_CLKP LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_2)
697 #endif /* SAI3 */
698 #if defined(RCC_CDCCIP1R_SAI2ASEL)
699 #define LL_RCC_SAI2A_CLKSOURCE_PLL1Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, 0x00000000U)
700 #define LL_RCC_SAI2A_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_0)
701 #define LL_RCC_SAI2A_CLKSOURCE_PLL3P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_1)
702 #define LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_1)
703 #define LL_RCC_SAI2A_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_2)
704 #define LL_RCC_SAI2A_CLKSOURCE_SPDIF LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_2)
705 #endif /* RCC_CDCCIP1R_SAI2ASEL */
706 #if defined(RCC_CDCCIP1R_SAI2BSEL)
707 #define LL_RCC_SAI2B_CLKSOURCE_PLL1Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, 0x00000000U)
708 #define LL_RCC_SAI2B_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_0)
709 #define LL_RCC_SAI2B_CLKSOURCE_PLL3P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_1)
710 #define LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_1)
711 #define LL_RCC_SAI2B_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_2)
712 #define LL_RCC_SAI2B_CLKSOURCE_SPDIF LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_2)
713 #endif /* RCC_CDCCIP1R_SAI2BSEL */
714 #if defined(SAI4_Block_A)
715 #define LL_RCC_SAI4A_CLKSOURCE_PLL1Q LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, 0x00000000U)
716 #define LL_RCC_SAI4A_CLKSOURCE_PLL2P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_0)
717 #define LL_RCC_SAI4A_CLKSOURCE_PLL3P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_1)
718 #define LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1)
719 #define LL_RCC_SAI4A_CLKSOURCE_CLKP LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_2)
720 #endif /* SAI4_Block_A */
721 #if defined(SAI4_Block_B)
722 #define LL_RCC_SAI4B_CLKSOURCE_PLL1Q LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, 0x00000000U)
723 #define LL_RCC_SAI4B_CLKSOURCE_PLL2P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_0)
724 #define LL_RCC_SAI4B_CLKSOURCE_PLL3P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_1)
725 #define LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1)
726 #define LL_RCC_SAI4B_CLKSOURCE_CLKP LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_2)
727 #endif /* SAI4_Block_B */
728 /**
729 * @}
730 */
731
732 /** @defgroup RCC_LL_EC_SDMMC_CLKSOURCE Peripheral SDMMC clock source selection
733 * @{
734 */
735 #if defined(RCC_D1CCIPR_SDMMCSEL)
736 #define LL_RCC_SDMMC_CLKSOURCE_PLL1Q (0x00000000U)
737 #define LL_RCC_SDMMC_CLKSOURCE_PLL2R (RCC_D1CCIPR_SDMMCSEL)
738 #else
739 #define LL_RCC_SDMMC_CLKSOURCE_PLL1Q (0x00000000U)
740 #define LL_RCC_SDMMC_CLKSOURCE_PLL2R (RCC_CDCCIPR_SDMMCSEL)
741 #endif /* RCC_D1CCIPR_SDMMCSEL */
742 /**
743 * @}
744 */
745
746 /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
747 * @{
748 */
749 #if defined(RCC_D2CCIP2R_RNGSEL)
750 #define LL_RCC_RNG_CLKSOURCE_HSI48 (0x00000000U)
751 #define LL_RCC_RNG_CLKSOURCE_PLL1Q (RCC_D2CCIP2R_RNGSEL_0)
752 #define LL_RCC_RNG_CLKSOURCE_LSE (RCC_D2CCIP2R_RNGSEL_1)
753 #define LL_RCC_RNG_CLKSOURCE_LSI (RCC_D2CCIP2R_RNGSEL_1 | RCC_D2CCIP2R_RNGSEL_0)
754 #else
755 #define LL_RCC_RNG_CLKSOURCE_HSI48 (0x00000000U)
756 #define LL_RCC_RNG_CLKSOURCE_PLL1Q (RCC_CDCCIP2R_RNGSEL_0)
757 #define LL_RCC_RNG_CLKSOURCE_LSE (RCC_CDCCIP2R_RNGSEL_1)
758 #define LL_RCC_RNG_CLKSOURCE_LSI (RCC_CDCCIP2R_RNGSEL_1 | RCC_CDCCIP2R_RNGSEL_0)
759 #endif /* RCC_D2CCIP2R_RNGSEL */
760 /**
761 * @}
762 */
763
764 /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
765 * @{
766 */
767 #if defined(RCC_D2CCIP2R_USBSEL)
768 #define LL_RCC_USB_CLKSOURCE_DISABLE (0x00000000U)
769 #define LL_RCC_USB_CLKSOURCE_PLL1Q (RCC_D2CCIP2R_USBSEL_0)
770 #define LL_RCC_USB_CLKSOURCE_PLL3Q (RCC_D2CCIP2R_USBSEL_1)
771 #define LL_RCC_USB_CLKSOURCE_HSI48 (RCC_D2CCIP2R_USBSEL_1 | RCC_D2CCIP2R_USBSEL_0)
772 #else
773 #define LL_RCC_USB_CLKSOURCE_DISABLE (0x00000000U)
774 #define LL_RCC_USB_CLKSOURCE_PLL1Q (RCC_CDCCIP2R_USBSEL_0)
775 #define LL_RCC_USB_CLKSOURCE_PLL3Q (RCC_CDCCIP2R_USBSEL_1)
776 #define LL_RCC_USB_CLKSOURCE_HSI48 (RCC_CDCCIP2R_USBSEL_1 | RCC_CDCCIP2R_USBSEL_0)
777 #endif /* RCC_D2CCIP2R_USBSEL */
778 /**
779 * @}
780 */
781
782 /** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection
783 * @{
784 */
785 #if defined(RCC_D2CCIP2R_CECSEL)
786 #define LL_RCC_CEC_CLKSOURCE_LSE (0x00000000U)
787 #define LL_RCC_CEC_CLKSOURCE_LSI (RCC_D2CCIP2R_CECSEL_0)
788 #define LL_RCC_CEC_CLKSOURCE_CSI_DIV122 (RCC_D2CCIP2R_CECSEL_1)
789 #else
790 #define LL_RCC_CEC_CLKSOURCE_LSE (0x00000000U)
791 #define LL_RCC_CEC_CLKSOURCE_LSI (RCC_CDCCIP2R_CECSEL_0)
792 #define LL_RCC_CEC_CLKSOURCE_CSI_DIV122 (RCC_CDCCIP2R_CECSEL_1)
793 #endif
794 /**
795 * @}
796 */
797
798 #if defined(DSI)
799 /** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection
800 * @{
801 */
802 #define LL_RCC_DSI_CLKSOURCE_PHY (0x00000000U)
803 #define LL_RCC_DSI_CLKSOURCE_PLL2Q (RCC_D1CCIPR_DSISEL)
804 /**
805 * @}
806 */
807 #endif /* DSI */
808
809 /** @defgroup RCC_LL_EC_DFSDM_CLKSOURCE Peripheral DFSDM clock source selection
810 * @{
811 */
812 #if defined(RCC_D2CCIP1R_DFSDM1SEL)
813 #define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 (0x00000000U)
814 #define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK (RCC_D2CCIP1R_DFSDM1SEL)
815 #else
816 #define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 (0x00000000U)
817 #define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK (RCC_CDCCIP1R_DFSDM1SEL)
818 #endif /* RCC_D2CCIP1R_DFSDM1SEL */
819 /**
820 * @}
821 */
822
823 #if defined(DFSDM2_BASE)
824 /** @defgroup RCC_LL_EC_DFSDM2_CLKSOURCE Peripheral DFSDM2 clock source selection
825 * @{
826 */
827 #define LL_RCC_DFSDM2_CLKSOURCE_PCLK4 (0x00000000U)
828 #define LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (RCC_SRDCCIPR_DFSDM2SEL)
829 /**
830 * @}
831 */
832 #endif /* DFSDM2_BASE */
833
834 /** @defgroup RCC_LL_EC_FMC_CLKSOURCE Peripheral FMC clock source selection
835 * @{
836 */
837 #if defined(RCC_D1CCIPR_FMCSEL)
838 #define LL_RCC_FMC_CLKSOURCE_HCLK (0x00000000U)
839 #define LL_RCC_FMC_CLKSOURCE_PLL1Q (RCC_D1CCIPR_FMCSEL_0)
840 #define LL_RCC_FMC_CLKSOURCE_PLL2R (RCC_D1CCIPR_FMCSEL_1)
841 #define LL_RCC_FMC_CLKSOURCE_CLKP (RCC_D1CCIPR_FMCSEL_0 | RCC_D1CCIPR_FMCSEL_1)
842 #else
843 #define LL_RCC_FMC_CLKSOURCE_HCLK (0x00000000U)
844 #define LL_RCC_FMC_CLKSOURCE_PLL1Q (RCC_CDCCIPR_FMCSEL_0)
845 #define LL_RCC_FMC_CLKSOURCE_PLL2R (RCC_CDCCIPR_FMCSEL_1)
846 #define LL_RCC_FMC_CLKSOURCE_CLKP (RCC_CDCCIPR_FMCSEL_0 | RCC_CDCCIPR_FMCSEL_1)
847 #endif /* RCC_D1CCIPR_FMCSEL */
848 /**
849 * @}
850 */
851
852 #if defined(QUADSPI)
853 /** @defgroup RCC_LL_EC_QSPI_CLKSOURCE Peripheral QSPI clock source selection
854 * @{
855 */
856 #define LL_RCC_QSPI_CLKSOURCE_HCLK (0x00000000U)
857 #define LL_RCC_QSPI_CLKSOURCE_PLL1Q (RCC_D1CCIPR_QSPISEL_0)
858 #define LL_RCC_QSPI_CLKSOURCE_PLL2R (RCC_D1CCIPR_QSPISEL_1)
859 #define LL_RCC_QSPI_CLKSOURCE_CLKP (RCC_D1CCIPR_QSPISEL_0 | RCC_D1CCIPR_QSPISEL_1)
860 /**
861 * @}
862 */
863 #endif /* QUADSPI */
864
865
866 #if defined(OCTOSPI1) || defined(OCTOSPI2)
867 /** @defgroup RCC_LL_EC_OSPI_CLKSOURCE Peripheral OSPI clock source selection
868 * @{
869 */
870 #define LL_RCC_OSPI_CLKSOURCE_HCLK (0x00000000U)
871 #define LL_RCC_OSPI_CLKSOURCE_PLL1Q (RCC_CDCCIPR_OCTOSPISEL_0)
872 #define LL_RCC_OSPI_CLKSOURCE_PLL2R (RCC_CDCCIPR_OCTOSPISEL_1)
873 #define LL_RCC_OSPI_CLKSOURCE_CLKP (RCC_CDCCIPR_OCTOSPISEL_0 | RCC_CDCCIPR_OCTOSPISEL_1)
874 /**
875 * @}
876 */
877 #endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
878
879
880 /** @defgroup RCC_LL_EC_CLKP_CLKSOURCE Peripheral CLKP clock source selection
881 * @{
882 */
883 #if defined(RCC_D1CCIPR_CKPERSEL)
884 #define LL_RCC_CLKP_CLKSOURCE_HSI (0x00000000U)
885 #define LL_RCC_CLKP_CLKSOURCE_CSI (RCC_D1CCIPR_CKPERSEL_0)
886 #define LL_RCC_CLKP_CLKSOURCE_HSE (RCC_D1CCIPR_CKPERSEL_1)
887 #else
888 #define LL_RCC_CLKP_CLKSOURCE_HSI (0x00000000U)
889 #define LL_RCC_CLKP_CLKSOURCE_CSI (RCC_CDCCIPR_CKPERSEL_0)
890 #define LL_RCC_CLKP_CLKSOURCE_HSE (RCC_CDCCIPR_CKPERSEL_1)
891 #endif /* RCC_D1CCIPR_CKPERSEL */
892 /**
893 * @}
894 */
895
896 /** @defgroup RCC_LL_EC_SPIx_CLKSOURCE Peripheral SPI clock source selection
897 * @{
898 */
899 #if defined(RCC_D2CCIP1R_SPI123SEL)
900 #define LL_RCC_SPI123_CLKSOURCE_PLL1Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, 0x00000000U)
901 #define LL_RCC_SPI123_CLKSOURCE_PLL2P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_0)
902 #define LL_RCC_SPI123_CLKSOURCE_PLL3P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_1)
903 #define LL_RCC_SPI123_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1)
904 #define LL_RCC_SPI123_CLKSOURCE_CLKP LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_2)
905 #else
906 #define LL_RCC_SPI123_CLKSOURCE_PLL1Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, 0x00000000U)
907 #define LL_RCC_SPI123_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_0)
908 #define LL_RCC_SPI123_CLKSOURCE_PLL3P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_1)
909 #define LL_RCC_SPI123_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_0 | RCC_CDCCIP1R_SPI123SEL_1)
910 #define LL_RCC_SPI123_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_2)
911 #endif /* RCC_D2CCIP1R_SPI123SEL */
912 #if defined(RCC_D2CCIP1R_SPI45SEL)
913 #define LL_RCC_SPI45_CLKSOURCE_PCLK2 LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, 0x00000000U)
914 #define LL_RCC_SPI45_CLKSOURCE_PLL2Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_0)
915 #define LL_RCC_SPI45_CLKSOURCE_PLL3Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_1)
916 #define LL_RCC_SPI45_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1)
917 #define LL_RCC_SPI45_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_2)
918 #define LL_RCC_SPI45_CLKSOURCE_HSE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2)
919 #else
920 #define LL_RCC_SPI45_CLKSOURCE_PCLK2 LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, 0x00000000U)
921 #define LL_RCC_SPI45_CLKSOURCE_PLL2Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_0)
922 #define LL_RCC_SPI45_CLKSOURCE_PLL3Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_1)
923 #define LL_RCC_SPI45_CLKSOURCE_HSI LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_1)
924 #define LL_RCC_SPI45_CLKSOURCE_CSI LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_2)
925 #define LL_RCC_SPI45_CLKSOURCE_HSE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_2)
926 #endif /* (RCC_D2CCIP1R_SPI45SEL */
927 #if defined(RCC_D3CCIPR_SPI6SEL)
928 #define LL_RCC_SPI6_CLKSOURCE_PCLK4 LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, 0x00000000U)
929 #define LL_RCC_SPI6_CLKSOURCE_PLL2Q LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_0)
930 #define LL_RCC_SPI6_CLKSOURCE_PLL3Q LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_1)
931 #define LL_RCC_SPI6_CLKSOURCE_HSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_1)
932 #define LL_RCC_SPI6_CLKSOURCE_CSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_2)
933 #define LL_RCC_SPI6_CLKSOURCE_HSE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_2)
934 #else
935 #define LL_RCC_SPI6_CLKSOURCE_PCLK4 LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, 0x00000000U)
936 #define LL_RCC_SPI6_CLKSOURCE_PLL2Q LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_0)
937 #define LL_RCC_SPI6_CLKSOURCE_PLL3Q LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_1)
938 #define LL_RCC_SPI6_CLKSOURCE_HSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_1)
939 #define LL_RCC_SPI6_CLKSOURCE_CSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_2)
940 #define LL_RCC_SPI6_CLKSOURCE_HSE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_2)
941 #define LL_RCC_SPI6_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_1 | RCC_SRDCCIPR_SPI6SEL_2)
942 #endif /* RCC_D3CCIPR_SPI6SEL */
943 /**
944 * @}
945 */
946
947 /** @defgroup RCC_LL_EC_SPDIF_CLKSOURCE Peripheral SPDIF clock source selection
948 * @{
949 */
950 #if defined(RCC_D2CCIP1R_SPDIFSEL)
951 #define LL_RCC_SPDIF_CLKSOURCE_PLL1Q (0x00000000U)
952 #define LL_RCC_SPDIF_CLKSOURCE_PLL2R (RCC_D2CCIP1R_SPDIFSEL_0)
953 #define LL_RCC_SPDIF_CLKSOURCE_PLL3R (RCC_D2CCIP1R_SPDIFSEL_1)
954 #define LL_RCC_SPDIF_CLKSOURCE_HSI (RCC_D2CCIP1R_SPDIFSEL_0 | RCC_D2CCIP1R_SPDIFSEL_1)
955 #else
956 #define LL_RCC_SPDIF_CLKSOURCE_PLL1Q (0x00000000U)
957 #define LL_RCC_SPDIF_CLKSOURCE_PLL2R (RCC_CDCCIP1R_SPDIFSEL_0)
958 #define LL_RCC_SPDIF_CLKSOURCE_PLL3R (RCC_CDCCIP1R_SPDIFSEL_1)
959 #define LL_RCC_SPDIF_CLKSOURCE_HSI (RCC_CDCCIP1R_SPDIFSEL_0 | RCC_CDCCIP1R_SPDIFSEL_1)
960 #endif /* RCC_D2CCIP1R_SPDIFSEL */
961 /**
962 * @}
963 */
964
965 #if defined(FDCAN1) || defined(FDCAN2)
966 /** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE Peripheral FDCAN clock source selection
967 * @{
968 */
969 #if defined(RCC_D2CCIP1R_FDCANSEL)
970 #define LL_RCC_FDCAN_CLKSOURCE_HSE (0x00000000U)
971 #define LL_RCC_FDCAN_CLKSOURCE_PLL1Q (RCC_D2CCIP1R_FDCANSEL_0)
972 #define LL_RCC_FDCAN_CLKSOURCE_PLL2Q (RCC_D2CCIP1R_FDCANSEL_1)
973 #else
974 #define LL_RCC_FDCAN_CLKSOURCE_HSE (0x00000000U)
975 #define LL_RCC_FDCAN_CLKSOURCE_PLL1Q (RCC_CDCCIP1R_FDCANSEL_0)
976 #define LL_RCC_FDCAN_CLKSOURCE_PLL2Q (RCC_CDCCIP1R_FDCANSEL_1)
977 #endif /* RCC_D2CCIP1R_FDCANSEL */
978 /**
979 * @}
980 */
981 #endif /*FDCAN1 || FDCAN2*/
982
983 /** @defgroup RCC_LL_EC_SWP_CLKSOURCE Peripheral SWP clock source selection
984 * @{
985 */
986 #if defined(RCC_D2CCIP1R_SWPSEL)
987 #define LL_RCC_SWP_CLKSOURCE_PCLK1 (0x00000000U)
988 #define LL_RCC_SWP_CLKSOURCE_HSI (RCC_D2CCIP1R_SWPSEL)
989 #else
990 #define LL_RCC_SWP_CLKSOURCE_PCLK1 (0x00000000U)
991 #define LL_RCC_SWP_CLKSOURCE_HSI (RCC_CDCCIP1R_SWPSEL)
992 #endif /* RCC_D2CCIP1R_SWPSEL */
993 /**
994 * @}
995 */
996
997 /** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection
998 * @{
999 */
1000 #if defined(RCC_D3CCIPR_ADCSEL)
1001 #define LL_RCC_ADC_CLKSOURCE_PLL2P (0x00000000U)
1002 #define LL_RCC_ADC_CLKSOURCE_PLL3R (RCC_D3CCIPR_ADCSEL_0)
1003 #define LL_RCC_ADC_CLKSOURCE_CLKP (RCC_D3CCIPR_ADCSEL_1)
1004 #else
1005 #define LL_RCC_ADC_CLKSOURCE_PLL2P (0x00000000U)
1006 #define LL_RCC_ADC_CLKSOURCE_PLL3R (RCC_SRDCCIPR_ADCSEL_0)
1007 #define LL_RCC_ADC_CLKSOURCE_CLKP (RCC_SRDCCIPR_ADCSEL_1)
1008 #endif /* RCC_D3CCIPR_ADCSEL */
1009 /**
1010 * @}
1011 */
1012
1013 /** @defgroup RCC_LL_EC_USARTx_CLKSOURCE Peripheral USART get clock source
1014 * @{
1015 */
1016 #if defined (RCC_D2CCIP2R_USART16SEL)
1017 #define LL_RCC_USART16_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, 0x00000000U)
1018 #else
1019 #define LL_RCC_USART16_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, 0x00000000U)
1020 /* alias*/
1021 #define LL_RCC_USART16910_CLKSOURCE LL_RCC_USART16_CLKSOURCE
1022 #endif /* RCC_D2CCIP2R_USART16SEL */
1023 #if defined (RCC_D2CCIP2R_USART28SEL)
1024 #define LL_RCC_USART234578_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, 0x00000000U)
1025 #else
1026 #define LL_RCC_USART234578_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, 0x00000000U)
1027 #endif /* RCC_D2CCIP2R_USART28SEL */
1028 /**
1029 * @}
1030 */
1031
1032 /** @defgroup RCC_LL_EC_LPUARTx_CLKSOURCE Peripheral LPUART get clock source
1033 * @{
1034 */
1035 #if defined(RCC_D3CCIPR_LPUART1SEL)
1036 #define LL_RCC_LPUART1_CLKSOURCE RCC_D3CCIPR_LPUART1SEL
1037 #else
1038 #define LL_RCC_LPUART1_CLKSOURCE RCC_SRDCCIPR_LPUART1SEL
1039 #endif /* RCC_D3CCIPR_LPUART1SEL */
1040 /**
1041 * @}
1042 */
1043
1044 /** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE Peripheral I2C get clock source
1045 * @{
1046 */
1047 #if defined(RCC_D2CCIP2R_I2C123SEL)
1048 #define LL_RCC_I2C123_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, 0x00000000U)
1049 #else
1050 #define LL_RCC_I2C123_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, 0x00000000U)
1051 #endif /* RCC_D2CCIP2R_I2C123SEL */
1052 #if defined(RCC_D3CCIPR_I2C4SEL)
1053 #define LL_RCC_I2C4_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, 0x00000000U)
1054 #else
1055 #define LL_RCC_I2C4_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, 0x00000000U)
1056 #endif /* RCC_D3CCIPR_I2C4SEL */
1057 /**
1058 * @}
1059 */
1060
1061 /** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE Peripheral LPTIM get clock source
1062 * @{
1063 */
1064 #if defined(RCC_D2CCIP2R_LPTIM1SEL)
1065 #define LL_RCC_LPTIM1_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, 0x00000000U)
1066 #else
1067 #define LL_RCC_LPTIM1_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, 0x00000000U)
1068 #endif /* RCC_D2CCIP2R_LPTIM1SEL) */
1069 #if defined(RCC_D3CCIPR_LPTIM2SEL)
1070 #define LL_RCC_LPTIM2_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, 0x00000000U)
1071 #else
1072 #define LL_RCC_LPTIM2_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, 0x00000000U)
1073 #endif /* RCC_D3CCIPR_LPTIM2SEL */
1074 #if defined(RCC_D3CCIPR_LPTIM345SEL)
1075 #define LL_RCC_LPTIM345_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, 0x00000000U)
1076 #else
1077 #define LL_RCC_LPTIM345_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, 0x00000000U)
1078 #define LL_RCC_LPTIM3_CLKSOURCE LL_RCC_LPTIM345_CLKSOURCE /* alias */
1079 #endif /* RCC_D3CCIPR_LPTIM345SEL */
1080 /**
1081 * @}
1082 */
1083
1084 /** @defgroup RCC_LL_EC_SAIx_CLKSOURCE Peripheral SAI get clock source
1085 * @{
1086 */
1087 #if defined(RCC_D2CCIP1R_SAI1SEL)
1088 #define LL_RCC_SAI1_CLKSOURCE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, 0x00000000U)
1089 #else
1090 #define LL_RCC_SAI1_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, 0x00000000U)
1091 #endif /* RCC_D2CCIP1R_SAI1SEL */
1092 #if defined(RCC_D2CCIP1R_SAI23SEL)
1093 #define LL_RCC_SAI23_CLKSOURCE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, 0x00000000U)
1094 #endif /* RCC_D2CCIP1R_SAI23SEL */
1095 #if defined(RCC_CDCCIP1R_SAI2ASEL)
1096 #define LL_RCC_SAI2A_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, 0x00000000U)
1097 #endif /* RCC_CDCCIP1R_SAI2ASEL */
1098 #if defined(RCC_CDCCIP1R_SAI2BSEL)
1099 #define LL_RCC_SAI2B_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, 0x00000000U)
1100 #endif /* RCC_CDCCIP1R_SAI2BSEL */
1101 #if defined(RCC_D3CCIPR_SAI4ASEL)
1102 #define LL_RCC_SAI4A_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, 0x00000000U)
1103 #endif /* RCC_D3CCIPR_SAI4ASEL */
1104 #if defined(RCC_D3CCIPR_SAI4BSEL)
1105 #define LL_RCC_SAI4B_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, 0x00000000U)
1106 #endif /* RCC_D3CCIPR_SAI4BSEL */
1107 /**
1108 * @}
1109 */
1110
1111 /** @defgroup RCC_LL_EC_SDMMC_CLKSOURCE Peripheral SDMMC get clock source
1112 * @{
1113 */
1114 #if defined(RCC_D1CCIPR_SDMMCSEL)
1115 #define LL_RCC_SDMMC_CLKSOURCE RCC_D1CCIPR_SDMMCSEL
1116 #else
1117 #define LL_RCC_SDMMC_CLKSOURCE RCC_CDCCIPR_SDMMCSEL
1118 #endif /* RCC_D1CCIPR_SDMMCSEL */
1119 /**
1120 * @}
1121 */
1122
1123 /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG get clock source
1124 * @{
1125 */
1126 #if (RCC_D2CCIP2R_RNGSEL)
1127 #define LL_RCC_RNG_CLKSOURCE RCC_D2CCIP2R_RNGSEL
1128 #else
1129 #define LL_RCC_RNG_CLKSOURCE RCC_CDCCIP2R_RNGSEL
1130 #endif /* RCC_D2CCIP2R_RNGSEL */
1131 /**
1132 * @}
1133 */
1134
1135 /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB get clock source
1136 * @{
1137 */
1138 #if (RCC_D2CCIP2R_USBSEL)
1139 #define LL_RCC_USB_CLKSOURCE RCC_D2CCIP2R_USBSEL
1140 #else
1141 #define LL_RCC_USB_CLKSOURCE RCC_CDCCIP2R_USBSEL
1142 #endif /* RCC_D2CCIP2R_USBSEL */
1143 /**
1144 * @}
1145 */
1146
1147 /** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC get clock source
1148 * @{
1149 */
1150 #if (RCC_D2CCIP2R_CECSEL)
1151 #define LL_RCC_CEC_CLKSOURCE RCC_D2CCIP2R_CECSEL
1152 #else
1153 #define LL_RCC_CEC_CLKSOURCE RCC_CDCCIP2R_CECSEL
1154 #endif /* RCC_D2CCIP2R_CECSEL */
1155 /**
1156 * @}
1157 */
1158
1159 #if defined(DSI)
1160 /** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI get clock source
1161 * @{
1162 */
1163 #define LL_RCC_DSI_CLKSOURCE RCC_D1CCIPR_DSISEL
1164 /**
1165 * @}
1166 */
1167 #endif /* DSI */
1168
1169 /** @defgroup RCC_LL_EC_DFSDM_CLKSOURCE Peripheral DFSDM get clock source
1170 * @{
1171 */
1172 #if defined(RCC_D2CCIP1R_DFSDM1SEL)
1173 #define LL_RCC_DFSDM1_CLKSOURCE RCC_D2CCIP1R_DFSDM1SEL
1174 #else
1175 #define LL_RCC_DFSDM1_CLKSOURCE RCC_CDCCIP1R_DFSDM1SEL
1176 #endif /* RCC_D2CCIP1R_DFSDM1SEL */
1177 /**
1178 * @}
1179 */
1180
1181 #if defined(DFSDM2_BASE)
1182 /** @defgroup RCC_LL_EC_DFSDM2_CLKSOURCE Peripheral DFSDM2 get clock source
1183 * @{
1184 */
1185 #define LL_RCC_DFSDM2_CLKSOURCE RCC_SRDCCIPR_DFSDM2SEL
1186 /**
1187 * @}
1188 */
1189 #endif /* DFSDM2 */
1190
1191
1192 /** @defgroup RCC_LL_EC_FMC_CLKSOURCE Peripheral FMC get clock source
1193 * @{
1194 */
1195 #if defined(RCC_D1CCIPR_FMCSEL)
1196 #define LL_RCC_FMC_CLKSOURCE RCC_D1CCIPR_FMCSEL
1197 #else
1198 #define LL_RCC_FMC_CLKSOURCE RCC_CDCCIPR_FMCSEL
1199 #endif
1200 /**
1201 * @}
1202 */
1203
1204 #if defined(QUADSPI)
1205 /** @defgroup RCC_LL_EC_QSPI_CLKSOURCE Peripheral QSPI get clock source
1206 * @{
1207 */
1208 #define LL_RCC_QSPI_CLKSOURCE RCC_D1CCIPR_QSPISEL
1209 /**
1210 * @}
1211 */
1212 #endif /* QUADSPI */
1213
1214 #if defined(OCTOSPI1) || defined(OCTOSPI2)
1215 /** @defgroup RCC_LL_EC_OSPI_CLKSOURCE Peripheral OSPI get clock source
1216 * @{
1217 */
1218 #define LL_RCC_OSPI_CLKSOURCE RCC_CDCCIPR_OCTOSPISEL
1219 /**
1220 * @}
1221 */
1222 #endif /* OCTOSPI1 || OCTOSPI2 */
1223
1224 /** @defgroup RCC_LL_EC_CLKP_CLKSOURCE Peripheral CLKP get clock source
1225 * @{
1226 */
1227 #if defined(RCC_D1CCIPR_CKPERSEL)
1228 #define LL_RCC_CLKP_CLKSOURCE RCC_D1CCIPR_CKPERSEL
1229 #else
1230 #define LL_RCC_CLKP_CLKSOURCE RCC_CDCCIPR_CKPERSEL
1231 #endif /* RCC_D1CCIPR_CKPERSEL */
1232 /**
1233 * @}
1234 */
1235
1236 /** @defgroup RCC_LL_EC_SPIx_CLKSOURCE Peripheral SPI get clock source
1237 * @{
1238 */
1239 #if defined(RCC_D2CCIP1R_SPI123SEL)
1240 #define LL_RCC_SPI123_CLKSOURCE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, 0x00000000U)
1241 #else
1242 #define LL_RCC_SPI123_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, 0x00000000U)
1243 #endif /* RCC_D2CCIP1R_SPI123SEL */
1244 #if defined(RCC_D2CCIP1R_SPI45SEL)
1245 #define LL_RCC_SPI45_CLKSOURCE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, 0x00000000U)
1246 #else
1247 #define LL_RCC_SPI45_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, 0x00000000U)
1248 #endif /* RCC_D2CCIP1R_SPI45SEL */
1249 #if defined(RCC_D3CCIPR_SPI6SEL)
1250 #define LL_RCC_SPI6_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, 0x00000000U)
1251 #else
1252 #define LL_RCC_SPI6_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, 0x00000000U)
1253 #endif /* RCC_D3CCIPR_SPI6SEL */
1254 /**
1255 * @}
1256 */
1257
1258 /** @defgroup RCC_LL_EC_SPDIF_CLKSOURCE Peripheral SPDIF get clock source
1259 * @{
1260 */
1261 #if defined(RCC_D2CCIP1R_SPDIFSEL)
1262 #define LL_RCC_SPDIF_CLKSOURCE RCC_D2CCIP1R_SPDIFSEL
1263 #else
1264 #define LL_RCC_SPDIF_CLKSOURCE RCC_CDCCIP1R_SPDIFSEL
1265 #endif /* RCC_D2CCIP1R_SPDIFSEL */
1266 /**
1267 * @}
1268 */
1269
1270 #if defined(FDCAN1) || defined(FDCAN2)
1271 /** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE Peripheral FDCAN get clock source
1272 * @{
1273 */
1274 #if defined(RCC_D2CCIP1R_FDCANSEL)
1275 #define LL_RCC_FDCAN_CLKSOURCE RCC_D2CCIP1R_FDCANSEL
1276 #else
1277 #define LL_RCC_FDCAN_CLKSOURCE RCC_CDCCIP1R_FDCANSEL
1278 #endif
1279 /**
1280 * @}
1281 */
1282 #endif /*FDCAN1 || FDCAN2*/
1283
1284 /** @defgroup RCC_LL_EC_SWP_CLKSOURCE Peripheral SWP get clock source
1285 * @{
1286 */
1287 #if defined(RCC_D2CCIP1R_SWPSEL)
1288 #define LL_RCC_SWP_CLKSOURCE RCC_D2CCIP1R_SWPSEL
1289 #else
1290 #define LL_RCC_SWP_CLKSOURCE RCC_CDCCIP1R_SWPSEL
1291 #endif /* RCC_D2CCIP1R_SWPSEL */
1292 /**
1293 * @}
1294 */
1295
1296 /** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC get clock source
1297 * @{
1298 */
1299 #if defined(RCC_D3CCIPR_ADCSEL)
1300 #define LL_RCC_ADC_CLKSOURCE RCC_D3CCIPR_ADCSEL
1301 #else
1302 #define LL_RCC_ADC_CLKSOURCE RCC_SRDCCIPR_ADCSEL
1303 #endif /* RCC_D3CCIPR_ADCSEL */
1304 /**
1305 * @}
1306 */
1307
1308 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
1309 * @{
1310 */
1311 #define LL_RCC_RTC_CLKSOURCE_NONE (uint32_t)(0x00000000U)
1312 #define LL_RCC_RTC_CLKSOURCE_LSE (uint32_t)(RCC_BDCR_RTCSEL_0)
1313 #define LL_RCC_RTC_CLKSOURCE_LSI (uint32_t)(RCC_BDCR_RTCSEL_1)
1314 #define LL_RCC_RTC_CLKSOURCE_HSE (uint32_t)(RCC_BDCR_RTCSEL_0 | RCC_BDCR_RTCSEL_1)
1315 /**
1316 * @}
1317 */
1318
1319 /** @defgroup RCC_LL_EC_TIM_CLKPRESCALER Timers clocks prescalers selection
1320 * @{
1321 */
1322 #define LL_RCC_TIM_PRESCALER_TWICE (uint32_t)(0x00000000U)
1323 #define LL_RCC_TIM_PRESCALER_FOUR_TIMES (uint32_t)(RCC_CFGR_TIMPRE)
1324 /**
1325 * @}
1326 */
1327
1328 #if defined(HRTIM1)
1329 /** @defgroup RCC_LL_EC_HRTIM_CLKSOURCE High Resolution Timers clock selection
1330 * @{
1331 */
1332 #define LL_RCC_HRTIM_CLKSOURCE_TIM (uint32_t)(0x00000000U) /* HRTIM Clock source is same as other timers */
1333 #define LL_RCC_HRTIM_CLKSOURCE_CPU (uint32_t)(RCC_CFGR_HRTIMSEL) /* HRTIM Clock source is the CPU clock */
1334 /**
1335 * @}
1336 */
1337 #endif /* HRTIM1 */
1338
1339 /** @defgroup RCC_LL_EC_PLLSOURCE All PLLs entry clock source
1340 * @{
1341 */
1342 #define LL_RCC_PLLSOURCE_HSI RCC_PLLCKSELR_PLLSRC_HSI
1343 #define LL_RCC_PLLSOURCE_CSI RCC_PLLCKSELR_PLLSRC_CSI
1344 #define LL_RCC_PLLSOURCE_HSE RCC_PLLCKSELR_PLLSRC_HSE
1345 #define LL_RCC_PLLSOURCE_NONE RCC_PLLCKSELR_PLLSRC_NONE
1346 /**
1347 * @}
1348 */
1349
1350 /** @defgroup RCC_LL_EC_PLLINPUTRANGE All PLLs input range
1351 * @{
1352 */
1353 #define LL_RCC_PLLINPUTRANGE_1_2 (uint32_t)(0x00000000U)
1354 #define LL_RCC_PLLINPUTRANGE_2_4 (uint32_t)(0x00000001)
1355 #define LL_RCC_PLLINPUTRANGE_4_8 (uint32_t)(0x00000002)
1356 #define LL_RCC_PLLINPUTRANGE_8_16 (uint32_t)(0x00000003)
1357 /**
1358 * @}
1359 */
1360
1361 /** @defgroup RCC_LL_EC_PLLVCORANGE All PLLs VCO range
1362 * @{
1363 */
1364 #define LL_RCC_PLLVCORANGE_WIDE (uint32_t)(0x00000000U) /* VCO output range: 192 to 836 MHz OR 128 to 544 MHz (*) */
1365 #define LL_RCC_PLLVCORANGE_MEDIUM (uint32_t)(0x00000001) /* VCO output range: 150 to 420 MHz */
1366 /**
1367 * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
1368 * @}
1369 */
1370
1371 /**
1372 * @}
1373 */
1374
1375 /* Exported macro ------------------------------------------------------------*/
1376 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
1377 * @{
1378 */
1379
1380 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
1381 * @{
1382 */
1383
1384 /**
1385 * @brief Write a value in RCC register
1386 * @param __REG__ Register to be written
1387 * @param __VALUE__ Value to be written in the register
1388 * @retval None
1389 */
1390 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
1391
1392 /**
1393 * @brief Read a value in RCC register
1394 * @param __REG__ Register to be read
1395 * @retval Register value
1396 */
1397 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
1398 /**
1399 * @}
1400 */
1401
1402 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
1403 * @{
1404 */
1405
1406 /**
1407 * @brief Helper macro to calculate the SYSCLK frequency
1408 * @param __SYSINPUTCLKFREQ__ Frequency of the input of sys_ck (based on HSE/CSI/HSI/PLL1P)
1409 * @param __SYSPRESCALER__ This parameter can be one of the following values:
1410 * @arg @ref LL_RCC_SYSCLK_DIV_1
1411 * @arg @ref LL_RCC_SYSCLK_DIV_2
1412 * @arg @ref LL_RCC_SYSCLK_DIV_4
1413 * @arg @ref LL_RCC_SYSCLK_DIV_8
1414 * @arg @ref LL_RCC_SYSCLK_DIV_16
1415 * @arg @ref LL_RCC_SYSCLK_DIV_64
1416 * @arg @ref LL_RCC_SYSCLK_DIV_128
1417 * @arg @ref LL_RCC_SYSCLK_DIV_256
1418 * @arg @ref LL_RCC_SYSCLK_DIV_512
1419 * @retval SYSCLK clock frequency (in Hz)
1420 */
1421 #if defined(RCC_D1CFGR_D1CPRE)
1422 #define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos])
1423 #else
1424 #define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos])
1425 #endif /* RCC_D1CFGR_D1CPRE */
1426
1427 /**
1428 * @brief Helper macro to calculate the HCLK frequency
1429 * @param __SYSCLKFREQ__ SYSCLK frequency.
1430 * @param __HPRESCALER__ This parameter can be one of the following values:
1431 * @arg @ref LL_RCC_AHB_DIV_1
1432 * @arg @ref LL_RCC_AHB_DIV_2
1433 * @arg @ref LL_RCC_AHB_DIV_4
1434 * @arg @ref LL_RCC_AHB_DIV_8
1435 * @arg @ref LL_RCC_AHB_DIV_16
1436 * @arg @ref LL_RCC_AHB_DIV_64
1437 * @arg @ref LL_RCC_AHB_DIV_128
1438 * @arg @ref LL_RCC_AHB_DIV_256
1439 * @arg @ref LL_RCC_AHB_DIV_512
1440 * @retval HCLK clock frequency (in Hz)
1441 */
1442 #if defined(RCC_D1CFGR_HPRE)
1443 #define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> LL_RCC_PrescTable[((__HPRESCALER__) & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos])
1444 #else
1445 #define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> LL_RCC_PrescTable[((__HPRESCALER__) & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos])
1446 #endif /* RCC_D1CFGR_HPRE */
1447
1448 /**
1449 * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
1450 * @param __HCLKFREQ__ HCLK frequency
1451 * @param __APB1PRESCALER__ This parameter can be one of the following values:
1452 * @arg @ref LL_RCC_APB1_DIV_1
1453 * @arg @ref LL_RCC_APB1_DIV_2
1454 * @arg @ref LL_RCC_APB1_DIV_4
1455 * @arg @ref LL_RCC_APB1_DIV_8
1456 * @arg @ref LL_RCC_APB1_DIV_16
1457 * @retval PCLK1 clock frequency (in Hz)
1458 */
1459 #if defined(RCC_D2CFGR_D2PPRE1)
1460 #define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos])
1461 #else
1462 #define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos])
1463 #endif /* RCC_D2CFGR_D2PPRE1 */
1464
1465 /**
1466 * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
1467 * @param __HCLKFREQ__ HCLK frequency
1468 * @param __APB2PRESCALER__ This parameter can be one of the following values:
1469 * @arg @ref LL_RCC_APB2_DIV_1
1470 * @arg @ref LL_RCC_APB2_DIV_2
1471 * @arg @ref LL_RCC_APB2_DIV_4
1472 * @arg @ref LL_RCC_APB2_DIV_8
1473 * @arg @ref LL_RCC_APB2_DIV_16
1474 * @retval PCLK2 clock frequency (in Hz)
1475 */
1476 #if defined(RCC_D2CFGR_D2PPRE2)
1477 #define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_D2CFGR_D2PPRE2) >> RCC_D2CFGR_D2PPRE2_Pos])
1478 #else
1479 #define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos])
1480 #endif /* RCC_D2CFGR_D2PPRE2 */
1481
1482 /**
1483 * @brief Helper macro to calculate the PCLK3 frequency (APB3)
1484 * @param __HCLKFREQ__ HCLK frequency
1485 * @param __APB3PRESCALER__ This parameter can be one of the following values:
1486 * @arg @ref LL_RCC_APB3_DIV_1
1487 * @arg @ref LL_RCC_APB3_DIV_2
1488 * @arg @ref LL_RCC_APB3_DIV_4
1489 * @arg @ref LL_RCC_APB3_DIV_8
1490 * @arg @ref LL_RCC_APB3_DIV_16
1491 * @retval PCLK1 clock frequency (in Hz)
1492 */
1493 #if defined(RCC_D1CFGR_D1PPRE)
1494 #define LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_D1CFGR_D1PPRE) >> RCC_D1CFGR_D1PPRE_Pos])
1495 #else
1496 #define LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_CDCFGR1_CDPPRE) >> RCC_CDCFGR1_CDPPRE_Pos])
1497 #endif /* RCC_D1CFGR_D1PPRE */
1498
1499 /**
1500 * @brief Helper macro to calculate the PCLK4 frequency (ABP4)
1501 * @param __HCLKFREQ__ HCLK frequency
1502 * @param __APB4PRESCALER__ This parameter can be one of the following values:
1503 * @arg @ref LL_RCC_APB4_DIV_1
1504 * @arg @ref LL_RCC_APB4_DIV_2
1505 * @arg @ref LL_RCC_APB4_DIV_4
1506 * @arg @ref LL_RCC_APB4_DIV_8
1507 * @arg @ref LL_RCC_APB4_DIV_16
1508 * @retval PCLK1 clock frequency (in Hz)
1509 */
1510 #if defined(RCC_D3CFGR_D3PPRE)
1511 #define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos])
1512 #else
1513 #define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_SRDCFGR_SRDPPRE) >> RCC_SRDCFGR_SRDPPRE_Pos])
1514 #endif /* RCC_D3CFGR_D3PPRE */
1515
1516 /**
1517 * @}
1518 */
1519
1520 #if defined(USE_FULL_LL_DRIVER)
1521 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
1522 * @{
1523 */
1524 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
1525 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
1526 /**
1527 * @}
1528 */
1529 #endif /* USE_FULL_LL_DRIVER */
1530
1531 /**
1532 * @}
1533 */
1534
1535 /* Exported functions --------------------------------------------------------*/
1536 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
1537 * @{
1538 */
1539
1540 /** @defgroup RCC_LL_EF_HSE HSE
1541 * @{
1542 */
1543
1544 /**
1545 * @brief Enable the Clock Security System.
1546 * @note Once HSE Clock Security System is enabled it cannot be changed anymore unless
1547 * a reset occurs or system enter in standby mode.
1548 * @rmtoll CR CSSHSEON LL_RCC_HSE_EnableCSS
1549 * @retval None
1550 */
1551 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
1552 {
1553 SET_BIT(RCC->CR, RCC_CR_CSSHSEON);
1554 }
1555
1556 /**
1557 * @brief Enable HSE external oscillator (HSE Bypass)
1558 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
1559 * @retval None
1560 */
1561 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
1562 {
1563 SET_BIT(RCC->CR, RCC_CR_HSEBYP);
1564 }
1565
1566 /**
1567 * @brief Disable HSE external oscillator (HSE Bypass)
1568 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
1569 * @retval None
1570 */
1571 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
1572 {
1573 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
1574 }
1575
1576 #if defined(RCC_CR_HSEEXT)
1577 /**
1578 * @brief Select the Analog HSE external clock type in Bypass mode
1579 * @rmtoll CR HSEEXT LL_RCC_HSE_SelectAnalogClock
1580 * @retval None
1581 */
1582 __STATIC_INLINE void LL_RCC_HSE_SelectAnalogClock(void)
1583 {
1584 CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);
1585 }
1586
1587 /**
1588 * @brief Select the Digital HSE external clock type in Bypass mode
1589 * @rmtoll CR HSEEXT LL_RCC_HSE_SelectDigitalClock
1590 * @retval None
1591 */
1592 __STATIC_INLINE void LL_RCC_HSE_SelectDigitalClock(void)
1593 {
1594 SET_BIT(RCC->CR, RCC_CR_HSEEXT);
1595 }
1596 #endif /* RCC_CR_HSEEXT */
1597
1598 /**
1599 * @brief Enable HSE crystal oscillator (HSE ON)
1600 * @rmtoll CR HSEON LL_RCC_HSE_Enable
1601 * @retval None
1602 */
1603 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
1604 {
1605 SET_BIT(RCC->CR, RCC_CR_HSEON);
1606 }
1607
1608 /**
1609 * @brief Disable HSE crystal oscillator (HSE ON)
1610 * @rmtoll CR HSEON LL_RCC_HSE_Disable
1611 * @retval None
1612 */
1613 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
1614 {
1615 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
1616 }
1617
1618 /**
1619 * @brief Check if HSE oscillator Ready
1620 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
1621 * @retval State of bit (1 or 0).
1622 */
1623 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
1624 {
1625 return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY))?1UL:0UL);
1626 }
1627
1628 /**
1629 * @}
1630 */
1631
1632 /** @defgroup RCC_LL_EF_HSI HSI
1633 * @{
1634 */
1635
1636 /**
1637 * @brief Enable HSI oscillator
1638 * @rmtoll CR HSION LL_RCC_HSI_Enable
1639 * @retval None
1640 */
1641 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
1642 {
1643 SET_BIT(RCC->CR, RCC_CR_HSION);
1644 }
1645
1646 /**
1647 * @brief Disable HSI oscillator
1648 * @rmtoll CR HSION LL_RCC_HSI_Disable
1649 * @retval None
1650 */
1651 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
1652 {
1653 CLEAR_BIT(RCC->CR, RCC_CR_HSION);
1654 }
1655
1656 /**
1657 * @brief Check if HSI clock is ready
1658 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
1659 * @retval State of bit (1 or 0).
1660 */
1661 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
1662 {
1663 return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY))?1UL:0UL);
1664 }
1665
1666 /**
1667 * @brief Check if HSI new divider applied and ready
1668 * @rmtoll CR HSIDIVF LL_RCC_HSI_IsDividerReady
1669 * @retval State of bit (1 or 0).
1670 */
1671 __STATIC_INLINE uint32_t LL_RCC_HSI_IsDividerReady(void)
1672 {
1673 return ((READ_BIT(RCC->CR, RCC_CR_HSIDIVF) == (RCC_CR_HSIDIVF))?1UL:0UL);
1674 }
1675
1676 /**
1677 * @brief Set HSI divider
1678 * @rmtoll CR HSIDIV LL_RCC_HSI_SetDivider
1679 * @param Divider This parameter can be one of the following values:
1680 * @arg @ref LL_RCC_HSI_DIV1
1681 * @arg @ref LL_RCC_HSI_DIV2
1682 * @arg @ref LL_RCC_HSI_DIV4
1683 * @arg @ref LL_RCC_HSI_DIV8
1684 * @retval None.
1685 */
1686 __STATIC_INLINE void LL_RCC_HSI_SetDivider(uint32_t Divider)
1687 {
1688 MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, Divider);
1689 }
1690
1691 /**
1692 * @brief Get HSI divider
1693 * @rmtoll CR HSIDIV LL_RCC_HSI_GetDivider
1694 * @retval can be one of the following values:
1695 * @arg @ref LL_RCC_HSI_DIV1
1696 * @arg @ref LL_RCC_HSI_DIV2
1697 * @arg @ref LL_RCC_HSI_DIV4
1698 * @arg @ref LL_RCC_HSI_DIV8
1699 */
1700 __STATIC_INLINE uint32_t LL_RCC_HSI_GetDivider(void)
1701 {
1702 return (READ_BIT(RCC->CR, RCC_CR_HSIDIV));
1703 }
1704
1705 /**
1706 * @brief Enable HSI oscillator in Stop mode
1707 * @rmtoll CR HSIKERON LL_RCC_HSI_EnableStopMode
1708 * @retval None
1709 */
1710 __STATIC_INLINE void LL_RCC_HSI_EnableStopMode(void)
1711 {
1712 SET_BIT(RCC->CR, RCC_CR_HSIKERON);
1713 }
1714
1715 /**
1716 * @brief Disable HSI oscillator in Stop mode
1717 * @rmtoll CR HSION LL_RCC_HSI_DisableStopMode
1718 * @retval None
1719 */
1720 __STATIC_INLINE void LL_RCC_HSI_DisableStopMode(void)
1721 {
1722 CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
1723 }
1724
1725 /**
1726 * @brief Get HSI Calibration value
1727 * @note When HSITRIM is written, HSICAL is updated with the sum of
1728 * HSITRIM and the factory trim value
1729 * @rmtoll HSICFGR HSICAL LL_RCC_HSI_GetCalibration
1730 * @retval A value between 0 and 4095 (0xFFF)
1731 */
1732 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
1733 {
1734 return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSICAL) >> RCC_HSICFGR_HSICAL_Pos);
1735 }
1736
1737 /**
1738 * @brief Set HSI Calibration trimming
1739 * @note user-programmable trimming value that is added to the HSICAL
1740 * @note Default value is 64 (32 for Cut1.x), which, when added to the HSICAL value,
1741 * should trim the HSI to 64 MHz +/- 1 %
1742 * @rmtoll HSICFGR HSITRIM LL_RCC_HSI_SetCalibTrimming
1743 * @param Parameter can be a value between 0 and 127 (63 for Cut1.x)
1744 * @retval None
1745 */
1746 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
1747 {
1748 #if defined(RCC_VER_X)
1749 if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
1750 {
1751 /* STM32H7 Rev.Y */
1752 MODIFY_REG(RCC->HSICFGR, 0x3F000U, Value << 12U);
1753 }
1754 else
1755 {
1756 /* STM32H7 Rev.V */
1757 MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos);
1758 }
1759 #else
1760 MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos);
1761 #endif /* RCC_VER_X */
1762 }
1763
1764 /**
1765 * @brief Get HSI Calibration trimming
1766 * @rmtoll HSICFGR HSITRIM LL_RCC_HSI_GetCalibTrimming
1767 * @retval A value between 0 and 127 (63 for Cut1.x)
1768 */
1769 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
1770 {
1771 #if defined(RCC_VER_X)
1772 if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
1773 {
1774 /* STM32H7 Rev.Y */
1775 return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x3F000U) >> 12U);
1776 }
1777 else
1778 {
1779 /* STM32H7 Rev.V */
1780 return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
1781 }
1782 #else
1783 return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
1784 #endif /* RCC_VER_X */
1785 }
1786
1787 /**
1788 * @}
1789 */
1790
1791 /** @defgroup RCC_LL_EF_CSI CSI
1792 * @{
1793 */
1794
1795 /**
1796 * @brief Enable CSI oscillator
1797 * @rmtoll CR CSION LL_RCC_CSI_Enable
1798 * @retval None
1799 */
1800 __STATIC_INLINE void LL_RCC_CSI_Enable(void)
1801 {
1802 SET_BIT(RCC->CR, RCC_CR_CSION);
1803 }
1804
1805 /**
1806 * @brief Disable CSI oscillator
1807 * @rmtoll CR CSION LL_RCC_CSI_Disable
1808 * @retval None
1809 */
1810 __STATIC_INLINE void LL_RCC_CSI_Disable(void)
1811 {
1812 CLEAR_BIT(RCC->CR, RCC_CR_CSION);
1813 }
1814
1815 /**
1816 * @brief Check if CSI clock is ready
1817 * @rmtoll CR CSIRDY LL_RCC_CSI_IsReady
1818 * @retval State of bit (1 or 0).
1819 */
1820 __STATIC_INLINE uint32_t LL_RCC_CSI_IsReady(void)
1821 {
1822 return ((READ_BIT(RCC->CR, RCC_CR_CSIRDY) == (RCC_CR_CSIRDY))?1UL:0UL);
1823 }
1824
1825 /**
1826 * @brief Enable CSI oscillator in Stop mode
1827 * @rmtoll CR CSIKERON LL_RCC_CSI_EnableStopMode
1828 * @retval None
1829 */
1830 __STATIC_INLINE void LL_RCC_CSI_EnableStopMode(void)
1831 {
1832 SET_BIT(RCC->CR, RCC_CR_CSIKERON);
1833 }
1834
1835 /**
1836 * @brief Disable CSI oscillator in Stop mode
1837 * @rmtoll CR CSIKERON LL_RCC_CSI_DisableStopMode
1838 * @retval None
1839 */
1840 __STATIC_INLINE void LL_RCC_CSI_DisableStopMode(void)
1841 {
1842 CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON);
1843 }
1844
1845 /**
1846 * @brief Get CSI Calibration value
1847 * @note When CSITRIM is written, CSICAL is updated with the sum of
1848 * CSITRIM and the factory trim value
1849 * @rmtoll CSICFGR CSICAL LL_RCC_CSI_GetCalibration
1850 * @retval A value between 0 and 255 (0xFF)
1851 */
1852 __STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibration(void)
1853 {
1854 #if defined(RCC_VER_X)
1855 if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
1856 {
1857 /* STM32H7 Rev.Y */
1858 return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x3FC0000U) >> 18U);
1859 }
1860 else
1861 {
1862 /* STM32H7 Rev.V */
1863 return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSICAL) >> RCC_CSICFGR_CSICAL_Pos);
1864 }
1865 #else
1866 return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSICAL) >> RCC_CSICFGR_CSICAL_Pos);
1867 #endif /* RCC_VER_X */
1868 }
1869
1870 /**
1871 * @brief Set CSI Calibration trimming
1872 * @note user-programmable trimming value that is added to the CSICAL
1873 * @note Default value is 16, which, when added to the CSICAL value,
1874 * should trim the CSI to 4 MHz +/- 1 %
1875 * @rmtoll CSICFGR CSITRIM LL_RCC_CSI_SetCalibTrimming
1876 * @param Value can be a value between 0 and 31
1877 * @retval None
1878 */
1879 __STATIC_INLINE void LL_RCC_CSI_SetCalibTrimming(uint32_t Value)
1880 {
1881 #if defined(RCC_VER_X)
1882 if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
1883 {
1884 /* STM32H7 Rev.Y */
1885 MODIFY_REG(RCC->HSICFGR, 0x7C000000U, Value << 26U);
1886 }
1887 else
1888 {
1889 /* STM32H7 Rev.V */
1890 MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, Value << RCC_CSICFGR_CSITRIM_Pos);
1891 }
1892 #else
1893 MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, Value << RCC_CSICFGR_CSITRIM_Pos);
1894 #endif /* RCC_VER_X */
1895 }
1896
1897 /**
1898 * @brief Get CSI Calibration trimming
1899 * @rmtoll CSICFGR CSITRIM LL_RCC_CSI_GetCalibTrimming
1900 * @retval A value between 0 and 31
1901 */
1902 __STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibTrimming(void)
1903 {
1904 #if defined(RCC_VER_X)
1905 if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
1906 {
1907 /* STM32H7 Rev.Y */
1908 return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x7C000000U) >> 26U);
1909 }
1910 else
1911 {
1912 /* STM32H7 Rev.V */
1913 return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
1914 }
1915 #else
1916 return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
1917 #endif /* RCC_VER_X */
1918 }
1919
1920 /**
1921 * @}
1922 */
1923
1924 /** @defgroup RCC_LL_EF_HSI48 HSI48
1925 * @{
1926 */
1927
1928 /**
1929 * @brief Enable HSI48 oscillator
1930 * @rmtoll CR HSI48ON LL_RCC_HSI48_Enable
1931 * @retval None
1932 */
1933 __STATIC_INLINE void LL_RCC_HSI48_Enable(void)
1934 {
1935 SET_BIT(RCC->CR, RCC_CR_HSI48ON);
1936 }
1937
1938 /**
1939 * @brief Disable HSI48 oscillator
1940 * @rmtoll CR HSI48ON LL_RCC_HSI48_Disable
1941 * @retval None
1942 */
1943 __STATIC_INLINE void LL_RCC_HSI48_Disable(void)
1944 {
1945 CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON);
1946 }
1947
1948 /**
1949 * @brief Check if HSI48 clock is ready
1950 * @rmtoll CR HSI48RDY LL_RCC_HSI48_IsReady
1951 * @retval State of bit (1 or 0).
1952 */
1953 __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
1954 {
1955 return ((READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == (RCC_CR_HSI48RDY))?1UL:0UL);
1956 }
1957
1958 /**
1959 * @brief Get HSI48 Calibration value
1960 * @note When HSI48TRIM is written, HSI48CAL is updated with the sum of
1961 * HSI48TRIM and the factory trim value
1962 * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration
1963 * @retval A value between 0 and 1023 (0x3FF)
1964 */
1965 __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
1966 {
1967 return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);
1968 }
1969 /**
1970 * @}
1971 */
1972
1973 #if defined(RCC_CR_D1CKRDY)
1974
1975 /** @defgroup RCC_LL_EF_D1CLK D1CKREADY
1976 * @{
1977 */
1978
1979 /**
1980 * @brief Check if D1 clock is ready
1981 * @rmtoll CR D1CKRDY LL_RCC_D1CK_IsReady
1982 * @retval State of bit (1 or 0).
1983 */
1984 __STATIC_INLINE uint32_t LL_RCC_D1CK_IsReady(void)
1985 {
1986 return ((READ_BIT(RCC->CR, RCC_CR_D1CKRDY) == (RCC_CR_D1CKRDY))?1UL:0UL);
1987 }
1988
1989 /**
1990 * @}
1991 */
1992 #else
1993
1994 /** @defgroup RCC_LL_EF_CPUCLK CPUCKREADY
1995 * @{
1996 */
1997
1998 /**
1999 * @brief Check if CPU clock is ready
2000 * @rmtoll CR CPUCKRDY LL_RCC_CPUCK_IsReady
2001 * @retval State of bit (1 or 0).
2002 */
2003 __STATIC_INLINE uint32_t LL_RCC_CPUCK_IsReady(void)
2004 {
2005 return ((READ_BIT(RCC->CR, RCC_CR_CPUCKRDY) == (RCC_CR_CPUCKRDY))?1UL:0UL);
2006 }
2007 /* alias */
2008 #define LL_RCC_D1CK_IsReady LL_RCC_CPUCK_IsReady
2009 /**
2010 * @}
2011 */
2012 #endif /* RCC_CR_D1CKRDY */
2013
2014 #if defined(RCC_CR_D2CKRDY)
2015
2016 /** @defgroup RCC_LL_EF_D2CLK D2CKREADY
2017 * @{
2018 */
2019
2020 /**
2021 * @brief Check if D2 clock is ready
2022 * @rmtoll CR D2CKRDY LL_RCC_D2CK_IsReady
2023 * @retval State of bit (1 or 0).
2024 */
2025 __STATIC_INLINE uint32_t LL_RCC_D2CK_IsReady(void)
2026 {
2027 return ((READ_BIT(RCC->CR, RCC_CR_D2CKRDY) == (RCC_CR_D2CKRDY))?1UL:0UL);
2028 }
2029 /**
2030 * @}
2031 */
2032 #else
2033
2034 /** @defgroup RCC_LL_EF_CDCLK CDCKREADY
2035 * @{
2036 */
2037
2038 /**
2039 * @brief Check if CD clock is ready
2040 * @rmtoll CR CDCKRDY LL_RCC_CDCK_IsReady
2041 * @retval State of bit (1 or 0).
2042 */
2043 __STATIC_INLINE uint32_t LL_RCC_CDCK_IsReady(void)
2044 {
2045 return ((READ_BIT(RCC->CR, RCC_CR_CDCKRDY) == (RCC_CR_CDCKRDY))?1UL:0UL);
2046 }
2047 #define LL_RCC_D2CK_IsReady LL_RCC_CDCK_IsReady
2048 /**
2049 * @}
2050 */
2051 #endif /* RCC_CR_D2CKRDY */
2052
2053 /** @defgroup RCC_LL_EF_SYSTEM_WIDE_RESET RESET
2054 * @{
2055 */
2056 #if defined(RCC_GCR_WW1RSC)
2057
2058 /**
2059 * @brief Enable system wide reset for Window Watch Dog 1
2060 * @rmtoll GCR WW1RSC LL_RCC_WWDG1_EnableSystemReset
2061 * @retval None.
2062 */
2063 __STATIC_INLINE void LL_RCC_WWDG1_EnableSystemReset(void)
2064 {
2065 SET_BIT(RCC->GCR, RCC_GCR_WW1RSC);
2066 }
2067
2068 /**
2069 * @brief Check if Window Watch Dog 1 reset is system wide
2070 * @rmtoll GCR WW1RSC LL_RCC_WWDG1_IsSystemReset
2071 * @retval State of bit (1 or 0).
2072 */
2073 __STATIC_INLINE uint32_t LL_RCC_WWDG1_IsSystemReset(void)
2074 {
2075 return ((READ_BIT(RCC->GCR, RCC_GCR_WW1RSC) == RCC_GCR_WW1RSC)?1UL:0UL);
2076 }
2077 #endif /* RCC_GCR_WW1RSC */
2078
2079 #if defined(DUAL_CORE)
2080 /**
2081 * @brief Enable system wide reset for Window Watch Dog 2
2082 * @rmtoll GCR WW1RSC LL_RCC_WWDG2_EnableSystemReset
2083 * @retval None.
2084 */
2085 __STATIC_INLINE void LL_RCC_WWDG2_EnableSystemReset(void)
2086 {
2087 SET_BIT(RCC->GCR, RCC_GCR_WW2RSC);
2088 }
2089
2090 /**
2091 * @brief Check if Window Watch Dog 2 reset is system wide
2092 * @rmtoll GCR WW2RSC LL_RCC_WWDG2_IsSystemReset
2093 * @retval State of bit (1 or 0).
2094 */
2095 __STATIC_INLINE uint32_t LL_RCC_WWDG2_IsSystemReset(void)
2096 {
2097 return ((READ_BIT(RCC->GCR, RCC_GCR_WW2RSC) == RCC_GCR_WW2RSC)?1UL:0UL);
2098 }
2099 #endif /*DUAL_CORE*/
2100 /**
2101 * @}
2102 */
2103
2104 #if defined(DUAL_CORE)
2105 /** @defgroup RCC_LL_EF_BOOT_CPU CPU
2106 * @{
2107 */
2108
2109 /**
2110 * @brief Force CM4 boot (if hold by option byte BCM4 = 0)
2111 * @rmtoll GCR BOOT_C2 LL_RCC_ForceCM4Boot
2112 * @retval None.
2113 */
2114 __STATIC_INLINE void LL_RCC_ForceCM4Boot(void)
2115 {
2116 SET_BIT(RCC->GCR, RCC_GCR_BOOT_C2);
2117 }
2118
2119 /**
2120 * @brief Check if CM4 boot is forced
2121 * @rmtoll GCR BOOT_C2 LL_RCC_IsCM4BootForced
2122 * @retval State of bit (1 or 0).
2123 */
2124 __STATIC_INLINE uint32_t LL_RCC_IsCM4BootForced(void)
2125 {
2126 return ((READ_BIT(RCC->GCR, RCC_GCR_BOOT_C2) == RCC_GCR_BOOT_C2)?1UL:0UL);
2127 }
2128
2129 /**
2130 * @brief Force CM7 boot (if hold by option byte BCM7 = 0)
2131 * @rmtoll GCR BOOT_C1 LL_RCC_ForceCM7Boot
2132 * @retval None.
2133 */
2134 __STATIC_INLINE void LL_RCC_ForceCM7Boot(void)
2135 {
2136 SET_BIT(RCC->GCR, RCC_GCR_BOOT_C1);
2137 }
2138
2139 /**
2140 * @brief Check if CM7 boot is forced
2141 * @rmtoll GCR BOOT_C1 LL_RCC_IsCM7BootForced
2142 * @retval State of bit (1 or 0).
2143 */
2144 __STATIC_INLINE uint32_t LL_RCC_IsCM7BootForced(void)
2145 {
2146 return ((READ_BIT(RCC->GCR, RCC_GCR_BOOT_C1) == RCC_GCR_BOOT_C1)?1UL:0UL);
2147 }
2148
2149 /**
2150 * @}
2151 */
2152 #endif /*DUAL_CORE*/
2153
2154 /** @defgroup RCC_LL_EF_LSE LSE
2155 * @{
2156 */
2157
2158 /**
2159 * @brief Enable the Clock Security System on LSE.
2160 * @note Once LSE Clock Security System is enabled it cannot be changed anymore unless
2161 * a clock failure is detected.
2162 * @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS
2163 * @retval None
2164 */
2165 __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
2166 {
2167 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
2168 }
2169
2170 /**
2171 * @brief Check if LSE failure is detected by Clock Security System
2172 * @rmtoll BDCR LSECSSD LL_RCC_LSE_IsFailureDetected
2173 * @retval State of bit (1 or 0).
2174 */
2175 __STATIC_INLINE uint32_t LL_RCC_LSE_IsFailureDetected(void)
2176 {
2177 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD))?1UL:0UL);
2178 }
2179
2180 /**
2181 * @brief Enable Low Speed External (LSE) crystal.
2182 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
2183 * @retval None
2184 */
2185 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
2186 {
2187 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
2188 }
2189
2190 /**
2191 * @brief Disable Low Speed External (LSE) crystal.
2192 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
2193 * @retval None
2194 */
2195 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
2196 {
2197 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
2198 }
2199
2200 /**
2201 * @brief Enable external clock source (LSE bypass).
2202 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
2203 * @retval None
2204 */
2205 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
2206 {
2207 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
2208 }
2209
2210 /**
2211 * @brief Disable external clock source (LSE bypass).
2212 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
2213 * @retval None
2214 */
2215 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
2216 {
2217 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
2218 }
2219
2220 #if defined(RCC_BDCR_LSEEXT)
2221 /**
2222 * @brief Enable Low-speed external DIGITAL clock type in Bypass mode (not to be used if RTC is active).
2223 * @note The external clock must be enabled with the LSEON bit, to be used by the device.
2224 * The LSEEXT bit can be written only if the LSE oscillator is disabled.
2225 * @rmtoll BDCR LSEEXT LL_RCC_LSE_SelectDigitalClock
2226 * @retval None
2227 */
2228 __STATIC_INLINE void LL_RCC_LSE_SelectDigitalClock(void)
2229 {
2230 SET_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);
2231 }
2232
2233 /**
2234 * @brief Enable Low-speed external ANALOG clock type in Bypass mode (default after Backup domain reset).
2235 * @note The external clock must be enabled with the LSEON bit, to be used by the device.
2236 * The LSEEXT bit can be written only if the LSE oscillator is disabled.
2237 * @rmtoll BDCR LSEEXT LL_RCC_LSE_SelectAnalogClock
2238 * @retval None
2239 */
2240 __STATIC_INLINE void LL_RCC_LSE_SelectAnalogClock(void)
2241 {
2242 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);
2243 }
2244 #endif /* RCC_BDCR_LSEEXT */
2245
2246 /**
2247 * @brief Set LSE oscillator drive capability
2248 * @note The oscillator is in Xtal mode when it is not in bypass mode.
2249 * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
2250 * @param LSEDrive This parameter can be one of the following values:
2251 * @arg @ref LL_RCC_LSEDRIVE_LOW
2252 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
2253 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
2254 * @arg @ref LL_RCC_LSEDRIVE_HIGH
2255 * @retval None
2256 */
2257 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
2258 {
2259 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
2260 }
2261
2262 /**
2263 * @brief Get LSE oscillator drive capability
2264 * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
2265 * @retval Returned value can be one of the following values:
2266 * @arg @ref LL_RCC_LSEDRIVE_LOW
2267 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
2268 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
2269 * @arg @ref LL_RCC_LSEDRIVE_HIGH
2270 */
2271 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
2272 {
2273 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
2274 }
2275
2276 /**
2277 * @brief Check if LSE oscillator Ready
2278 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
2279 * @retval State of bit (1 or 0).
2280 */
2281 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
2282 {
2283 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY))?1UL:0UL);
2284 }
2285
2286 /**
2287 * @}
2288 */
2289
2290 /** @defgroup RCC_LL_EF_LSI LSI
2291 * @{
2292 */
2293
2294 /**
2295 * @brief Enable LSI Oscillator
2296 * @rmtoll CSR LSION LL_RCC_LSI_Enable
2297 * @retval None
2298 */
2299 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
2300 {
2301 SET_BIT(RCC->CSR, RCC_CSR_LSION);
2302 }
2303
2304 /**
2305 * @brief Disable LSI Oscillator
2306 * @rmtoll CSR LSION LL_RCC_LSI_Disable
2307 * @retval None
2308 */
2309 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
2310 {
2311 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
2312 }
2313
2314 /**
2315 * @brief Check if LSI is Ready
2316 * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
2317 * @retval State of bit (1 or 0).
2318 */
2319 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
2320 {
2321 return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY))?1UL:0UL);
2322 }
2323
2324 /**
2325 * @}
2326 */
2327
2328 /** @defgroup RCC_LL_EF_System System
2329 * @{
2330 */
2331
2332 /**
2333 * @brief Configure the system clock source
2334 * @rmtoll CFGR SW LL_RCC_SetSysClkSource
2335 * @param Source This parameter can be one of the following values:
2336 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
2337 * @arg @ref LL_RCC_SYS_CLKSOURCE_CSI
2338 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
2339 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL1
2340 * @retval None
2341 */
2342 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
2343 {
2344 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
2345 }
2346
2347 /**
2348 * @brief Get the system clock source
2349 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
2350 * @retval Returned value can be one of the following values:
2351 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
2352 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_CSI
2353 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
2354 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL1
2355 */
2356 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
2357 {
2358 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
2359 }
2360
2361 /**
2362 * @brief Configure the system wakeup clock source
2363 * @rmtoll CFGR STOPWUCK LL_RCC_SetSysWakeUpClkSource
2364 * @param Source This parameter can be one of the following values:
2365 * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI
2366 * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_CSI
2367 * @retval None
2368 */
2369 __STATIC_INLINE void LL_RCC_SetSysWakeUpClkSource(uint32_t Source)
2370 {
2371 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Source);
2372 }
2373
2374 /**
2375 * @brief Get the system wakeup clock source
2376 * @rmtoll CFGR STOPWUCK LL_RCC_GetSysWakeUpClkSource
2377 * @retval Returned value can be one of the following values:
2378 * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI
2379 * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_CSI
2380 */
2381 __STATIC_INLINE uint32_t LL_RCC_GetSysWakeUpClkSource(void)
2382 {
2383 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK));
2384 }
2385
2386 /**
2387 * @brief Configure the kernel wakeup clock source
2388 * @rmtoll CFGR STOPKERWUCK LL_RCC_SetKerWakeUpClkSource
2389 * @param Source This parameter can be one of the following values:
2390 * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_HSI
2391 * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_CSI
2392 * @retval None
2393 */
2394 __STATIC_INLINE void LL_RCC_SetKerWakeUpClkSource(uint32_t Source)
2395 {
2396 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, Source);
2397 }
2398
2399 /**
2400 * @brief Get the kernel wakeup clock source
2401 * @rmtoll CFGR STOPKERWUCK LL_RCC_GetKerWakeUpClkSource
2402 * @retval Returned value can be one of the following values:
2403 * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_HSI
2404 * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_CSI
2405 */
2406 __STATIC_INLINE uint32_t LL_RCC_GetKerWakeUpClkSource(void)
2407 {
2408 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPKERWUCK));
2409 }
2410
2411 /**
2412 * @brief Set System prescaler
2413 * @rmtoll D1CFGR/CDCFGR1 D1CPRE/CDCPRE LL_RCC_SetSysPrescaler
2414 * @param Prescaler This parameter can be one of the following values:
2415 * @arg @ref LL_RCC_SYSCLK_DIV_1
2416 * @arg @ref LL_RCC_SYSCLK_DIV_2
2417 * @arg @ref LL_RCC_SYSCLK_DIV_4
2418 * @arg @ref LL_RCC_SYSCLK_DIV_8
2419 * @arg @ref LL_RCC_SYSCLK_DIV_16
2420 * @arg @ref LL_RCC_SYSCLK_DIV_64
2421 * @arg @ref LL_RCC_SYSCLK_DIV_128
2422 * @arg @ref LL_RCC_SYSCLK_DIV_256
2423 * @arg @ref LL_RCC_SYSCLK_DIV_512
2424 * @retval None
2425 */
2426 __STATIC_INLINE void LL_RCC_SetSysPrescaler(uint32_t Prescaler)
2427 {
2428 #if defined(RCC_D1CFGR_D1CPRE)
2429 MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, Prescaler);
2430 #else
2431 MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, Prescaler);
2432 #endif /* RCC_D1CFGR_D1CPRE */
2433 }
2434
2435 /**
2436 * @brief Set AHB prescaler
2437 * @rmtoll D1CFGR/CDCFGR1 HPRE LL_RCC_SetAHBPrescaler
2438 * @param Prescaler This parameter can be one of the following values:
2439 * @arg @ref LL_RCC_AHB_DIV_1
2440 * @arg @ref LL_RCC_AHB_DIV_2
2441 * @arg @ref LL_RCC_AHB_DIV_4
2442 * @arg @ref LL_RCC_AHB_DIV_8
2443 * @arg @ref LL_RCC_AHB_DIV_16
2444 * @arg @ref LL_RCC_AHB_DIV_64
2445 * @arg @ref LL_RCC_AHB_DIV_128
2446 * @arg @ref LL_RCC_AHB_DIV_256
2447 * @arg @ref LL_RCC_AHB_DIV_512
2448 * @retval None
2449 */
2450 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
2451 {
2452 #if defined(RCC_D1CFGR_HPRE)
2453 MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, Prescaler);
2454 #else
2455 MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, Prescaler);
2456 #endif /* RCC_D1CFGR_HPRE */
2457 }
2458
2459 /**
2460 * @brief Set APB1 prescaler
2461 * @rmtoll D2CFGR/CDCFGR2 D2PPRE1/CDPPRE1 LL_RCC_SetAPB1Prescaler
2462 * @param Prescaler This parameter can be one of the following values:
2463 * @arg @ref LL_RCC_APB1_DIV_1
2464 * @arg @ref LL_RCC_APB1_DIV_2
2465 * @arg @ref LL_RCC_APB1_DIV_4
2466 * @arg @ref LL_RCC_APB1_DIV_8
2467 * @arg @ref LL_RCC_APB1_DIV_16
2468 * @retval None
2469 */
2470 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
2471 {
2472 #if defined(RCC_D2CFGR_D2PPRE1)
2473 MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, Prescaler);
2474 #else
2475 MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, Prescaler);
2476 #endif /* RCC_D2CFGR_D2PPRE1 */
2477 }
2478
2479 /**
2480 * @brief Set APB2 prescaler
2481 * @rmtoll D2CFGR/CDCFGR2 D2PPRE2/CDPPRE2 LL_RCC_SetAPB2Prescaler
2482 * @param Prescaler This parameter can be one of the following values:
2483 * @arg @ref LL_RCC_APB2_DIV_1
2484 * @arg @ref LL_RCC_APB2_DIV_2
2485 * @arg @ref LL_RCC_APB2_DIV_4
2486 * @arg @ref LL_RCC_APB2_DIV_8
2487 * @arg @ref LL_RCC_APB2_DIV_16
2488 * @retval None
2489 */
2490 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
2491 {
2492 #if defined(RCC_D2CFGR_D2PPRE2)
2493 MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, Prescaler);
2494 #else
2495 MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, Prescaler);
2496 #endif /* RCC_D2CFGR_D2PPRE2 */
2497 }
2498
2499 /**
2500 * @brief Set APB3 prescaler
2501 * @rmtoll D1CFGR/CDCFGR1 D1PPRE/CDPPRE LL_RCC_SetAPB3Prescaler
2502 * @param Prescaler This parameter can be one of the following values:
2503 * @arg @ref LL_RCC_APB3_DIV_1
2504 * @arg @ref LL_RCC_APB3_DIV_2
2505 * @arg @ref LL_RCC_APB3_DIV_4
2506 * @arg @ref LL_RCC_APB3_DIV_8
2507 * @arg @ref LL_RCC_APB3_DIV_16
2508 * @retval None
2509 */
2510 __STATIC_INLINE void LL_RCC_SetAPB3Prescaler(uint32_t Prescaler)
2511 {
2512 #if defined(RCC_D1CFGR_D1PPRE)
2513 MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, Prescaler);
2514 #else
2515 MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, Prescaler);
2516 #endif /* RCC_D1CFGR_D1PPRE */
2517 }
2518
2519 /**
2520 * @brief Set APB4 prescaler
2521 * @rmtoll D3CFGR/SRDCFGR D3PPRE/SRDPPRE LL_RCC_SetAPB4Prescaler
2522 * @param Prescaler This parameter can be one of the following values:
2523 * @arg @ref LL_RCC_APB4_DIV_1
2524 * @arg @ref LL_RCC_APB4_DIV_2
2525 * @arg @ref LL_RCC_APB4_DIV_4
2526 * @arg @ref LL_RCC_APB4_DIV_8
2527 * @arg @ref LL_RCC_APB4_DIV_16
2528 * @retval None
2529 */
2530 __STATIC_INLINE void LL_RCC_SetAPB4Prescaler(uint32_t Prescaler)
2531 {
2532 #if defined(RCC_D3CFGR_D3PPRE)
2533 MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, Prescaler);
2534 #else
2535 MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, Prescaler);
2536 #endif /* RCC_D3CFGR_D3PPRE */
2537 }
2538
2539 /**
2540 * @brief Get System prescaler
2541 * @rmtoll D1CFGR/CDCFGR1 D1CPRE/CDCPRE LL_RCC_GetSysPrescaler
2542 * @retval Returned value can be one of the following values:
2543 * @arg @ref LL_RCC_SYSCLK_DIV_1
2544 * @arg @ref LL_RCC_SYSCLK_DIV_2
2545 * @arg @ref LL_RCC_SYSCLK_DIV_4
2546 * @arg @ref LL_RCC_SYSCLK_DIV_8
2547 * @arg @ref LL_RCC_SYSCLK_DIV_16
2548 * @arg @ref LL_RCC_SYSCLK_DIV_64
2549 * @arg @ref LL_RCC_SYSCLK_DIV_128
2550 * @arg @ref LL_RCC_SYSCLK_DIV_256
2551 * @arg @ref LL_RCC_SYSCLK_DIV_512
2552 */
2553 __STATIC_INLINE uint32_t LL_RCC_GetSysPrescaler(void)
2554 {
2555 #if defined(RCC_D1CFGR_D1CPRE)
2556 return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_D1CPRE));
2557 #else
2558 return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE));
2559 #endif /* RCC_D1CFGR_D1CPRE */
2560 }
2561
2562 /**
2563 * @brief Get AHB prescaler
2564 * @rmtoll D1CFGR/ CDCFGR1 HPRE LL_RCC_GetAHBPrescaler
2565 * @retval Returned value can be one of the following values:
2566 * @arg @ref LL_RCC_AHB_DIV_1
2567 * @arg @ref LL_RCC_AHB_DIV_2
2568 * @arg @ref LL_RCC_AHB_DIV_4
2569 * @arg @ref LL_RCC_AHB_DIV_8
2570 * @arg @ref LL_RCC_AHB_DIV_16
2571 * @arg @ref LL_RCC_AHB_DIV_64
2572 * @arg @ref LL_RCC_AHB_DIV_128
2573 * @arg @ref LL_RCC_AHB_DIV_256
2574 * @arg @ref LL_RCC_AHB_DIV_512
2575 */
2576 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
2577 {
2578 #if defined(RCC_D1CFGR_HPRE)
2579 return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_HPRE));
2580 #else
2581 return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_HPRE));
2582 #endif /* RCC_D1CFGR_HPRE */
2583 }
2584
2585 /**
2586 * @brief Get APB1 prescaler
2587 * @rmtoll D2CFGR/CDCFGR2 D2PPRE1/CDPPRE1 LL_RCC_GetAPB1Prescaler
2588 * @retval Returned value can be one of the following values:
2589 * @arg @ref LL_RCC_APB1_DIV_1
2590 * @arg @ref LL_RCC_APB1_DIV_2
2591 * @arg @ref LL_RCC_APB1_DIV_4
2592 * @arg @ref LL_RCC_APB1_DIV_8
2593 * @arg @ref LL_RCC_APB1_DIV_16
2594 */
2595 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
2596 {
2597 #if defined(RCC_D2CFGR_D2PPRE1)
2598 return (uint32_t)(READ_BIT(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1));
2599 #else
2600 return (uint32_t)(READ_BIT(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1));
2601 #endif /* RCC_D2CFGR_D2PPRE1 */
2602 }
2603
2604 /**
2605 * @brief Get APB2 prescaler
2606 * @rmtoll D2CFGR/CDCFGR2 D2PPRE2/CDPPRE2 LL_RCC_GetAPB2Prescaler
2607 * @retval Returned value can be one of the following values:
2608 * @arg @ref LL_RCC_APB2_DIV_1
2609 * @arg @ref LL_RCC_APB2_DIV_2
2610 * @arg @ref LL_RCC_APB2_DIV_4
2611 * @arg @ref LL_RCC_APB2_DIV_8
2612 * @arg @ref LL_RCC_APB2_DIV_16
2613 */
2614 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
2615 {
2616 #if defined(RCC_D2CFGR_D2PPRE2)
2617 return (uint32_t)(READ_BIT(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2));
2618 #else
2619 return (uint32_t)(READ_BIT(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2));
2620 #endif /* RCC_D2CFGR_D2PPRE2 */
2621 }
2622
2623 /**
2624 * @brief Get APB3 prescaler
2625 * @rmtoll D1CFGR/CDCFGR1 D1PPRE/CDPPRE LL_RCC_GetAPB3Prescaler
2626 * @retval Returned value can be one of the following values:
2627 * @arg @ref LL_RCC_APB3_DIV_1
2628 * @arg @ref LL_RCC_APB3_DIV_2
2629 * @arg @ref LL_RCC_APB3_DIV_4
2630 * @arg @ref LL_RCC_APB3_DIV_8
2631 * @arg @ref LL_RCC_APB3_DIV_16
2632 */
2633 __STATIC_INLINE uint32_t LL_RCC_GetAPB3Prescaler(void)
2634 {
2635 #if defined(RCC_D1CFGR_D1PPRE)
2636 return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_D1PPRE));
2637 #else
2638 return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE));
2639 #endif /* RCC_D1CFGR_D1PPRE */
2640 }
2641
2642 /**
2643 * @brief Get APB4 prescaler
2644 * @rmtoll D3CFGR/SRDCFGR D3PPRE/SRDPPRE LL_RCC_GetAPB4Prescaler
2645 * @retval Returned value can be one of the following values:
2646 * @arg @ref LL_RCC_APB4_DIV_1
2647 * @arg @ref LL_RCC_APB4_DIV_2
2648 * @arg @ref LL_RCC_APB4_DIV_4
2649 * @arg @ref LL_RCC_APB4_DIV_8
2650 * @arg @ref LL_RCC_APB4_DIV_16
2651 */
2652 __STATIC_INLINE uint32_t LL_RCC_GetAPB4Prescaler(void)
2653 {
2654 #if defined(RCC_D3CFGR_D3PPRE)
2655 return (uint32_t)(READ_BIT(RCC->D3CFGR, RCC_D3CFGR_D3PPRE));
2656 #else
2657 return (uint32_t)(READ_BIT(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE));
2658 #endif /* RCC_D3CFGR_D3PPRE */
2659 }
2660
2661 /**
2662 * @}
2663 */
2664
2665 /** @defgroup RCC_LL_EF_MCO MCO
2666 * @{
2667 */
2668
2669 /**
2670 * @brief Configure MCOx
2671 * @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n
2672 * CFGR MCO1PRE LL_RCC_ConfigMCO\n
2673 * CFGR MCO2 LL_RCC_ConfigMCO\n
2674 * CFGR MCO2PRE LL_RCC_ConfigMCO
2675 * @param MCOxSource This parameter can be one of the following values:
2676 * @arg @ref LL_RCC_MCO1SOURCE_HSI
2677 * @arg @ref LL_RCC_MCO1SOURCE_LSE
2678 * @arg @ref LL_RCC_MCO1SOURCE_HSE
2679 * @arg @ref LL_RCC_MCO1SOURCE_PLL1QCLK
2680 * @arg @ref LL_RCC_MCO1SOURCE_HSI48
2681 * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
2682 * @arg @ref LL_RCC_MCO2SOURCE_PLL2PCLK
2683 * @arg @ref LL_RCC_MCO2SOURCE_HSE
2684 * @arg @ref LL_RCC_MCO2SOURCE_PLL1PCLK
2685 * @arg @ref LL_RCC_MCO2SOURCE_CSI
2686 * @arg @ref LL_RCC_MCO2SOURCE_LSI
2687 * @param MCOxPrescaler This parameter can be one of the following values:
2688 * @arg @ref LL_RCC_MCO1_DIV_1
2689 * @arg @ref LL_RCC_MCO1_DIV_2
2690 * @arg @ref LL_RCC_MCO1_DIV_3
2691 * @arg @ref LL_RCC_MCO1_DIV_4
2692 * @arg @ref LL_RCC_MCO1_DIV_5
2693 * @arg @ref LL_RCC_MCO1_DIV_6
2694 * @arg @ref LL_RCC_MCO1_DIV_7
2695 * @arg @ref LL_RCC_MCO1_DIV_8
2696 * @arg @ref LL_RCC_MCO1_DIV_9
2697 * @arg @ref LL_RCC_MCO1_DIV_10
2698 * @arg @ref LL_RCC_MCO1_DIV_11
2699 * @arg @ref LL_RCC_MCO1_DIV_12
2700 * @arg @ref LL_RCC_MCO1_DIV_13
2701 * @arg @ref LL_RCC_MCO1_DIV_14
2702 * @arg @ref LL_RCC_MCO1_DIV_15
2703 * @arg @ref LL_RCC_MCO2_DIV_1
2704 * @arg @ref LL_RCC_MCO2_DIV_2
2705 * @arg @ref LL_RCC_MCO2_DIV_3
2706 * @arg @ref LL_RCC_MCO2_DIV_4
2707 * @arg @ref LL_RCC_MCO2_DIV_5
2708 * @arg @ref LL_RCC_MCO2_DIV_6
2709 * @arg @ref LL_RCC_MCO2_DIV_7
2710 * @arg @ref LL_RCC_MCO2_DIV_8
2711 * @arg @ref LL_RCC_MCO2_DIV_9
2712 * @arg @ref LL_RCC_MCO2_DIV_10
2713 * @arg @ref LL_RCC_MCO2_DIV_11
2714 * @arg @ref LL_RCC_MCO2_DIV_12
2715 * @arg @ref LL_RCC_MCO2_DIV_13
2716 * @arg @ref LL_RCC_MCO2_DIV_14
2717 * @arg @ref LL_RCC_MCO2_DIV_15
2718 * @retval None
2719 */
2720 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
2721 {
2722 MODIFY_REG(RCC->CFGR, (MCOxSource << 16U) | (MCOxPrescaler << 16U), (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U));
2723 }
2724
2725 /**
2726 * @}
2727 */
2728
2729 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
2730 * @{
2731 */
2732
2733 /**
2734 * @brief Configure periph clock source
2735 * @rmtoll D2CCIP1R/CDCCIP1R * LL_RCC_SetClockSource\n
2736 * D2CCIP2R/CDCCIP2R * LL_RCC_SetClockSource\n
2737 * D3CCIPR/SRDCCIPR * LL_RCC_SetClockSource
2738 * @param ClkSource This parameter can be one of the following values:
2739 * @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2
2740 * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q
2741 * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q
2742 * @arg @ref LL_RCC_USART16_CLKSOURCE_HSI
2743 * @arg @ref LL_RCC_USART16_CLKSOURCE_CSI
2744 * @arg @ref LL_RCC_USART16_CLKSOURCE_LSE
2745 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
2746 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
2747 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
2748 * @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
2749 * @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
2750 * @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
2751 * @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1
2752 * @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R
2753 * @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI
2754 * @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI
2755 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4
2756 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R
2757 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
2758 * @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI
2759 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
2760 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
2761 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
2762 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
2763 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
2764 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
2765 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
2766 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
2767 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R
2768 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
2769 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
2770 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
2771 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4
2772 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P
2773 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R
2774 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE
2775 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI
2776 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP
2777 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
2778 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
2779 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
2780 * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
2781 * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
2782 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q
2783 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P
2784 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P
2785 * @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN
2786 * @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP
2787 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
2788 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*)
2789 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*)
2790 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*)
2791 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*)
2792 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*)
2793 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*)
2794 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*)
2795 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP (*)
2796 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_SPDIF (*)
2797 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*)
2798 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)
2799 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
2800 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
2801 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
2802 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)
2803 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)
2804 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)
2805 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)
2806 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*)
2807 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*)
2808 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q
2809 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P
2810 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P
2811 * @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
2812 * @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP
2813 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
2814 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
2815 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
2816 * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
2817 * @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
2818 * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
2819 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
2820 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
2821 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
2822 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
2823 * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
2824 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
2825 * @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)
2826 *
2827 * (*) value not defined in all devices.
2828 * @retval None
2829 */
2830 __STATIC_INLINE void LL_RCC_SetClockSource(uint32_t ClkSource)
2831 {
2832 #if defined(RCC_D1CCIPR_FMCSEL)
2833 register uint32_t * pReg = (uint32_t *)((uint32_t)&RCC->D1CCIPR + LL_CLKSOURCE_REG(ClkSource));
2834 #else
2835 register uint32_t * pReg = (uint32_t *)((uint32_t)&RCC->CDCCIPR + LL_CLKSOURCE_REG(ClkSource));
2836 #endif /* */
2837 MODIFY_REG(*pReg, LL_CLKSOURCE_MASK(ClkSource), LL_CLKSOURCE_CONFIG(ClkSource));
2838 }
2839
2840 /**
2841 * @brief Configure USARTx clock source
2842 * @rmtoll D2CCIP2R / D2CCIP2R USART16SEL LL_RCC_SetUSARTClockSource\n
2843 * D2CCIP2R / D2CCIP2R USART28SEL LL_RCC_SetUSARTClockSource
2844 * @param ClkSource This parameter can be one of the following values:
2845 * @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2
2846 * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q
2847 * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q
2848 * @arg @ref LL_RCC_USART16_CLKSOURCE_HSI
2849 * @arg @ref LL_RCC_USART16_CLKSOURCE_CSI
2850 * @arg @ref LL_RCC_USART16_CLKSOURCE_LSE
2851 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
2852 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
2853 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
2854 * @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
2855 * @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
2856 * @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
2857 * @retval None
2858 */
2859 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t ClkSource)
2860 {
2861 LL_RCC_SetClockSource(ClkSource);
2862 }
2863
2864 /**
2865 * @brief Configure LPUARTx clock source
2866 * @rmtoll D3CCIPR / SRDCCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource
2867 * @param ClkSource This parameter can be one of the following values:
2868 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK4
2869 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q
2870 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q
2871 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
2872 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI
2873 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
2874 * @retval None
2875 */
2876 __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t ClkSource)
2877 {
2878 #if defined(RCC_D3CCIPR_LPUART1SEL)
2879 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, ClkSource);
2880 #else
2881 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, ClkSource);
2882 #endif /* RCC_D3CCIPR_LPUART1SEL */
2883 }
2884
2885 /**
2886 * @brief Configure I2Cx clock source
2887 * @rmtoll D2CCIP2R / CDCCIP2R I2C123SEL LL_RCC_SetI2CClockSource\n
2888 * D3CCIPR / SRDCCIPR I2C4SEL LL_RCC_SetI2CClockSource
2889 * @param ClkSource This parameter can be one of the following values:
2890 * @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1
2891 * @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R
2892 * @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI
2893 * @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI
2894 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4
2895 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R
2896 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
2897 * @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI
2898 * @retval None
2899 */
2900 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t ClkSource)
2901 {
2902 LL_RCC_SetClockSource(ClkSource);
2903 }
2904
2905 /**
2906 * @brief Configure LPTIMx clock source
2907 * @rmtoll D2CCIP2R / CDCCIP2R LPTIM1SEL LL_RCC_SetLPTIMClockSource
2908 * D3CCIPR / SRDCCIPR LPTIM2SEL LL_RCC_SetLPTIMClockSource\n
2909 * D3CCIPR / SRDCCIPR LPTIM345SEL LL_RCC_SetLPTIMClockSource
2910 * @param ClkSource This parameter can be one of the following values:
2911 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
2912 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
2913 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
2914 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
2915 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
2916 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
2917 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
2918 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
2919 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R
2920 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
2921 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
2922 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
2923 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4
2924 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P
2925 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R
2926 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE
2927 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI
2928 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP
2929 * @retval None
2930 */
2931 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t ClkSource)
2932 {
2933 LL_RCC_SetClockSource(ClkSource);
2934 }
2935
2936 /**
2937 * @brief Configure SAIx clock source
2938 * @rmtoll D2CCIP1R / CDCCIP1R SAI1SEL LL_RCC_SetSAIClockSource\n
2939 * D2CCIP1R / CDCCIP1R SAI23SEL LL_RCC_SetSAIClockSource
2940 * D3CCIPR / SRDCCIPR SAI4ASEL LL_RCC_SetSAI4xClockSource\n
2941 * D3CCIPR / SRDCCIPR SAI4BSEL LL_RCC_SetSAI4xClockSource
2942 * @param ClkSource This parameter can be one of the following values:
2943 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
2944 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
2945 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
2946 * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
2947 * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
2948 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q
2949 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P
2950 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P
2951 * @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN
2952 * @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP
2953 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
2954 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*)
2955 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*)
2956 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*)
2957 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*)
2958 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*)
2959 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*)
2960 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*)
2961 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP (*)
2962 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_SPDIF (*)
2963 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*)
2964 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)
2965 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
2966 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
2967 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
2968 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)
2969 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)
2970 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)
2971 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)
2972 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*)
2973 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*)
2974 *
2975 * (*) value not defined in all devices.
2976 * @retval None
2977 */
2978 __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t ClkSource)
2979 {
2980 LL_RCC_SetClockSource(ClkSource);
2981 }
2982
2983 /**
2984 * @brief Configure SDMMCx clock source
2985 * @rmtoll D1CCIPR / CDCCIPR SDMMCSEL LL_RCC_SetSDMMCClockSource
2986 * @param ClkSource This parameter can be one of the following values:
2987 * @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL1Q
2988 * @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL2R
2989 * @retval None
2990 */
2991 __STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t ClkSource)
2992 {
2993 #if defined(RCC_D1CCIPR_SDMMCSEL)
2994 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, ClkSource);
2995 #else
2996 MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL, ClkSource);
2997 #endif /* RCC_D1CCIPR_SDMMCSEL */
2998 }
2999
3000 /**
3001 * @brief Configure RNGx clock source
3002 * @rmtoll D2CCIP2R / CDCCIP2R RNGSEL LL_RCC_SetRNGClockSource
3003 * @param ClkSource This parameter can be one of the following values:
3004 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
3005 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q
3006 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
3007 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
3008 * @retval None
3009 */
3010 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t ClkSource)
3011 {
3012 #if defined(RCC_D2CCIP2R_RNGSEL)
3013 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, ClkSource);
3014 #else
3015 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL, ClkSource);
3016 #endif /* RCC_D2CCIP2R_RNGSEL */
3017 }
3018
3019 /**
3020 * @brief Configure USBx clock source
3021 * @rmtoll D2CCIP2R / CDCCIP2R USBSEL LL_RCC_SetUSBClockSource
3022 * @param ClkSource This parameter can be one of the following values:
3023 * @arg @ref LL_RCC_USB_CLKSOURCE_DISABLE
3024 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL1Q
3025 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL3Q
3026 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
3027 * @retval None
3028 */
3029 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t ClkSource)
3030 {
3031 #if defined(RCC_D2CCIP2R_USBSEL)
3032 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, ClkSource);
3033 #else
3034 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL, ClkSource);
3035 #endif /* RCC_D2CCIP2R_USBSEL */
3036 }
3037
3038 /**
3039 * @brief Configure CECx clock source
3040 * @rmtoll D2CCIP2R / CDCCIP2R CECSEL LL_RCC_SetCECClockSource
3041 * @param ClkSource This parameter can be one of the following values:
3042 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
3043 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSI
3044 * @arg @ref LL_RCC_CEC_CLKSOURCE_CSI_DIV122
3045 * @retval None
3046 */
3047 __STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t ClkSource)
3048 {
3049 #if defined(RCC_D2CCIP2R_CECSEL)
3050 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, ClkSource);
3051 #else
3052 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL, ClkSource);
3053 #endif /* RCC_D2CCIP2R_CECSEL */
3054 }
3055
3056 #if defined(DSI)
3057 /**
3058 * @brief Configure DSIx clock source
3059 * @rmtoll D1CCIPR DSISEL LL_RCC_SetDSIClockSource
3060 * @param ClkSource This parameter can be one of the following values:
3061 * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
3062 * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL2Q
3063 * @retval None
3064 */
3065 __STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t ClkSource)
3066 {
3067 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL, ClkSource);
3068 }
3069 #endif /* DSI */
3070
3071 /**
3072 * @brief Configure DFSDMx Kernel clock source
3073 * @rmtoll D2CCIP1R / CDCCIP1R DFSDM1SEL LL_RCC_SetDFSDMClockSource
3074 * @param ClkSource This parameter can be one of the following values:
3075 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
3076 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
3077 * @retval None
3078 */
3079 __STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t ClkSource)
3080 {
3081 #if defined(RCC_D2CCIP1R_DFSDM1SEL)
3082 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, ClkSource);
3083 #else
3084 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, ClkSource);
3085 #endif /* RCC_D2CCIP1R_DFSDM1SEL */
3086 }
3087
3088 #if defined(DFSDM2_BASE)
3089 /**
3090 * @brief Configure DFSDMx Kernel clock source
3091 * @rmtoll SRDCCIPR DFSDM2SEL LL_RCC_SetDFSDM2ClockSource
3092 * @param ClkSource This parameter can be one of the following values:
3093 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2
3094 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK
3095 * @retval None
3096 */
3097 __STATIC_INLINE void LL_RCC_SetDFSDM2ClockSource(uint32_t ClkSource)
3098 {
3099 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, ClkSource);
3100 }
3101 #endif /* DFSDM2 */
3102
3103 /**
3104 * @brief Configure FMCx Kernel clock source
3105 * @rmtoll D1CCIPR / CDCCIPR FMCSEL LL_RCC_SetFMCClockSource
3106 * @param ClkSource This parameter can be one of the following values:
3107 * @arg @ref LL_RCC_FMC_CLKSOURCE_HCLK
3108 * @arg @ref LL_RCC_FMC_CLKSOURCE_PLL1Q
3109 * @arg @ref LL_RCC_FMC_CLKSOURCE_PLL2R
3110 * @arg @ref LL_RCC_FMC_CLKSOURCE_CLKP
3111 * @retval None
3112 */
3113 __STATIC_INLINE void LL_RCC_SetFMCClockSource(uint32_t ClkSource)
3114 {
3115 #if defined(RCC_D1CCIPR_FMCSEL)
3116 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, ClkSource);
3117 #else
3118 MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL, ClkSource);
3119 #endif /* RCC_D1CCIPR_FMCSEL */
3120 }
3121
3122 #if defined(QUADSPI)
3123 /**
3124 * @brief Configure QSPIx Kernel clock source
3125 * @rmtoll D1CCIPR QSPISEL LL_RCC_SetQSPIClockSource
3126 * @param ClkSource This parameter can be one of the following values:
3127 * @arg @ref LL_RCC_QSPI_CLKSOURCE_HCLK
3128 * @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL1Q
3129 * @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL2R
3130 * @arg @ref LL_RCC_QSPI_CLKSOURCE_CLKP
3131 * @retval None
3132 */
3133 __STATIC_INLINE void LL_RCC_SetQSPIClockSource(uint32_t ClkSource)
3134 {
3135 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL, ClkSource);
3136 }
3137 #endif /* QUADSPI */
3138
3139 #if defined(OCTOSPI1) || defined(OCTOSPI2)
3140 /**
3141 * @brief Configure OSPIx Kernel clock source
3142 * @rmtoll D1CCIPR OPISEL LL_RCC_SetOSPIClockSource
3143 * @param ClkSource This parameter can be one of the following values:
3144 * @arg @ref LL_RCC_OSPI_CLKSOURCE_HCLK
3145 * @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL1Q
3146 * @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL2R
3147 * @arg @ref LL_RCC_OSPI_CLKSOURCE_CLKP
3148 * @retval None
3149 */
3150 __STATIC_INLINE void LL_RCC_SetOSPIClockSource(uint32_t ClkSource)
3151 {
3152 MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL, ClkSource);
3153 }
3154 #endif /* OCTOSPI1 || OCTOSPI2 */
3155
3156 /**
3157 * @brief Configure CLKP Kernel clock source
3158 * @rmtoll D1CCIPR / CDCCIPR CKPERSEL LL_RCC_SetCLKPClockSource
3159 * @param ClkSource This parameter can be one of the following values:
3160 * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI
3161 * @arg @ref LL_RCC_CLKP_CLKSOURCE_CSI
3162 * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE
3163 * @retval None
3164 */
3165 __STATIC_INLINE void LL_RCC_SetCLKPClockSource(uint32_t ClkSource)
3166 {
3167 #if defined(RCC_D1CCIPR_CKPERSEL)
3168 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, ClkSource);
3169 #else
3170 MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL, ClkSource);
3171 #endif /* RCC_D1CCIPR_CKPERSEL */
3172 }
3173
3174 /**
3175 * @brief Configure SPIx Kernel clock source
3176 * @rmtoll D2CCIP1R / CDCCIP1R SPI123SEL LL_RCC_SetSPIClockSource\n
3177 * D2CCIP1R / CDCCIP1R SPI45SEL LL_RCC_SetSPIClockSource\n
3178 * D3CCIPR / SRDCCIPR SPI6SEL LL_RCC_SetSPIClockSource
3179 * @param ClkSource This parameter can be one of the following values:
3180 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q
3181 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P
3182 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P
3183 * @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
3184 * @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP
3185 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
3186 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
3187 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
3188 * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
3189 * @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
3190 * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
3191 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
3192 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
3193 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
3194 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
3195 * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
3196 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
3197 * @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)
3198 *
3199 * (*) value not defined in all devices.
3200 * @retval None
3201 */
3202 __STATIC_INLINE void LL_RCC_SetSPIClockSource(uint32_t ClkSource)
3203 {
3204 LL_RCC_SetClockSource(ClkSource);
3205 }
3206
3207 /**
3208 * @brief Configure SPDIFx Kernel clock source
3209 * @rmtoll D2CCIP1R / CDCCIP1R SPDIFSEL LL_RCC_SetSPDIFClockSource
3210 * @param ClkSource This parameter can be one of the following values:
3211 * @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL1Q
3212 * @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL2R
3213 * @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL3R
3214 * @arg @ref LL_RCC_SPDIF_CLKSOURCE_HSI
3215 * @retval None
3216 */
3217 __STATIC_INLINE void LL_RCC_SetSPDIFClockSource(uint32_t ClkSource)
3218 {
3219 #if defined(RCC_D2CCIP1R_SPDIFSEL)
3220 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, ClkSource);
3221 #else
3222 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, ClkSource);
3223 #endif /* RCC_D2CCIP1R_SPDIFSEL */
3224 }
3225
3226 /**
3227 * @brief Configure FDCANx Kernel clock source
3228 * @rmtoll D2CCIP1R / CDCCIP1R FDCANSEL LL_RCC_SetFDCANClockSource
3229 * @param ClkSource This parameter can be one of the following values:
3230 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
3231 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1Q
3232 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2Q
3233 * @retval None
3234 */
3235 __STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t ClkSource)
3236 {
3237 #if defined(RCC_D2CCIP1R_FDCANSEL)
3238 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, ClkSource);
3239 #else
3240 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL, ClkSource);
3241 #endif /* RCC_D2CCIP1R_FDCANSEL */
3242 }
3243
3244 /**
3245 * @brief Configure SWPx Kernel clock source
3246 * @rmtoll D2CCIP1R / CDCCIP1R SWPSEL LL_RCC_SetSWPClockSource
3247 * @param ClkSource This parameter can be one of the following values:
3248 * @arg @ref LL_RCC_SWP_CLKSOURCE_PCLK1
3249 * @arg @ref LL_RCC_SWP_CLKSOURCE_HSI
3250 * @retval None
3251 */
3252 __STATIC_INLINE void LL_RCC_SetSWPClockSource(uint32_t ClkSource)
3253 {
3254 #if defined(RCC_D2CCIP1R_SWPSEL)
3255 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, ClkSource);
3256 #else
3257 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL, ClkSource);
3258 #endif /* RCC_D2CCIP1R_SWPSEL */
3259 }
3260
3261 /**
3262 * @brief Configure ADCx Kernel clock source
3263 * @rmtoll D3CCIPR / SRDCCIPR ADCSEL LL_RCC_SetADCClockSource
3264 * @param ClkSource This parameter can be one of the following values:
3265 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL2P
3266 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL3R
3267 * @arg @ref LL_RCC_ADC_CLKSOURCE_CLKP
3268 * @retval None
3269 */
3270 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ClkSource)
3271 {
3272 #if defined(RCC_D3CCIPR_ADCSEL)
3273 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, ClkSource);
3274 #else
3275 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL, ClkSource);
3276 #endif /* RCC_D3CCIPR_ADCSEL */
3277 }
3278
3279 /**
3280 * @brief Get periph clock source
3281 * @rmtoll D1CCIPR / CDCCIPR * LL_RCC_GetClockSource\n
3282 * D2CCIP1R / CDCCIP1R * LL_RCC_GetClockSource\n
3283 * D2CCIP2R / CDCCIP2R * LL_RCC_GetClockSource\n
3284 * D3CCIPR / SRDCCIPR * LL_RCC_GetClockSource
3285 * @param Periph This parameter can be one of the following values:
3286 * @arg @ref LL_RCC_USART16_CLKSOURCE
3287 * @arg @ref LL_RCC_USART234578_CLKSOURCE
3288 * @arg @ref LL_RCC_I2C123_CLKSOURCE
3289 * @arg @ref LL_RCC_I2C4_CLKSOURCE
3290 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
3291 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
3292 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE
3293 * @arg @ref LL_RCC_SAI1_CLKSOURCE
3294 * @arg @ref LL_RCC_SAI23_CLKSOURCE
3295 * @arg @ref LL_RCC_SAI4A_CLKSOURCE (*)
3296 * @arg @ref LL_RCC_SAI4B_CLKSOURCE (*)
3297 * @arg @ref LL_RCC_SAI2A_CLKSOURCE (*)
3298 * @arg @ref LL_RCC_SAI2B_CLKSOURCE (*)
3299 * @arg @ref LL_RCC_SPI123_CLKSOURCE (*)
3300 * @arg @ref LL_RCC_SPI45_CLKSOURCE (*)
3301 * @arg @ref LL_RCC_SPI6_CLKSOURCE (*)
3302 * @retval Returned value can be one of the following values:
3303 * @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2
3304 * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q
3305 * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q
3306 * @arg @ref LL_RCC_USART16_CLKSOURCE_HSI
3307 * @arg @ref LL_RCC_USART16_CLKSOURCE_CSI
3308 * @arg @ref LL_RCC_USART16_CLKSOURCE_LSE
3309 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
3310 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
3311 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
3312 * @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
3313 * @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
3314 * @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
3315 * @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1
3316 * @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R
3317 * @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI
3318 * @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI
3319 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4
3320 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R
3321 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
3322 * @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI
3323 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
3324 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
3325 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
3326 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
3327 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
3328 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
3329 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
3330 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
3331 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R
3332 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
3333 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
3334 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
3335 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4
3336 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P
3337 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R
3338 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE
3339 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI
3340 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP
3341 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
3342 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
3343 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
3344 * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
3345 * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
3346 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*)
3347 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*)
3348 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*)
3349 * @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*)
3350 * @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*)
3351 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
3352 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*)
3353 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*)
3354 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*)
3355 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_CLKP (*)
3356 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*)
3357 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)
3358 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
3359 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
3360 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
3361 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*)
3362 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*)
3363 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*)
3364 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*)
3365 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP (*)
3366 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*)
3367 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)
3368 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)
3369 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)
3370 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)
3371 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*)
3372 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*)
3373 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q
3374 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P
3375 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P
3376 * @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
3377 * @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP
3378 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
3379 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
3380 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
3381 * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
3382 * @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
3383 * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
3384 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
3385 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
3386 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
3387 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
3388 * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
3389 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
3390 * @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)
3391 *
3392 * (*) value not defined in all devices.
3393 * @retval None
3394 */
3395 __STATIC_INLINE uint32_t LL_RCC_GetClockSource(uint32_t Periph)
3396 {
3397 #if defined(RCC_D1CCIPR_FMCSEL)
3398 register const uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->D1CCIPR) + LL_CLKSOURCE_REG(Periph)));
3399 #else
3400 register const uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->CDCCIPR) + LL_CLKSOURCE_REG(Periph)));
3401 #endif /* RCC_D1CCIPR_FMCSEL */
3402 return (uint32_t) (Periph | (((READ_BIT(*pReg, LL_CLKSOURCE_MASK(Periph))) >> LL_CLKSOURCE_SHIFT(Periph)) << LL_RCC_CONFIG_SHIFT) );
3403 }
3404
3405 /**
3406 * @brief Get USARTx clock source
3407 * @rmtoll D2CCIP2R / CDCCIP2R USART16SEL LL_RCC_GetUSARTClockSource\n
3408 * D2CCIP2R / CDCCIP2R USART28SEL LL_RCC_GetUSARTClockSource
3409 * @param Periph This parameter can be one of the following values:
3410 * @arg @ref LL_RCC_USART16_CLKSOURCE
3411 * @arg @ref LL_RCC_USART234578_CLKSOURCE
3412 * @retval Returned value can be one of the following values:
3413 * @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2
3414 * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q
3415 * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q
3416 * @arg @ref LL_RCC_USART16_CLKSOURCE_HSI
3417 * @arg @ref LL_RCC_USART16_CLKSOURCE_CSI
3418 * @arg @ref LL_RCC_USART16_CLKSOURCE_LSE
3419 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
3420 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
3421 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
3422 * @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
3423 * @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
3424 * @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
3425 */
3426 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t Periph)
3427 {
3428 return LL_RCC_GetClockSource(Periph);
3429 }
3430
3431 /**
3432 * @brief Get LPUART clock source
3433 * @rmtoll D3CCIPR / SRDCCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource
3434 * @param Periph This parameter can be one of the following values:
3435 * @arg @ref LL_RCC_LPUART1_CLKSOURCE
3436 * @retval Returned value can be one of the following values:
3437 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK4
3438 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q
3439 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q
3440 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
3441 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI
3442 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
3443 */
3444 __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t Periph)
3445 {
3446 UNUSED(Periph);
3447 #if defined(RCC_D3CCIPR_LPUART1SEL)
3448 return (uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL));
3449 #else
3450 return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL));
3451 #endif /* RCC_D3CCIPR_LPUART1SEL */
3452 }
3453
3454 /**
3455 * @brief Get I2Cx clock source
3456 * @rmtoll D2CCIP2R / CDCCIP2R I2C123SEL LL_RCC_GetI2CClockSource\n
3457 * D3CCIPR / SRDCCIPR I2C4SEL LL_RCC_GetI2CClockSource
3458 * @param Periph This parameter can be one of the following values:
3459 * @arg @ref LL_RCC_I2C123_CLKSOURCE
3460 * @arg @ref LL_RCC_I2C4_CLKSOURCE
3461 * @retval Returned value can be one of the following values:
3462 * @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1
3463 * @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R
3464 * @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI
3465 * @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI
3466 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4
3467 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R
3468 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
3469 * @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI
3470 */
3471 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t Periph)
3472 {
3473 return LL_RCC_GetClockSource(Periph);
3474 }
3475
3476 /**
3477 * @brief Get LPTIM clock source
3478 * @rmtoll D2CCIP2R / CDCCIP2R LPTIM1SEL LL_RCC_GetLPTIMClockSource\n
3479 * D3CCIPR / SRDCCIPR LPTIM2SEL LL_RCC_GetLPTIMClockSource\n
3480 * D3CCIPR / SRDCCIPR LPTIM345SEL LL_RCC_GetLPTIMClockSource
3481 * @param Perihp This parameter can be one of the following values:
3482 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
3483 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
3484 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE
3485 * @retval Returned value can be one of the following values:
3486 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
3487 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
3488 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
3489 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
3490 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
3491 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
3492 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
3493 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
3494 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R
3495 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
3496 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
3497 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
3498 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4
3499 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P
3500 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R
3501 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE
3502 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI
3503 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP
3504 * @retval None
3505 */
3506 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t Periph)
3507 {
3508 return LL_RCC_GetClockSource(Periph);
3509 }
3510
3511 /**
3512 * @brief Get SAIx clock source
3513 * @rmtoll D2CCIP1R / CDCCIP1R SAI1SEL LL_RCC_GetSAIClockSource\n
3514 * D2CCIP1R / CDCCIP1R SAI23SEL LL_RCC_GetSAIClockSource
3515 * D3CCIPR / SRDCCIPR SAI4ASEL LL_RCC_GetSAIClockSource\n
3516 * D3CCIPR / SRDCCIPR SAI4BSEL LL_RCC_GetSAIClockSource
3517 * @param Periph This parameter can be one of the following values:
3518 * @arg @ref LL_RCC_SAI1_CLKSOURCE
3519 * @arg @ref LL_RCC_SAI23_CLKSOURCE
3520 * @arg @ref LL_RCC_SAI4A_CLKSOURCE
3521 * @arg @ref LL_RCC_SAI4B_CLKSOURCE
3522 * @retval Returned value can be one of the following values:
3523 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
3524 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
3525 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
3526 * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
3527 * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
3528 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*)
3529 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*)
3530 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*)
3531 * @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*)
3532 * @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*)
3533 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*)
3534 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*)
3535 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*)
3536 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*)
3537 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP (*)
3538 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_SPDIF (*)
3539 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)
3540 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)
3541 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)
3542 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)
3543 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*)
3544 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*)
3545 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
3546 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*)
3547 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*)
3548 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*)
3549 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_CLKP (*)
3550 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*)
3551 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)
3552 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
3553 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
3554 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
3555 *
3556 * (*) value not defined in all devices.
3557 */
3558 __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t Periph)
3559 {
3560 return LL_RCC_GetClockSource(Periph);
3561 }
3562
3563 /**
3564 * @brief Get SDMMC clock source
3565 * @rmtoll D1CCIPR / CDCCIPR SDMMCSEL LL_RCC_GetSDMMCClockSource
3566 * @param Periph This parameter can be one of the following values:
3567 * @arg @ref LL_RCC_SDMMC_CLKSOURCE
3568 * @retval Returned value can be one of the following values:
3569 * @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL1Q
3570 * @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL2R
3571 */
3572 __STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t Periph)
3573 {
3574 UNUSED(Periph);
3575 #if defined(RCC_D1CCIPR_SDMMCSEL)
3576 return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL));
3577 #else
3578 return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL));
3579 #endif /* RCC_D1CCIPR_SDMMCSEL */
3580 }
3581
3582 /**
3583 * @brief Get RNG clock source
3584 * @rmtoll D2CCIP2R RNGSEL LL_RCC_GetRNGClockSource
3585 * @param Periph This parameter can be one of the following values:
3586 * @arg @ref LL_RCC_RNG_CLKSOURCE
3587 * @retval Returned value can be one of the following values:
3588 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
3589 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q
3590 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
3591 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
3592 */
3593 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t Periph)
3594 {
3595 UNUSED(Periph);
3596 #if defined(RCC_D2CCIP2R_RNGSEL)
3597 return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL));
3598 #else
3599 return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL));
3600 #endif /* RCC_D2CCIP2R_RNGSEL */
3601 }
3602
3603 /**
3604 * @brief Get USB clock source
3605 * @rmtoll D2CCIP2R / CDCCIP2R USBSEL LL_RCC_GetUSBClockSource
3606 * @param Periph This parameter can be one of the following values:
3607 * @arg @ref LL_RCC_USB_CLKSOURCE
3608 * @retval Returned value can be one of the following values:
3609 * @arg @ref LL_RCC_USB_CLKSOURCE_DISABLE
3610 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL1Q
3611 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL3Q
3612 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
3613 */
3614 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t Periph)
3615 {
3616 UNUSED(Periph);
3617 #if defined(RCC_D2CCIP2R_USBSEL)
3618 return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL));
3619 #else
3620 return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL));
3621 #endif /* RCC_D2CCIP2R_USBSEL */
3622 }
3623
3624 /**
3625 * @brief Get CEC clock source
3626 * @rmtoll D2CCIP2R / CDCCIP2R CECSEL LL_RCC_GetCECClockSource
3627 * @param Periph This parameter can be one of the following values:
3628 * @arg @ref LL_RCC_CEC_CLKSOURCE
3629 * @retval Returned value can be one of the following values:
3630 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
3631 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSI
3632 * @arg @ref LL_RCC_CEC_CLKSOURCE_CSI_DIV122
3633 */
3634 __STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t Periph)
3635 {
3636 UNUSED(Periph);
3637 #if defined(RCC_D2CCIP2R_CECSEL)
3638 return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL));
3639 #else
3640 return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL));
3641 #endif /* RCC_D2CCIP2R_CECSEL */
3642 }
3643
3644 #if defined(DSI)
3645 /**
3646 * @brief Get DSI clock source
3647 * @rmtoll D1CCIPR DSISEL LL_RCC_GetDSIClockSource
3648 * @param Periph This parameter can be one of the following values:
3649 * @arg @ref LL_RCC_DSI_CLKSOURCE
3650 * @retval Returned value can be one of the following values:
3651 * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
3652 * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL2Q
3653 */
3654 __STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t Periph)
3655 {
3656 UNUSED(Periph);
3657 return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL));
3658 }
3659 #endif /* DSI */
3660
3661 /**
3662 * @brief Get DFSDM Kernel clock source
3663 * @rmtoll D2CCIP1R / CDCCIP1R DFSDM1SEL LL_RCC_GetDFSDMClockSource
3664 * @param Periph This parameter can be one of the following values:
3665 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE
3666 * @retval Returned value can be one of the following values:
3667 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
3668 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
3669 */
3670 __STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t Periph)
3671 {
3672 UNUSED(Periph);
3673 #if defined(RCC_D2CCIP1R_DFSDM1SEL)
3674 return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL));
3675 #else
3676 return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL));
3677 #endif /* RCC_D2CCIP1R_DFSDM1SEL */
3678 }
3679
3680 #if defined(DFSDM2_BASE)
3681 /**
3682 * @brief Get DFSDM2 Kernel clock source
3683 * @rmtoll SRDCCIPR DFSDM2SEL LL_RCC_GetDFSDM2ClockSource
3684 * @param Periph This parameter can be one of the following values:
3685 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE
3686 * @retval Returned value can be one of the following values:
3687 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK4
3688 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK
3689 */
3690 __STATIC_INLINE uint32_t LL_RCC_GetDFSDM2ClockSource(uint32_t Periph)
3691 {
3692 UNUSED(Periph);
3693 return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL));
3694 }
3695 #endif /* DFSDM2_BASE */
3696
3697 /**
3698 * @brief Get FMC Kernel clock source
3699 * @rmtoll D1CCIPR / D1CCIPR FMCSEL LL_RCC_GetFMCClockSource
3700 * @param Periph This parameter can be one of the following values:
3701 * @arg @ref LL_RCC_FMC_CLKSOURCE
3702 * @retval Returned value can be one of the following values:
3703 * @arg @ref LL_RCC_FMC_CLKSOURCE_HCLK
3704 * @arg @ref LL_RCC_FMC_CLKSOURCE_PLL1Q
3705 * @arg @ref LL_RCC_FMC_CLKSOURCE_PLL2R
3706 * @arg @ref LL_RCC_FMC_CLKSOURCE_CLKP
3707 */
3708 __STATIC_INLINE uint32_t LL_RCC_GetFMCClockSource(uint32_t Periph)
3709 {
3710 UNUSED(Periph);
3711 #if defined(RCC_D1CCIPR_FMCSEL)
3712 return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL));
3713 #else
3714 return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL));
3715 #endif /* RCC_D1CCIPR_FMCSEL */
3716 }
3717
3718 #if defined(QUADSPI)
3719 /**
3720 * @brief Get QSPI Kernel clock source
3721 * @rmtoll D1CCIPR / CDCCIPR QSPISEL LL_RCC_GetQSPIClockSource
3722 * @param Periph This parameter can be one of the following values:
3723 * @arg @ref LL_RCC_QSPI_CLKSOURCE
3724 * @retval Returned value can be one of the following values:
3725 * @arg @ref LL_RCC_QSPI_CLKSOURCE_HCLK
3726 * @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL1Q
3727 * @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL2R
3728 * @arg @ref LL_RCC_QSPI_CLKSOURCE_CLKP
3729 */
3730 __STATIC_INLINE uint32_t LL_RCC_GetQSPIClockSource(uint32_t Periph)
3731 {
3732 UNUSED(Periph);
3733 return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL));
3734 }
3735 #endif /* QUADSPI */
3736
3737 #if defined(OCTOSPI1) || defined(OCTOSPI2)
3738 /**
3739 * @brief Get OSPI Kernel clock source
3740 * @rmtoll CDCCIPR OSPISEL LL_RCC_GetOSPIClockSource
3741 * @param Periph This parameter can be one of the following values:
3742 * @arg @ref LL_RCC_OSPI_CLKSOURCE
3743 * @retval Returned value can be one of the following values:
3744 * @arg @ref LL_RCC_OSPI_CLKSOURCE_HCLK
3745 * @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL1Q
3746 * @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL2R
3747 * @arg @ref LL_RCC_OSPI_CLKSOURCE_CLKP
3748 */
3749 __STATIC_INLINE uint32_t LL_RCC_GetOSPIClockSource(uint32_t Periph)
3750 {
3751 UNUSED(Periph);
3752 return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL));
3753 }
3754 #endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
3755
3756 /**
3757 * @brief Get CLKP Kernel clock source
3758 * @rmtoll D1CCIPR / CDCCIPR CKPERSEL LL_RCC_GetCLKPClockSource
3759 * @param Periph This parameter can be one of the following values:
3760 * @arg @ref LL_RCC_CLKP_CLKSOURCE
3761 * @retval Returned value can be one of the following values:
3762 * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI
3763 * @arg @ref LL_RCC_CLKP_CLKSOURCE_CSI
3764 * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE
3765 */
3766 __STATIC_INLINE uint32_t LL_RCC_GetCLKPClockSource(uint32_t Periph)
3767 {
3768 UNUSED(Periph);
3769 #if defined(RCC_D1CCIPR_CKPERSEL)
3770 return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL));
3771 #else
3772 return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL));
3773 #endif /* RCC_D1CCIPR_CKPERSEL */
3774 }
3775
3776 /**
3777 * @brief Get SPIx Kernel clock source
3778 * @rmtoll D2CCIP1R / CDCCIP1R SPI123SEL LL_RCC_GetSPIClockSource\n
3779 * D2CCIP1R / CDCCIP1R SPI45SEL LL_RCC_GetSPIClockSource\n
3780 * D3CCIPR / SRDCCIPR SPI6SEL LL_RCC_GetSPIClockSource
3781 * @param Periph This parameter can be one of the following values:
3782 * @arg @ref LL_RCC_SPI123_CLKSOURCE
3783 * @arg @ref LL_RCC_SPI45_CLKSOURCE
3784 * @arg @ref LL_RCC_SPI6_CLKSOURCE
3785 * @retval Returned value can be one of the following values:
3786 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q
3787 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P
3788 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P
3789 * @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
3790 * @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP
3791 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
3792 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
3793 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
3794 * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
3795 * @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
3796 * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
3797 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
3798 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
3799 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
3800 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
3801 * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
3802 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
3803 * @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)
3804 *
3805 * (*) value not defined in all stm32h7xx lines.
3806 */
3807 __STATIC_INLINE uint32_t LL_RCC_GetSPIClockSource(uint32_t Periph)
3808 {
3809 return LL_RCC_GetClockSource(Periph);
3810 }
3811
3812 /**
3813 * @brief Get SPDIF Kernel clock source
3814 * @rmtoll D2CCIP1R / CDCCIP1R SPDIFSEL LL_RCC_GetSPDIFClockSource
3815 * @param Periph This parameter can be one of the following values:
3816 * @arg @ref LL_RCC_SPDIF_CLKSOURCE
3817 * @retval Returned value can be one of the following values:
3818 * @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL1Q
3819 * @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL2R
3820 * @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL3R
3821 * @arg @ref LL_RCC_SPDIF_CLKSOURCE_HSI
3822 */
3823 __STATIC_INLINE uint32_t LL_RCC_GetSPDIFClockSource(uint32_t Periph)
3824 {
3825 UNUSED(Periph);
3826 #if defined(RCC_D2CCIP1R_SPDIFSEL)
3827 return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL));
3828 #else
3829 return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL));
3830 #endif /* RCC_D2CCIP1R_SPDIFSEL */
3831 }
3832
3833 /**
3834 * @brief Get FDCAN Kernel clock source
3835 * @rmtoll D2CCIP1R / CDCCIP1R FDCANSEL LL_RCC_GetFDCANClockSource
3836 * @param Periph This parameter can be one of the following values:
3837 * @arg @ref LL_RCC_FDCAN_CLKSOURCE
3838 * @retval Returned value can be one of the following values:
3839 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
3840 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1Q
3841 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2Q
3842 */
3843 __STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t Periph)
3844 {
3845 UNUSED(Periph);
3846 #if defined(RCC_D2CCIP1R_FDCANSEL)
3847 return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL));
3848 #else
3849 return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL));
3850 #endif /* RCC_D2CCIP1R_FDCANSEL */
3851 }
3852
3853 /**
3854 * @brief Get SWP Kernel clock source
3855 * @rmtoll D2CCIP1R / CDCCIP1R SWPSEL LL_RCC_GetSWPClockSource
3856 * @param Periph This parameter can be one of the following values:
3857 * @arg @ref LL_RCC_SWP_CLKSOURCE
3858 * @retval Returned value can be one of the following values:
3859 * @arg @ref LL_RCC_SWP_CLKSOURCE_PCLK1
3860 * @arg @ref LL_RCC_SWP_CLKSOURCE_HSI
3861 */
3862 __STATIC_INLINE uint32_t LL_RCC_GetSWPClockSource(uint32_t Periph)
3863 {
3864 UNUSED(Periph);
3865 #if defined(RCC_D2CCIP1R_SWPSEL)
3866 return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL));
3867 #else
3868 return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL));
3869 #endif /* RCC_D2CCIP1R_SWPSEL */
3870 }
3871
3872 /**
3873 * @brief Get ADC Kernel clock source
3874 * @rmtoll D3CCIPR / SRDCCIPR ADCSEL LL_RCC_GetADCClockSource
3875 * @param Periph This parameter can be one of the following values:
3876 * @arg @ref LL_RCC_ADC_CLKSOURCE
3877 * @retval Returned value can be one of the following values:
3878 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL2P
3879 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL3R
3880 * @arg @ref LL_RCC_ADC_CLKSOURCE_CLKP
3881 */
3882 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t Periph)
3883 {
3884 UNUSED(Periph);
3885 #if defined (RCC_D3CCIPR_ADCSEL)
3886 return (uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL));
3887 #else
3888 return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL));
3889 #endif /* RCC_D3CCIPR_ADCSEL */
3890 }
3891
3892 /**
3893 * @}
3894 */
3895
3896 /** @defgroup RCC_LL_EF_RTC RTC
3897 * @{
3898 */
3899
3900 /**
3901 * @brief Set RTC Clock Source
3902 * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
3903 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
3904 * set). The BDRST bit can be used to reset them.
3905 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
3906 * @param Source This parameter can be one of the following values:
3907 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
3908 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
3909 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
3910 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
3911 * @retval None
3912 */
3913 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
3914 {
3915 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
3916 }
3917
3918 /**
3919 * @brief Get RTC Clock Source
3920 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
3921 * @retval Returned value can be one of the following values:
3922 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
3923 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
3924 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
3925 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
3926 */
3927 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
3928 {
3929 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
3930 }
3931
3932 /**
3933 * @brief Enable RTC
3934 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
3935 * @retval None
3936 */
3937 __STATIC_INLINE void LL_RCC_EnableRTC(void)
3938 {
3939 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
3940 }
3941
3942 /**
3943 * @brief Disable RTC
3944 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
3945 * @retval None
3946 */
3947 __STATIC_INLINE void LL_RCC_DisableRTC(void)
3948 {
3949 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
3950 }
3951
3952 /**
3953 * @brief Check if RTC has been enabled or not
3954 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
3955 * @retval State of bit (1 or 0).
3956 */
3957 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
3958 {
3959 return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN))?1UL:0UL);
3960 }
3961
3962 /**
3963 * @brief Force the Backup domain reset
3964 * @rmtoll BDCR BDRST / VSWRST LL_RCC_ForceBackupDomainReset
3965 * @retval None
3966 */
3967 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
3968 {
3969 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
3970 }
3971
3972 /**
3973 * @brief Release the Backup domain reset
3974 * @rmtoll BDCR BDRST / VSWRST LL_RCC_ReleaseBackupDomainReset
3975 * @retval None
3976 */
3977 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
3978 {
3979 #if defined(RCC_BDCR_BDRST)
3980 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
3981 #else
3982 CLEAR_BIT(RCC->BDCR, RCC_BDCR_VSWRST);
3983 #endif /* RCC_BDCR_BDRST */
3984 }
3985
3986 /**
3987 * @brief Set HSE Prescalers for RTC Clock
3988 * @rmtoll CFGR RTCPRE LL_RCC_SetRTC_HSEPrescaler
3989 * @param Prescaler This parameter can be one of the following values:
3990 * @arg @ref LL_RCC_RTC_NOCLOCK
3991 * @arg @ref LL_RCC_RTC_HSE_DIV_2
3992 * @arg @ref LL_RCC_RTC_HSE_DIV_3
3993 * @arg @ref LL_RCC_RTC_HSE_DIV_4
3994 * @arg @ref LL_RCC_RTC_HSE_DIV_5
3995 * @arg @ref LL_RCC_RTC_HSE_DIV_6
3996 * @arg @ref LL_RCC_RTC_HSE_DIV_7
3997 * @arg @ref LL_RCC_RTC_HSE_DIV_8
3998 * @arg @ref LL_RCC_RTC_HSE_DIV_9
3999 * @arg @ref LL_RCC_RTC_HSE_DIV_10
4000 * @arg @ref LL_RCC_RTC_HSE_DIV_11
4001 * @arg @ref LL_RCC_RTC_HSE_DIV_12
4002 * @arg @ref LL_RCC_RTC_HSE_DIV_13
4003 * @arg @ref LL_RCC_RTC_HSE_DIV_14
4004 * @arg @ref LL_RCC_RTC_HSE_DIV_15
4005 * @arg @ref LL_RCC_RTC_HSE_DIV_16
4006 * @arg @ref LL_RCC_RTC_HSE_DIV_17
4007 * @arg @ref LL_RCC_RTC_HSE_DIV_18
4008 * @arg @ref LL_RCC_RTC_HSE_DIV_19
4009 * @arg @ref LL_RCC_RTC_HSE_DIV_20
4010 * @arg @ref LL_RCC_RTC_HSE_DIV_21
4011 * @arg @ref LL_RCC_RTC_HSE_DIV_22
4012 * @arg @ref LL_RCC_RTC_HSE_DIV_23
4013 * @arg @ref LL_RCC_RTC_HSE_DIV_24
4014 * @arg @ref LL_RCC_RTC_HSE_DIV_25
4015 * @arg @ref LL_RCC_RTC_HSE_DIV_26
4016 * @arg @ref LL_RCC_RTC_HSE_DIV_27
4017 * @arg @ref LL_RCC_RTC_HSE_DIV_28
4018 * @arg @ref LL_RCC_RTC_HSE_DIV_29
4019 * @arg @ref LL_RCC_RTC_HSE_DIV_30
4020 * @arg @ref LL_RCC_RTC_HSE_DIV_31
4021 * @arg @ref LL_RCC_RTC_HSE_DIV_32
4022 * @arg @ref LL_RCC_RTC_HSE_DIV_33
4023 * @arg @ref LL_RCC_RTC_HSE_DIV_34
4024 * @arg @ref LL_RCC_RTC_HSE_DIV_35
4025 * @arg @ref LL_RCC_RTC_HSE_DIV_36
4026 * @arg @ref LL_RCC_RTC_HSE_DIV_37
4027 * @arg @ref LL_RCC_RTC_HSE_DIV_38
4028 * @arg @ref LL_RCC_RTC_HSE_DIV_39
4029 * @arg @ref LL_RCC_RTC_HSE_DIV_40
4030 * @arg @ref LL_RCC_RTC_HSE_DIV_41
4031 * @arg @ref LL_RCC_RTC_HSE_DIV_42
4032 * @arg @ref LL_RCC_RTC_HSE_DIV_43
4033 * @arg @ref LL_RCC_RTC_HSE_DIV_44
4034 * @arg @ref LL_RCC_RTC_HSE_DIV_45
4035 * @arg @ref LL_RCC_RTC_HSE_DIV_46
4036 * @arg @ref LL_RCC_RTC_HSE_DIV_47
4037 * @arg @ref LL_RCC_RTC_HSE_DIV_48
4038 * @arg @ref LL_RCC_RTC_HSE_DIV_49
4039 * @arg @ref LL_RCC_RTC_HSE_DIV_50
4040 * @arg @ref LL_RCC_RTC_HSE_DIV_51
4041 * @arg @ref LL_RCC_RTC_HSE_DIV_52
4042 * @arg @ref LL_RCC_RTC_HSE_DIV_53
4043 * @arg @ref LL_RCC_RTC_HSE_DIV_54
4044 * @arg @ref LL_RCC_RTC_HSE_DIV_55
4045 * @arg @ref LL_RCC_RTC_HSE_DIV_56
4046 * @arg @ref LL_RCC_RTC_HSE_DIV_57
4047 * @arg @ref LL_RCC_RTC_HSE_DIV_58
4048 * @arg @ref LL_RCC_RTC_HSE_DIV_59
4049 * @arg @ref LL_RCC_RTC_HSE_DIV_60
4050 * @arg @ref LL_RCC_RTC_HSE_DIV_61
4051 * @arg @ref LL_RCC_RTC_HSE_DIV_62
4052 * @arg @ref LL_RCC_RTC_HSE_DIV_63
4053 * @retval None
4054 */
4055 __STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)
4056 {
4057 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler);
4058 }
4059
4060 /**
4061 * @brief Get HSE Prescalers for RTC Clock
4062 * @rmtoll CFGR RTCPRE LL_RCC_GetRTC_HSEPrescaler
4063 * @retval Returned value can be one of the following values:
4064 * @arg @ref LL_RCC_RTC_NOCLOCK
4065 * @arg @ref LL_RCC_RTC_HSE_DIV_2
4066 * @arg @ref LL_RCC_RTC_HSE_DIV_3
4067 * @arg @ref LL_RCC_RTC_HSE_DIV_4
4068 * @arg @ref LL_RCC_RTC_HSE_DIV_5
4069 * @arg @ref LL_RCC_RTC_HSE_DIV_6
4070 * @arg @ref LL_RCC_RTC_HSE_DIV_7
4071 * @arg @ref LL_RCC_RTC_HSE_DIV_8
4072 * @arg @ref LL_RCC_RTC_HSE_DIV_9
4073 * @arg @ref LL_RCC_RTC_HSE_DIV_10
4074 * @arg @ref LL_RCC_RTC_HSE_DIV_11
4075 * @arg @ref LL_RCC_RTC_HSE_DIV_12
4076 * @arg @ref LL_RCC_RTC_HSE_DIV_13
4077 * @arg @ref LL_RCC_RTC_HSE_DIV_14
4078 * @arg @ref LL_RCC_RTC_HSE_DIV_15
4079 * @arg @ref LL_RCC_RTC_HSE_DIV_16
4080 * @arg @ref LL_RCC_RTC_HSE_DIV_17
4081 * @arg @ref LL_RCC_RTC_HSE_DIV_18
4082 * @arg @ref LL_RCC_RTC_HSE_DIV_19
4083 * @arg @ref LL_RCC_RTC_HSE_DIV_20
4084 * @arg @ref LL_RCC_RTC_HSE_DIV_21
4085 * @arg @ref LL_RCC_RTC_HSE_DIV_22
4086 * @arg @ref LL_RCC_RTC_HSE_DIV_23
4087 * @arg @ref LL_RCC_RTC_HSE_DIV_24
4088 * @arg @ref LL_RCC_RTC_HSE_DIV_25
4089 * @arg @ref LL_RCC_RTC_HSE_DIV_26
4090 * @arg @ref LL_RCC_RTC_HSE_DIV_27
4091 * @arg @ref LL_RCC_RTC_HSE_DIV_28
4092 * @arg @ref LL_RCC_RTC_HSE_DIV_29
4093 * @arg @ref LL_RCC_RTC_HSE_DIV_30
4094 * @arg @ref LL_RCC_RTC_HSE_DIV_31
4095 * @arg @ref LL_RCC_RTC_HSE_DIV_32
4096 * @arg @ref LL_RCC_RTC_HSE_DIV_33
4097 * @arg @ref LL_RCC_RTC_HSE_DIV_34
4098 * @arg @ref LL_RCC_RTC_HSE_DIV_35
4099 * @arg @ref LL_RCC_RTC_HSE_DIV_36
4100 * @arg @ref LL_RCC_RTC_HSE_DIV_37
4101 * @arg @ref LL_RCC_RTC_HSE_DIV_38
4102 * @arg @ref LL_RCC_RTC_HSE_DIV_39
4103 * @arg @ref LL_RCC_RTC_HSE_DIV_40
4104 * @arg @ref LL_RCC_RTC_HSE_DIV_41
4105 * @arg @ref LL_RCC_RTC_HSE_DIV_42
4106 * @arg @ref LL_RCC_RTC_HSE_DIV_43
4107 * @arg @ref LL_RCC_RTC_HSE_DIV_44
4108 * @arg @ref LL_RCC_RTC_HSE_DIV_45
4109 * @arg @ref LL_RCC_RTC_HSE_DIV_46
4110 * @arg @ref LL_RCC_RTC_HSE_DIV_47
4111 * @arg @ref LL_RCC_RTC_HSE_DIV_48
4112 * @arg @ref LL_RCC_RTC_HSE_DIV_49
4113 * @arg @ref LL_RCC_RTC_HSE_DIV_50
4114 * @arg @ref LL_RCC_RTC_HSE_DIV_51
4115 * @arg @ref LL_RCC_RTC_HSE_DIV_52
4116 * @arg @ref LL_RCC_RTC_HSE_DIV_53
4117 * @arg @ref LL_RCC_RTC_HSE_DIV_54
4118 * @arg @ref LL_RCC_RTC_HSE_DIV_55
4119 * @arg @ref LL_RCC_RTC_HSE_DIV_56
4120 * @arg @ref LL_RCC_RTC_HSE_DIV_57
4121 * @arg @ref LL_RCC_RTC_HSE_DIV_58
4122 * @arg @ref LL_RCC_RTC_HSE_DIV_59
4123 * @arg @ref LL_RCC_RTC_HSE_DIV_60
4124 * @arg @ref LL_RCC_RTC_HSE_DIV_61
4125 * @arg @ref LL_RCC_RTC_HSE_DIV_62
4126 * @arg @ref LL_RCC_RTC_HSE_DIV_63
4127 */
4128 __STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
4129 {
4130 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE));
4131 }
4132
4133 /**
4134 * @}
4135 */
4136
4137 /** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM
4138 * @{
4139 */
4140
4141 /**
4142 * @brief Set Timers Clock Prescalers
4143 * @rmtoll CFGR TIMPRE LL_RCC_SetTIMPrescaler
4144 * @param Prescaler This parameter can be one of the following values:
4145 * @arg @ref LL_RCC_TIM_PRESCALER_TWICE
4146 * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
4147 * @retval None
4148 */
4149 __STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler)
4150 {
4151 MODIFY_REG(RCC->CFGR, RCC_CFGR_TIMPRE, Prescaler);
4152 }
4153
4154 /**
4155 * @brief Get Timers Clock Prescalers
4156 * @rmtoll CFGR TIMPRE LL_RCC_GetTIMPrescaler
4157 * @retval Returned value can be one of the following values:
4158 * @arg @ref LL_RCC_TIM_PRESCALER_TWICE
4159 * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
4160 */
4161 __STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void)
4162 {
4163 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_TIMPRE));
4164 }
4165
4166 /**
4167 * @}
4168 */
4169
4170 #if defined(HRTIM1)
4171 /** @defgroup RCC_LL_EF_HRTIM_SET_CLOCK_SOURCE HRTIM
4172 * @{
4173 */
4174
4175 /**
4176 * @brief Set High Resolution Timers Clock Source
4177 * @rmtoll CFGR HRTIMSEL LL_RCC_SetHRTIMClockSource
4178 * @param Prescaler This parameter can be one of the following values:
4179 * @arg @ref LL_RCC_HRTIM_CLKSOURCE_TIM
4180 * @arg @ref LL_RCC_HRTIM_CLKSOURCE_CPU
4181 * @retval None
4182 */
4183 __STATIC_INLINE void LL_RCC_SetHRTIMClockSource(uint32_t Prescaler)
4184 {
4185 MODIFY_REG(RCC->CFGR, RCC_CFGR_HRTIMSEL, Prescaler);
4186 }
4187 #endif /* HRTIM1 */
4188
4189 #if defined(HRTIM1)
4190 /**
4191 * @brief Get High Resolution Timers Clock Source
4192 * @rmtoll CFGR HRTIMSEL LL_RCC_GetHRTIMClockSource
4193 * @retval Returned value can be one of the following values:
4194 * @arg @ref LL_RCC_HRTIM_CLKSOURCE_TIM
4195 * @arg @ref LL_RCC_HRTIM_CLKSOURCE_CPU
4196 */
4197 __STATIC_INLINE uint32_t LL_RCC_GetHRTIMClockSource(void)
4198 {
4199 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL));
4200 }
4201 /**
4202 * @}
4203 */
4204 #endif /* HRTIM1 */
4205
4206 /** @defgroup RCC_LL_EF_PLL PLL
4207 * @{
4208 */
4209
4210 /**
4211 * @brief Set the oscillator used as PLL clock source.
4212 * @note PLLSRC can be written only when All PLLs are disabled.
4213 * @rmtoll PLLCKSELR PLLSRC LL_RCC_PLL_SetSource
4214 * @param PLLSource parameter can be one of the following values:
4215 * @arg @ref LL_RCC_PLLSOURCE_HSI
4216 * @arg @ref LL_RCC_PLLSOURCE_CSI
4217 * @arg @ref LL_RCC_PLLSOURCE_HSE
4218 * @arg @ref LL_RCC_PLLSOURCE_NONE
4219 * @retval None
4220 */
4221 __STATIC_INLINE void LL_RCC_PLL_SetSource(uint32_t PLLSource)
4222 {
4223 MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, PLLSource);
4224 }
4225
4226 /**
4227 * @brief Get the oscillator used as PLL clock source.
4228 * @rmtoll PLLCKSELR PLLSRC LL_RCC_PLL_GetSource
4229 * @retval Returned value can be one of the following values:
4230 * @arg @ref LL_RCC_PLLSOURCE_HSI
4231 * @arg @ref LL_RCC_PLLSOURCE_CSI
4232 * @arg @ref LL_RCC_PLLSOURCE_HSE
4233 * @arg @ref LL_RCC_PLLSOURCE_NONE
4234 */
4235 __STATIC_INLINE uint32_t LL_RCC_PLL_GetSource(void)
4236 {
4237 return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC));
4238 }
4239
4240 /**
4241 * @brief Enable PLL1
4242 * @rmtoll CR PLL1ON LL_RCC_PLL1_Enable
4243 * @retval None
4244 */
4245 __STATIC_INLINE void LL_RCC_PLL1_Enable(void)
4246 {
4247 SET_BIT(RCC->CR, RCC_CR_PLL1ON);
4248 }
4249
4250 /**
4251 * @brief Disable PLL1
4252 * @note Cannot be disabled if the PLL1 clock is used as the system clock
4253 * @rmtoll CR PLL1ON LL_RCC_PLL1_Disable
4254 * @retval None
4255 */
4256 __STATIC_INLINE void LL_RCC_PLL1_Disable(void)
4257 {
4258 CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON);
4259 }
4260
4261 /**
4262 * @brief Check if PLL1 Ready
4263 * @rmtoll CR PLL1RDY LL_RCC_PLL1_IsReady
4264 * @retval State of bit (1 or 0).
4265 */
4266 __STATIC_INLINE uint32_t LL_RCC_PLL1_IsReady(void)
4267 {
4268 return ((READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == (RCC_CR_PLL1RDY))?1UL:0UL);
4269 }
4270
4271 /**
4272 * @brief Enable PLL1P
4273 * @note This API shall be called only when PLL1 is disabled.
4274 * @rmtoll PLLCFGR DIVP1EN LL_RCC_PLL1P_Enable
4275 * @retval None
4276 */
4277 __STATIC_INLINE void LL_RCC_PLL1P_Enable(void)
4278 {
4279 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN);
4280 }
4281
4282 /**
4283 * @brief Enable PLL1Q
4284 * @note This API shall be called only when PLL1 is disabled.
4285 * @rmtoll PLLCFGR DIVQ1EN LL_RCC_PLL1Q_Enable
4286 * @retval None
4287 */
4288 __STATIC_INLINE void LL_RCC_PLL1Q_Enable(void)
4289 {
4290 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN);
4291 }
4292
4293 /**
4294 * @brief Enable PLL1R
4295 * @note This API shall be called only when PLL1 is disabled.
4296 * @rmtoll PLLCFGR DIVR1EN LL_RCC_PLL1R_Enable
4297 * @retval None
4298 */
4299 __STATIC_INLINE void LL_RCC_PLL1R_Enable(void)
4300 {
4301 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN);
4302 }
4303
4304 /**
4305 * @brief Enable PLL1 FRACN
4306 * @rmtoll PLLCFGR PLL1FRACEN LL_RCC_PLL1FRACN_Enable
4307 * @retval None
4308 */
4309 __STATIC_INLINE void LL_RCC_PLL1FRACN_Enable(void)
4310 {
4311 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN);
4312 }
4313
4314 /**
4315 * @brief Check if PLL1 P is enabled
4316 * @rmtoll PLLCFGR DIVP1EN LL_RCC_PLL1P_IsEnabled
4317 * @retval State of bit (1 or 0).
4318 */
4319 __STATIC_INLINE uint32_t LL_RCC_PLL1P_IsEnabled(void)
4320 {
4321 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN) == RCC_PLLCFGR_DIVP1EN)?1UL:0UL);
4322 }
4323
4324 /**
4325 * @brief Check if PLL1 Q is enabled
4326 * @rmtoll PLLCFGR DIVQ1EN LL_RCC_PLL1Q_IsEnabled
4327 * @retval State of bit (1 or 0).
4328 */
4329 __STATIC_INLINE uint32_t LL_RCC_PLL1Q_IsEnabled(void)
4330 {
4331 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN) == RCC_PLLCFGR_DIVQ1EN)?1UL:0UL);
4332 }
4333
4334 /**
4335 * @brief Check if PLL1 R is enabled
4336 * @rmtoll PLLCFGR DIVR1EN LL_RCC_PLL1R_IsEnabled
4337 * @retval State of bit (1 or 0).
4338 */
4339 __STATIC_INLINE uint32_t LL_RCC_PLL1R_IsEnabled(void)
4340 {
4341 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN) == RCC_PLLCFGR_DIVR1EN)?1UL:0UL);
4342 }
4343
4344 /**
4345 * @brief Check if PLL1 FRACN is enabled
4346 * @rmtoll PLLCFGR PLL1FRACEN LL_RCC_PLL1FRACN_IsEnabled
4347 * @retval State of bit (1 or 0).
4348 */
4349 __STATIC_INLINE uint32_t LL_RCC_PLL1FRACN_IsEnabled(void)
4350 {
4351 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN) == RCC_PLLCFGR_PLL1FRACEN)?1UL:0UL);
4352 }
4353
4354 /**
4355 * @brief Disable PLL1P
4356 * @note This API shall be called only when PLL1 is disabled.
4357 * @rmtoll PLLCFGR DIVP1EN LL_RCC_PLL1P_Disable
4358 * @retval None
4359 */
4360 __STATIC_INLINE void LL_RCC_PLL1P_Disable(void)
4361 {
4362 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN);
4363 }
4364
4365 /**
4366 * @brief Disable PLL1Q
4367 * @note This API shall be called only when PLL1 is disabled.
4368 * @rmtoll PLLCFGR DIVQ1EN LL_RCC_PLL1Q_Disable
4369 * @retval None
4370 */
4371 __STATIC_INLINE void LL_RCC_PLL1Q_Disable(void)
4372 {
4373 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN);
4374 }
4375
4376 /**
4377 * @brief Disable PLL1R
4378 * @note This API shall be called only when PLL1 is disabled.
4379 * @rmtoll PLLCFGR DIVR1EN LL_RCC_PLL1R_Disable
4380 * @retval None
4381 */
4382 __STATIC_INLINE void LL_RCC_PLL1R_Disable(void)
4383 {
4384 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN);
4385 }
4386
4387 /**
4388 * @brief Disable PLL1 FRACN
4389 * @rmtoll PLLCFGR PLL1FRACEN LL_RCC_PLL1FRACN_Enable
4390 * @retval None
4391 */
4392 __STATIC_INLINE void LL_RCC_PLL1FRACN_Disable(void)
4393 {
4394 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN);
4395 }
4396
4397 /**
4398 * @brief Set PLL1 VCO OutputRange
4399 * @note This API shall be called only when PLL1 is disabled.
4400 * @rmtoll PLLCFGR PLL1VCOSEL LL_RCC_PLL1_SetVCOOuputRange
4401 * @param VCORange This parameter can be one of the following values:
4402 * @arg @ref LL_RCC_PLLVCORANGE_WIDE
4403 * @arg @ref LL_RCC_PLLVCORANGE_MEDIUM
4404 * @retval None
4405 */
4406 __STATIC_INLINE void LL_RCC_PLL1_SetVCOOutputRange(uint32_t VCORange)
4407 {
4408 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, VCORange << RCC_PLLCFGR_PLL1VCOSEL_Pos);
4409 }
4410
4411 /**
4412 * @brief Set PLL1 VCO Input Range
4413 * @note This API shall be called only when PLL1 is disabled.
4414 * @rmtoll PLLCFGR PLL1RGE LL_RCC_PLL1_SetVCOInputRange
4415 * @param InputRange This parameter can be one of the following values:
4416 * @arg @ref LL_RCC_PLLINPUTRANGE_1_2
4417 * @arg @ref LL_RCC_PLLINPUTRANGE_2_4
4418 * @arg @ref LL_RCC_PLLINPUTRANGE_4_8
4419 * @arg @ref LL_RCC_PLLINPUTRANGE_8_16
4420 * @retval None
4421 */
4422 __STATIC_INLINE void LL_RCC_PLL1_SetVCOInputRange(uint32_t InputRange)
4423 {
4424 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, InputRange << RCC_PLLCFGR_PLL1RGE_Pos);
4425 }
4426
4427 /**
4428 * @brief Get PLL1 N Coefficient
4429 * @rmtoll PLL1DIVR N1 LL_RCC_PLL1_GetN
4430 * @retval A value between 4 and 512
4431 */
4432 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetN(void)
4433 {
4434 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_N1) >> RCC_PLL1DIVR_N1_Pos) + 1UL);
4435 }
4436
4437 /**
4438 * @brief Get PLL1 M Coefficient
4439 * @rmtoll PLLCKSELR DIVM1 LL_RCC_PLL1_GetM
4440 * @retval A value between 0 and 63
4441 */
4442 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetM(void)
4443 {
4444 return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos);
4445 }
4446
4447 /**
4448 * @brief Get PLL1 P Coefficient
4449 * @rmtoll PLL1DIVR P1 LL_RCC_PLL1_GetP
4450 * @retval A value between 2 and 128
4451 */
4452 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetP(void)
4453 {
4454 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) + 1UL);
4455 }
4456
4457 /**
4458 * @brief Get PLL1 Q Coefficient
4459 * @rmtoll PLL1DIVR Q1 LL_RCC_PLL1_GetQ
4460 * @retval A value between 1 and 128
4461 */
4462 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetQ(void)
4463 {
4464 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) + 1UL);
4465 }
4466
4467 /**
4468 * @brief Get PLL1 R Coefficient
4469 * @rmtoll PLL1DIVR R1 LL_RCC_PLL1_GetR
4470 * @retval A value between 1 and 128
4471 */
4472 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetR(void)
4473 {
4474 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) + 1UL);
4475 }
4476
4477 /**
4478 * @brief Get PLL1 FRACN Coefficient
4479 * @rmtoll PLL1FRACR FRACN1 LL_RCC_PLL1_GetFRACN
4480 * @retval A value between 0 and 8191 (0x1FFF)
4481 */
4482 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetFRACN(void)
4483 {
4484 return (uint32_t)(READ_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos);
4485 }
4486
4487 /**
4488 * @brief Set PLL1 N Coefficient
4489 * @note This API shall be called only when PLL1 is disabled.
4490 * @rmtoll PLL1DIVR N1 LL_RCC_PLL1_SetN
4491 * @param N parameter can be a value between 4 and 512
4492 */
4493 __STATIC_INLINE void LL_RCC_PLL1_SetN(uint32_t N)
4494 {
4495 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_N1, (N-1UL) << RCC_PLL1DIVR_N1_Pos);
4496 }
4497
4498 /**
4499 * @brief Set PLL1 M Coefficient
4500 * @note This API shall be called only when PLL1 is disabled.
4501 * @rmtoll PLLCKSELR DIVM1 LL_RCC_PLL1_SetM
4502 * @param M parameter can be a value between 0 and 63
4503 */
4504 __STATIC_INLINE void LL_RCC_PLL1_SetM(uint32_t M)
4505 {
4506 MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1, M << RCC_PLLCKSELR_DIVM1_Pos);
4507 }
4508
4509 /**
4510 * @brief Set PLL1 P Coefficient
4511 * @note This API shall be called only when PLL1 is disabled.
4512 * @rmtoll PLL1DIVR P1 LL_RCC_PLL1_SetP
4513 * @param P parameter can be a value between 2 and 128 (ODD division factor not supportted)
4514 */
4515 __STATIC_INLINE void LL_RCC_PLL1_SetP(uint32_t P)
4516 {
4517 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_P1, (P-1UL) << RCC_PLL1DIVR_P1_Pos);
4518 }
4519
4520 /**
4521 * @brief Set PLL1 Q Coefficient
4522 * @note This API shall be called only when PLL1 is disabled.
4523 * @rmtoll PLL1DIVR Q1 LL_RCC_PLL1_SetQ
4524 * @param Q parameter can be a value between 1 and 128
4525 */
4526 __STATIC_INLINE void LL_RCC_PLL1_SetQ(uint32_t Q)
4527 {
4528 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1, (Q-1UL) << RCC_PLL1DIVR_Q1_Pos);
4529 }
4530
4531 /**
4532 * @brief Set PLL1 R Coefficient
4533 * @note This API shall be called only when PLL1 is disabled.
4534 * @rmtoll PLL1DIVR R1 LL_RCC_PLL1_SetR
4535 * @param R parameter can be a value between 1 and 128
4536 */
4537 __STATIC_INLINE void LL_RCC_PLL1_SetR(uint32_t R)
4538 {
4539 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_R1, (R-1UL) << RCC_PLL1DIVR_R1_Pos);
4540 }
4541
4542 /**
4543 * @brief Set PLL1 FRACN Coefficient
4544 * @rmtoll PLL1FRACR FRACN1 LL_RCC_PLL1_SetFRACN
4545 * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF)
4546 */
4547 __STATIC_INLINE void LL_RCC_PLL1_SetFRACN(uint32_t FRACN)
4548 {
4549 MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, FRACN << RCC_PLL1FRACR_FRACN1_Pos);
4550 }
4551
4552 /**
4553 * @brief Enable PLL2
4554 * @rmtoll CR PLL2ON LL_RCC_PLL2_Enable
4555 * @retval None
4556 */
4557 __STATIC_INLINE void LL_RCC_PLL2_Enable(void)
4558 {
4559 SET_BIT(RCC->CR, RCC_CR_PLL2ON);
4560 }
4561
4562 /**
4563 * @brief Disable PLL2
4564 * @note Cannot be disabled if the PLL2 clock is used as the system clock
4565 * @rmtoll CR PLL2ON LL_RCC_PLL2_Disable
4566 * @retval None
4567 */
4568 __STATIC_INLINE void LL_RCC_PLL2_Disable(void)
4569 {
4570 CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
4571 }
4572
4573 /**
4574 * @brief Check if PLL2 Ready
4575 * @rmtoll CR PLL2RDY LL_RCC_PLL2_IsReady
4576 * @retval State of bit (1 or 0).
4577 */
4578 __STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void)
4579 {
4580 return ((READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == (RCC_CR_PLL2RDY))?1UL:0UL);
4581 }
4582
4583 /**
4584 * @brief Enable PLL2P
4585 * @note This API shall be called only when PLL2 is disabled.
4586 * @rmtoll PLLCFGR DIVP2EN LL_RCC_PLL2P_Enable
4587 * @retval None
4588 */
4589 __STATIC_INLINE void LL_RCC_PLL2P_Enable(void)
4590 {
4591 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN);
4592 }
4593
4594 /**
4595 * @brief Enable PLL2Q
4596 * @note This API shall be called only when PLL2 is disabled.
4597 * @rmtoll PLLCFGR DIVQ2EN LL_RCC_PLL2Q_Enable
4598 * @retval None
4599 */
4600 __STATIC_INLINE void LL_RCC_PLL2Q_Enable(void)
4601 {
4602 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN);
4603 }
4604
4605 /**
4606 * @brief Enable PLL2R
4607 * @note This API shall be called only when PLL2 is disabled.
4608 * @rmtoll PLLCFGR DIVR2EN LL_RCC_PLL2R_Enable
4609 * @retval None
4610 */
4611 __STATIC_INLINE void LL_RCC_PLL2R_Enable(void)
4612 {
4613 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN);
4614 }
4615
4616 /**
4617 * @brief Enable PLL2 FRACN
4618 * @rmtoll PLLCFGR PLL2FRACEN LL_RCC_PLL2FRACN_Enable
4619 * @retval None
4620 */
4621 __STATIC_INLINE void LL_RCC_PLL2FRACN_Enable(void)
4622 {
4623 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN);
4624 }
4625
4626 /**
4627 * @brief Check if PLL2 P is enabled
4628 * @rmtoll PLLCFGR DIVP2EN LL_RCC_PLL2P_IsEnabled
4629 * @retval State of bit (1 or 0).
4630 */
4631 __STATIC_INLINE uint32_t LL_RCC_PLL2P_IsEnabled(void)
4632 {
4633 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN) == RCC_PLLCFGR_DIVP2EN)?1UL:0UL);
4634 }
4635
4636 /**
4637 * @brief Check if PLL2 Q is enabled
4638 * @rmtoll PLLCFGR DIVQ2EN LL_RCC_PLL2Q_IsEnabled
4639 * @retval State of bit (1 or 0).
4640 */
4641 __STATIC_INLINE uint32_t LL_RCC_PLL2Q_IsEnabled(void)
4642 {
4643 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN) == RCC_PLLCFGR_DIVQ2EN)?1UL:0UL);
4644 }
4645
4646 /**
4647 * @brief Check if PLL2 R is enabled
4648 * @rmtoll PLLCFGR DIVR2EN LL_RCC_PLL2R_IsEnabled
4649 * @retval State of bit (1 or 0).
4650 */
4651 __STATIC_INLINE uint32_t LL_RCC_PLL2R_IsEnabled(void)
4652 {
4653 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN) == RCC_PLLCFGR_DIVR2EN)?1UL:0UL);
4654 }
4655
4656 /**
4657 * @brief Check if PLL2 FRACN is enabled
4658 * @rmtoll PLLCFGR PLL2FRACEN LL_RCC_PLL2FRACN_IsEnabled
4659 * @retval State of bit (1 or 0).
4660 */
4661 __STATIC_INLINE uint32_t LL_RCC_PLL2FRACN_IsEnabled(void)
4662 {
4663 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) == RCC_PLLCFGR_PLL2FRACEN)?1UL:0UL);
4664 }
4665
4666 /**
4667 * @brief Disable PLL2P
4668 * @note This API shall be called only when PLL2 is disabled.
4669 * @rmtoll PLLCFGR DIVP2EN LL_RCC_PLL2P_Disable
4670 * @retval None
4671 */
4672 __STATIC_INLINE void LL_RCC_PLL2P_Disable(void)
4673 {
4674 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN);
4675 }
4676
4677 /**
4678 * @brief Disable PLL2Q
4679 * @note This API shall be called only when PLL2 is disabled.
4680 * @rmtoll PLLCFGR DIVQ2EN LL_RCC_PLL2Q_Disable
4681 * @retval None
4682 */
4683 __STATIC_INLINE void LL_RCC_PLL2Q_Disable(void)
4684 {
4685 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN);
4686 }
4687
4688 /**
4689 * @brief Disable PLL2R
4690 * @note This API shall be called only when PLL2 is disabled.
4691 * @rmtoll PLLCFGR DIVR2EN LL_RCC_PLL2R_Disable
4692 * @retval None
4693 */
4694 __STATIC_INLINE void LL_RCC_PLL2R_Disable(void)
4695 {
4696 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN);
4697 }
4698
4699 /**
4700 * @brief Disable PLL2 FRACN
4701 * @rmtoll PLLCFGR PLL2FRACEN LL_RCC_PLL2FRACN_Enable
4702 * @retval None
4703 */
4704 __STATIC_INLINE void LL_RCC_PLL2FRACN_Disable(void)
4705 {
4706 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN);
4707 }
4708
4709 /**
4710 * @brief Set PLL2 VCO OutputRange
4711 * @note This API shall be called only when PLL2 is disabled.
4712 * @rmtoll PLLCFGR PLL2VCOSEL LL_RCC_PLL2_SetVCOOuputRange
4713 * @param VCORange This parameter can be one of the following values:
4714 * @arg @ref LL_RCC_PLLVCORANGE_WIDE
4715 * @arg @ref LL_RCC_PLLVCORANGE_MEDIUM
4716 * @retval None
4717 */
4718 __STATIC_INLINE void LL_RCC_PLL2_SetVCOOutputRange(uint32_t VCORange)
4719 {
4720 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, VCORange << RCC_PLLCFGR_PLL2VCOSEL_Pos);
4721 }
4722
4723 /**
4724 * @brief Set PLL2 VCO Input Range
4725 * @note This API shall be called only when PLL2 is disabled.
4726 * @rmtoll PLLCFGR PLL2RGE LL_RCC_PLL2_SetVCOInputRange
4727 * @param InputRange This parameter can be one of the following values:
4728 * @arg @ref LL_RCC_PLLINPUTRANGE_1_2
4729 * @arg @ref LL_RCC_PLLINPUTRANGE_2_4
4730 * @arg @ref LL_RCC_PLLINPUTRANGE_4_8
4731 * @arg @ref LL_RCC_PLLINPUTRANGE_8_16
4732 * @retval None
4733 */
4734 __STATIC_INLINE void LL_RCC_PLL2_SetVCOInputRange(uint32_t InputRange)
4735 {
4736 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, InputRange << RCC_PLLCFGR_PLL2RGE_Pos);
4737 }
4738
4739 /**
4740 * @brief Get PLL2 N Coefficient
4741 * @rmtoll PLL2DIVR N2 LL_RCC_PLL2_GetN
4742 * @retval A value between 4 and 512
4743 */
4744 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetN(void)
4745 {
4746 return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_N2) >> RCC_PLL2DIVR_N2_Pos) + 1UL);
4747 }
4748
4749 /**
4750 * @brief Get PLL2 M Coefficient
4751 * @rmtoll PLLCKSELR DIVM2 LL_RCC_PLL2_GetM
4752 * @retval A value between 0 and 63
4753 */
4754 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetM(void)
4755 {
4756 return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM2) >> RCC_PLLCKSELR_DIVM2_Pos);
4757 }
4758
4759 /**
4760 * @brief Get PLL2 P Coefficient
4761 * @rmtoll PLL2DIVR P2 LL_RCC_PLL2_GetP
4762 * @retval A value between 1 and 128
4763 */
4764 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetP(void)
4765 {
4766 return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_P2) >> RCC_PLL2DIVR_P2_Pos) + 1UL);
4767 }
4768
4769 /**
4770 * @brief Get PLL2 Q Coefficient
4771 * @rmtoll PLL2DIVR Q2 LL_RCC_PLL2_GetQ
4772 * @retval A value between 1 and 128
4773 */
4774 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetQ(void)
4775 {
4776 return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_Q2) >> RCC_PLL2DIVR_Q2_Pos) + 1UL);
4777 }
4778
4779 /**
4780 * @brief Get PLL2 R Coefficient
4781 * @rmtoll PLL2DIVR R2 LL_RCC_PLL2_GetR
4782 * @retval A value between 1 and 128
4783 */
4784 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetR(void)
4785 {
4786 return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_R2) >> RCC_PLL2DIVR_R2_Pos) + 1UL);
4787 }
4788
4789 /**
4790 * @brief Get PLL2 FRACN Coefficient
4791 * @rmtoll PLL2FRACR FRACN2 LL_RCC_PLL2_GetFRACN
4792 * @retval A value between 0 and 8191 (0x1FFF)
4793 */
4794 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetFRACN(void)
4795 {
4796 return (uint32_t)(READ_BIT(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2) >> RCC_PLL2FRACR_FRACN2_Pos);
4797 }
4798
4799 /**
4800 * @brief Set PLL2 N Coefficient
4801 * @note This API shall be called only when PLL2 is disabled.
4802 * @rmtoll PLL2DIVR N2 LL_RCC_PLL2_SetN
4803 * @param N parameter can be a value between 4 and 512
4804 */
4805 __STATIC_INLINE void LL_RCC_PLL2_SetN(uint32_t N)
4806 {
4807 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_N2, (N-1UL) << RCC_PLL2DIVR_N2_Pos);
4808 }
4809
4810 /**
4811 * @brief Set PLL2 M Coefficient
4812 * @note This API shall be called only when PLL2 is disabled.
4813 * @rmtoll PLLCKSELR DIVM2 LL_RCC_PLL2_SetM
4814 * @param M parameter can be a value between 0 and 63
4815 */
4816 __STATIC_INLINE void LL_RCC_PLL2_SetM(uint32_t M)
4817 {
4818 MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM2, M << RCC_PLLCKSELR_DIVM2_Pos);
4819 }
4820
4821 /**
4822 * @brief Set PLL2 P Coefficient
4823 * @note This API shall be called only when PLL2 is disabled.
4824 * @rmtoll PLL2DIVR P2 LL_RCC_PLL2_SetP
4825 * @param P parameter can be a value between 1 and 128
4826 */
4827 __STATIC_INLINE void LL_RCC_PLL2_SetP(uint32_t P)
4828 {
4829 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_P2, (P-1UL) << RCC_PLL2DIVR_P2_Pos);
4830 }
4831
4832 /**
4833 * @brief Set PLL2 Q Coefficient
4834 * @note This API shall be called only when PLL2 is disabled.
4835 * @rmtoll PLL2DIVR Q2 LL_RCC_PLL2_SetQ
4836 * @param Q parameter can be a value between 1 and 128
4837 */
4838 __STATIC_INLINE void LL_RCC_PLL2_SetQ(uint32_t Q)
4839 {
4840 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_Q2, (Q-1UL) << RCC_PLL2DIVR_Q2_Pos);
4841 }
4842
4843 /**
4844 * @brief Set PLL2 R Coefficient
4845 * @note This API shall be called only when PLL2 is disabled.
4846 * @rmtoll PLL2DIVR R2 LL_RCC_PLL2_SetR
4847 * @param R parameter can be a value between 1 and 128
4848 */
4849 __STATIC_INLINE void LL_RCC_PLL2_SetR(uint32_t R)
4850 {
4851 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_R2, (R-1UL) << RCC_PLL2DIVR_R2_Pos);
4852 }
4853
4854 /**
4855 * @brief Set PLL2 FRACN Coefficient
4856 * @rmtoll PLL2FRACR FRACN2 LL_RCC_PLL2_SetFRACN
4857 * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF)
4858 */
4859 __STATIC_INLINE void LL_RCC_PLL2_SetFRACN(uint32_t FRACN)
4860 {
4861 MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2, FRACN << RCC_PLL2FRACR_FRACN2_Pos);
4862 }
4863
4864 /**
4865 * @brief Enable PLL3
4866 * @rmtoll CR PLL3ON LL_RCC_PLL3_Enable
4867 * @retval None
4868 */
4869 __STATIC_INLINE void LL_RCC_PLL3_Enable(void)
4870 {
4871 SET_BIT(RCC->CR, RCC_CR_PLL3ON);
4872 }
4873
4874 /**
4875 * @brief Disable PLL3
4876 * @note Cannot be disabled if the PLL3 clock is used as the system clock
4877 * @rmtoll CR PLL3ON LL_RCC_PLL3_Disable
4878 * @retval None
4879 */
4880 __STATIC_INLINE void LL_RCC_PLL3_Disable(void)
4881 {
4882 CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
4883 }
4884
4885 /**
4886 * @brief Check if PLL3 Ready
4887 * @rmtoll CR PLL3RDY LL_RCC_PLL3_IsReady
4888 * @retval State of bit (1 or 0).
4889 */
4890 __STATIC_INLINE uint32_t LL_RCC_PLL3_IsReady(void)
4891 {
4892 return ((READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == (RCC_CR_PLL3RDY))?1UL:0UL);
4893 }
4894
4895 /**
4896 * @brief Enable PLL3P
4897 * @note This API shall be called only when PLL3 is disabled.
4898 * @rmtoll PLLCFGR DIVP3EN LL_RCC_PLL3P_Enable
4899 * @retval None
4900 */
4901 __STATIC_INLINE void LL_RCC_PLL3P_Enable(void)
4902 {
4903 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN);
4904 }
4905
4906 /**
4907 * @brief Enable PLL3Q
4908 * @note This API shall be called only when PLL3 is disabled.
4909 * @rmtoll PLLCFGR DIVQ3EN LL_RCC_PLL3Q_Enable
4910 * @retval None
4911 */
4912 __STATIC_INLINE void LL_RCC_PLL3Q_Enable(void)
4913 {
4914 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN);
4915 }
4916
4917 /**
4918 * @brief Enable PLL3R
4919 * @note This API shall be called only when PLL3 is disabled.
4920 * @rmtoll PLLCFGR DIVR3EN LL_RCC_PLL3R_Enable
4921 * @retval None
4922 */
4923 __STATIC_INLINE void LL_RCC_PLL3R_Enable(void)
4924 {
4925 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN);
4926 }
4927
4928 /**
4929 * @brief Enable PLL3 FRACN
4930 * @rmtoll PLLCFGR PLL3FRACEN LL_RCC_PLL3FRACN_Enable
4931 * @retval None
4932 */
4933 __STATIC_INLINE void LL_RCC_PLL3FRACN_Enable(void)
4934 {
4935 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN);
4936 }
4937
4938 /**
4939 * @brief Check if PLL3 P is enabled
4940 * @rmtoll PLLCFGR DIVP3EN LL_RCC_PLL3P_IsEnabled
4941 * @retval State of bit (1 or 0).
4942 */
4943 __STATIC_INLINE uint32_t LL_RCC_PLL3P_IsEnabled(void)
4944 {
4945 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN) == RCC_PLLCFGR_DIVP3EN)?1UL:0UL);
4946 }
4947
4948 /**
4949 * @brief Check if PLL3 Q is enabled
4950 * @rmtoll PLLCFGR DIVQ3EN LL_RCC_PLL3Q_IsEnabled
4951 * @retval State of bit (1 or 0).
4952 */
4953 __STATIC_INLINE uint32_t LL_RCC_PLL3Q_IsEnabled(void)
4954 {
4955 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN) == RCC_PLLCFGR_DIVQ3EN)?1UL:0UL);
4956 }
4957
4958 /**
4959 * @brief Check if PLL3 R is enabled
4960 * @rmtoll PLLCFGR DIVR3EN LL_RCC_PLL3R_IsEnabled
4961 * @retval State of bit (1 or 0).
4962 */
4963 __STATIC_INLINE uint32_t LL_RCC_PLL3R_IsEnabled(void)
4964 {
4965 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN) == RCC_PLLCFGR_DIVR3EN)?1UL:0UL);
4966 }
4967
4968 /**
4969 * @brief Check if PLL3 FRACN is enabled
4970 * @rmtoll PLLCFGR PLL3FRACEN LL_RCC_PLL3FRACN_IsEnabled
4971 * @retval State of bit (1 or 0).
4972 */
4973 __STATIC_INLINE uint32_t LL_RCC_PLL3FRACN_IsEnabled(void)
4974 {
4975 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) == RCC_PLLCFGR_PLL3FRACEN)?1UL:0UL);
4976 }
4977
4978 /**
4979 * @brief Disable PLL3P
4980 * @note This API shall be called only when PLL3 is disabled.
4981 * @rmtoll PLLCFGR DIVP2EN LL_RCC_PLL3P_Disable
4982 * @retval None
4983 */
4984 __STATIC_INLINE void LL_RCC_PLL3P_Disable(void)
4985 {
4986 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN);
4987 }
4988
4989 /**
4990 * @brief Disable PLL3Q
4991 * @note This API shall be called only when PLL3 is disabled.
4992 * @rmtoll PLLCFGR DIVQ3EN LL_RCC_PLL3Q_Disable
4993 * @retval None
4994 */
4995 __STATIC_INLINE void LL_RCC_PLL3Q_Disable(void)
4996 {
4997 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN);
4998 }
4999
5000 /**
5001 * @brief Disable PLL3R
5002 * @note This API shall be called only when PLL3 is disabled.
5003 * @rmtoll PLLCFGR DIVR3EN LL_RCC_PLL3R_Disable
5004 * @retval None
5005 */
5006 __STATIC_INLINE void LL_RCC_PLL3R_Disable(void)
5007 {
5008 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN);
5009 }
5010
5011 /**
5012 * @brief Disable PLL3 FRACN
5013 * @rmtoll PLLCFGR PLL3FRACEN LL_RCC_PLL3FRACN_Enable
5014 * @retval None
5015 */
5016 __STATIC_INLINE void LL_RCC_PLL3FRACN_Disable(void)
5017 {
5018 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN);
5019 }
5020
5021 /**
5022 * @brief Set PLL3 VCO OutputRange
5023 * @note This API shall be called only when PLL3 is disabled.
5024 * @rmtoll PLLCFGR PLL3VCOSEL LL_RCC_PLL3_SetVCOOuputRange
5025 * @param VCORange This parameter can be one of the following values:
5026 * @arg @ref LL_RCC_PLLVCORANGE_WIDE
5027 * @arg @ref LL_RCC_PLLVCORANGE_MEDIUM
5028 * @retval None
5029 */
5030 __STATIC_INLINE void LL_RCC_PLL3_SetVCOOutputRange(uint32_t VCORange)
5031 {
5032 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, VCORange << RCC_PLLCFGR_PLL3VCOSEL_Pos);
5033 }
5034
5035 /**
5036 * @brief Set PLL3 VCO Input Range
5037 * @note This API shall be called only when PLL3 is disabled.
5038 * @rmtoll PLLCFGR PLL3RGE LL_RCC_PLL3_SetVCOInputRange
5039 * @param InputRange This parameter can be one of the following values:
5040 * @arg @ref LL_RCC_PLLINPUTRANGE_1_2
5041 * @arg @ref LL_RCC_PLLINPUTRANGE_2_4
5042 * @arg @ref LL_RCC_PLLINPUTRANGE_4_8
5043 * @arg @ref LL_RCC_PLLINPUTRANGE_8_16
5044 * @retval None
5045 */
5046 __STATIC_INLINE void LL_RCC_PLL3_SetVCOInputRange(uint32_t InputRange)
5047 {
5048 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, InputRange << RCC_PLLCFGR_PLL3RGE_Pos);
5049 }
5050
5051 /**
5052 * @brief Get PLL3 N Coefficient
5053 * @rmtoll PLL3DIVR N3 LL_RCC_PLL3_GetN
5054 * @retval A value between 4 and 512
5055 */
5056 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetN(void)
5057 {
5058 return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_N3) >> RCC_PLL3DIVR_N3_Pos) + 1UL);
5059 }
5060
5061 /**
5062 * @brief Get PLL3 M Coefficient
5063 * @rmtoll PLLCKSELR DIVM3 LL_RCC_PLL3_GetM
5064 * @retval A value between 0 and 63
5065 */
5066 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetM(void)
5067 {
5068 return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM3) >> RCC_PLLCKSELR_DIVM3_Pos);
5069 }
5070
5071 /**
5072 * @brief Get PLL3 P Coefficient
5073 * @rmtoll PLL3DIVR P3 LL_RCC_PLL3_GetP
5074 * @retval A value between 1 and 128
5075 */
5076 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetP(void)
5077 {
5078 return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_P3) >> RCC_PLL3DIVR_P3_Pos) + 1UL);
5079 }
5080
5081 /**
5082 * @brief Get PLL3 Q Coefficient
5083 * @rmtoll PLL3DIVR Q3 LL_RCC_PLL3_GetQ
5084 * @retval A value between 1 and 128
5085 */
5086 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetQ(void)
5087 {
5088 return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_Q3) >> RCC_PLL3DIVR_Q3_Pos) + 1UL);
5089 }
5090
5091 /**
5092 * @brief Get PLL3 R Coefficient
5093 * @rmtoll PLL3DIVR R3 LL_RCC_PLL3_GetR
5094 * @retval A value between 1 and 128
5095 */
5096 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetR(void)
5097 {
5098 return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_R3) >> RCC_PLL3DIVR_R3_Pos) + 1UL);
5099 }
5100
5101 /**
5102 * @brief Get PLL3 FRACN Coefficient
5103 * @rmtoll PLL3FRACR FRACN3 LL_RCC_PLL3_GetFRACN
5104 * @retval A value between 0 and 8191 (0x1FFF)
5105 */
5106 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetFRACN(void)
5107 {
5108 return (uint32_t)(READ_BIT(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3) >> RCC_PLL3FRACR_FRACN3_Pos);
5109 }
5110
5111 /**
5112 * @brief Set PLL3 N Coefficient
5113 * @note This API shall be called only when PLL3 is disabled.
5114 * @rmtoll PLL3DIVR N3 LL_RCC_PLL3_SetN
5115 * @param N parameter can be a value between 4 and 512
5116 */
5117 __STATIC_INLINE void LL_RCC_PLL3_SetN(uint32_t N)
5118 {
5119 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_N3, (N-1UL) << RCC_PLL3DIVR_N3_Pos);
5120 }
5121
5122 /**
5123 * @brief Set PLL3 M Coefficient
5124 * @note This API shall be called only when PLL3 is disabled.
5125 * @rmtoll PLLCKSELR DIVM3 LL_RCC_PLL3_SetM
5126 * @param M parameter can be a value between 0 and 63
5127 */
5128 __STATIC_INLINE void LL_RCC_PLL3_SetM(uint32_t M)
5129 {
5130 MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM3, M << RCC_PLLCKSELR_DIVM3_Pos);
5131 }
5132
5133 /**
5134 * @brief Set PLL3 P Coefficient
5135 * @note This API shall be called only when PLL3 is disabled.
5136 * @rmtoll PLL3DIVR P3 LL_RCC_PLL3_SetP
5137 * @param P parameter can be a value between 1 and 128
5138 */
5139 __STATIC_INLINE void LL_RCC_PLL3_SetP(uint32_t P)
5140 {
5141 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_P3, (P-1UL) << RCC_PLL3DIVR_P3_Pos);
5142 }
5143
5144 /**
5145 * @brief Set PLL3 Q Coefficient
5146 * @note This API shall be called only when PLL3 is disabled.
5147 * @rmtoll PLL3DIVR Q3 LL_RCC_PLL3_SetQ
5148 * @param Q parameter can be a value between 1 and 128
5149 */
5150 __STATIC_INLINE void LL_RCC_PLL3_SetQ(uint32_t Q)
5151 {
5152 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_Q3, (Q-1UL) << RCC_PLL3DIVR_Q3_Pos);
5153 }
5154
5155 /**
5156 * @brief Set PLL3 R Coefficient
5157 * @note This API shall be called only when PLL3 is disabled.
5158 * @rmtoll PLL3DIVR R3 LL_RCC_PLL3_SetR
5159 * @param R parameter can be a value between 1 and 128
5160 */
5161 __STATIC_INLINE void LL_RCC_PLL3_SetR(uint32_t R)
5162 {
5163 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_R3, (R-1UL) << RCC_PLL3DIVR_R3_Pos);
5164 }
5165
5166 /**
5167 * @brief Set PLL3 FRACN Coefficient
5168 * @rmtoll PLL3FRACR FRACN3 LL_RCC_PLL3_SetFRACN
5169 * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF)
5170 */
5171 __STATIC_INLINE void LL_RCC_PLL3_SetFRACN(uint32_t FRACN)
5172 {
5173 MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, FRACN << RCC_PLL3FRACR_FRACN3_Pos);
5174 }
5175
5176
5177 /**
5178 * @}
5179 */
5180
5181
5182 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
5183 * @{
5184 */
5185
5186 /**
5187 * @brief Clear LSI ready interrupt flag
5188 * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY
5189 * @retval None
5190 */
5191 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
5192 {
5193 SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
5194 }
5195
5196 /**
5197 * @brief Clear LSE ready interrupt flag
5198 * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY
5199 * @retval None
5200 */
5201 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
5202 {
5203 SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
5204 }
5205
5206 /**
5207 * @brief Clear HSI ready interrupt flag
5208 * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
5209 * @retval None
5210 */
5211 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
5212 {
5213 SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
5214 }
5215
5216 /**
5217 * @brief Clear HSE ready interrupt flag
5218 * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY
5219 * @retval None
5220 */
5221 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
5222 {
5223 SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
5224 }
5225
5226 /**
5227 * @brief Clear CSI ready interrupt flag
5228 * @rmtoll CICR CSIRDYC LL_RCC_ClearFlag_CSIRDY
5229 * @retval None
5230 */
5231 __STATIC_INLINE void LL_RCC_ClearFlag_CSIRDY(void)
5232 {
5233 SET_BIT(RCC->CICR, RCC_CICR_CSIRDYC);
5234 }
5235
5236 /**
5237 * @brief Clear HSI48 ready interrupt flag
5238 * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY
5239 * @retval None
5240 */
5241 __STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
5242 {
5243 SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
5244 }
5245
5246 /**
5247 * @brief Clear PLL1 ready interrupt flag
5248 * @rmtoll CICR PLL1RDYC LL_RCC_ClearFlag_PLL1RDY
5249 * @retval None
5250 */
5251 __STATIC_INLINE void LL_RCC_ClearFlag_PLL1RDY(void)
5252 {
5253 SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
5254 }
5255
5256 /**
5257 * @brief Clear PLL2 ready interrupt flag
5258 * @rmtoll CICR PLL2RDYC LL_RCC_ClearFlag_PLL2RDY
5259 * @retval None
5260 */
5261 __STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void)
5262 {
5263 SET_BIT(RCC->CICR, RCC_CICR_PLL2RDYC);
5264 }
5265
5266 /**
5267 * @brief Clear PLL3 ready interrupt flag
5268 * @rmtoll CICR PLL3RDYC LL_RCC_ClearFlag_PLL3RDY
5269 * @retval None
5270 */
5271 __STATIC_INLINE void LL_RCC_ClearFlag_PLL3RDY(void)
5272 {
5273 SET_BIT(RCC->CICR, RCC_CICR_PLL3RDYC);
5274 }
5275
5276 /**
5277 * @brief Clear LSE Clock security system interrupt flag
5278 * @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS
5279 * @retval None
5280 */
5281 __STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
5282 {
5283 SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
5284 }
5285
5286 /**
5287 * @brief Clear HSE Clock security system interrupt flag
5288 * @rmtoll CICR HSECSSC LL_RCC_ClearFlag_HSECSS
5289 * @retval None
5290 */
5291 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
5292 {
5293 SET_BIT(RCC->CICR, RCC_CICR_HSECSSC);
5294 }
5295
5296 /**
5297 * @brief Check if LSI ready interrupt occurred or not
5298 * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
5299 * @retval State of bit (1 or 0).
5300 */
5301 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
5302 {
5303 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF))?1UL:0UL);
5304 }
5305
5306 /**
5307 * @brief Check if LSE ready interrupt occurred or not
5308 * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
5309 * @retval State of bit (1 or 0).
5310 */
5311 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
5312 {
5313 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF))?1UL:0UL);
5314 }
5315
5316 /**
5317 * @brief Check if HSI ready interrupt occurred or not
5318 * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
5319 * @retval State of bit (1 or 0).
5320 */
5321 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
5322 {
5323 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF))?1UL:0UL);
5324 }
5325
5326 /**
5327 * @brief Check if HSE ready interrupt occurred or not
5328 * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
5329 * @retval State of bit (1 or 0).
5330 */
5331 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
5332 {
5333 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF))?1UL:0UL);
5334 }
5335
5336 /**
5337 * @brief Check if CSI ready interrupt occurred or not
5338 * @rmtoll CIFR CSIRDYF LL_RCC_IsActiveFlag_CSIRDY
5339 * @retval State of bit (1 or 0).
5340 */
5341 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CSIRDY(void)
5342 {
5343 return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSIRDYF) == (RCC_CIFR_CSIRDYF))?1UL:0UL);
5344 }
5345
5346 /**
5347 * @brief Check if HSI48 ready interrupt occurred or not
5348 * @rmtoll CIFR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY
5349 * @retval State of bit (1 or 0).
5350 */
5351 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
5352 {
5353 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF))?1UL:0UL);
5354 }
5355
5356 /**
5357 * @brief Check if PLL1 ready interrupt occurred or not
5358 * @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLL1RDY
5359 * @retval State of bit (1 or 0).
5360 */
5361 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL1RDY(void)
5362 {
5363 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF))?1UL:0UL);
5364 }
5365
5366 /**
5367 * @brief Check if PLL2 ready interrupt occurred or not
5368 * @rmtoll CIFR PLL2RDYF LL_RCC_IsActiveFlag_PLL2RDY
5369 * @retval State of bit (1 or 0).
5370 */
5371 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void)
5372 {
5373 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL2RDYF) == (RCC_CIFR_PLL2RDYF))?1UL:0UL);
5374 }
5375
5376 /**
5377 * @brief Check if PLL3 ready interrupt occurred or not
5378 * @rmtoll CIFR PLL3RDYF LL_RCC_IsActiveFlag_PLL3RDY
5379 * @retval State of bit (1 or 0).
5380 */
5381 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL3RDY(void)
5382 {
5383 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL3RDYF) == (RCC_CIFR_PLL3RDYF))?1UL:0UL);
5384 }
5385
5386 /**
5387 * @brief Check if LSE Clock security system interrupt occurred or not
5388 * @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS
5389 * @retval State of bit (1 or 0).
5390 */
5391 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
5392 {
5393 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF))?1UL:0UL);
5394 }
5395
5396 /**
5397 * @brief Check if HSE Clock security system interrupt occurred or not
5398 * @rmtoll CIFR HSECSSF LL_RCC_IsActiveFlag_HSECSS
5399 * @retval State of bit (1 or 0).
5400 */
5401 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
5402 {
5403 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSECSSF) == (RCC_CIFR_HSECSSF))?1UL:0UL);
5404 }
5405
5406 /**
5407 * @brief Check if RCC flag Low Power D1 reset is set or not.
5408 * @rmtoll RSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST (*)\n
5409 * RSR LPWR1RSTF LL_RCC_IsActiveFlag_LPWRRST (**)
5410 *
5411 * (*) Only available for single core devices
5412 * (**) Only available for Dual core devices
5413 * @retval State of bit (1 or 0).
5414 */
5415 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
5416 {
5417 #if defined(DUAL_CORE)
5418 return ((READ_BIT(RCC->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF))?1UL:0UL);
5419 #else
5420 return ((READ_BIT(RCC->RSR, RCC_RSR_LPWRRSTF) == (RCC_RSR_LPWRRSTF))?1UL:0UL);
5421 #endif /*DUAL_CORE*/
5422 }
5423
5424 #if defined(DUAL_CORE)
5425 /**
5426 * @brief Check if RCC flag Low Power D2 reset is set or not.
5427 * @rmtoll RSR LPWR2RSTF LL_RCC_IsActiveFlag_LPWR2RST
5428 * @retval State of bit (1 or 0).
5429 */
5430 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWR2RST(void)
5431 {
5432 return ((READ_BIT(RCC->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF))?1UL:0UL);
5433 }
5434 #endif /*DUAL_CORE*/
5435
5436 /**
5437 * @brief Check if RCC flag Window Watchdog 1 reset is set or not.
5438 * @rmtoll RSR WWDG1RSTF LL_RCC_IsActiveFlag_WWDG1RST
5439 * @retval State of bit (1 or 0).
5440 */
5441 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDG1RST(void)
5442 {
5443 return ((READ_BIT(RCC->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF))?1UL:0UL);
5444 }
5445
5446 #if defined(DUAL_CORE)
5447 /**
5448 * @brief Check if RCC flag Window Watchdog 2 reset is set or not.
5449 * @rmtoll RSR WWDG2RSTF LL_RCC_IsActiveFlag_WWDG2RST
5450 * @retval State of bit (1 or 0).
5451 */
5452 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDG2RST(void)
5453 {
5454 return ((READ_BIT(RCC->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF))?1UL:0UL);
5455 }
5456 #endif /*DUAL_CORE*/
5457
5458 /**
5459 * @brief Check if RCC flag Independent Watchdog 1 reset is set or not.
5460 * @rmtoll RSR IWDG1RSTF LL_RCC_IsActiveFlag_IWDG1RST
5461 * @retval State of bit (1 or 0).
5462 */
5463 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDG1RST(void)
5464 {
5465 return ((READ_BIT(RCC->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF))?1UL:0UL);
5466 }
5467
5468 #if defined(DUAL_CORE)
5469 /**
5470 * @brief Check if RCC flag Independent Watchdog 2 reset is set or not.
5471 * @rmtoll RSR IWDG2RSTF LL_RCC_IsActiveFlag_IWDG2RST
5472 * @retval State of bit (1 or 0).
5473 */
5474 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDG2RST(void)
5475 {
5476 return ((READ_BIT(RCC->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF))?1UL:0UL);
5477 }
5478 #endif /*DUAL_CORE*/
5479
5480 /**
5481 * @brief Check if RCC flag Software reset is set or not.
5482 * @rmtoll RSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST (*)\n
5483 * RSR SFT1RSTF LL_RCC_IsActiveFlag_SFTRST (**)
5484 *
5485 * (*) Only available for single core devices
5486 * (**) Only available for Dual core devices
5487 * @retval State of bit (1 or 0).
5488 */
5489 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
5490 {
5491 #if defined(DUAL_CORE)
5492 return ((READ_BIT(RCC->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF))?1UL:0UL);
5493 #else
5494 return ((READ_BIT(RCC->RSR, RCC_RSR_SFTRSTF) == (RCC_RSR_SFTRSTF))?1UL:0UL);
5495 #endif /*DUAL_CORE*/
5496 }
5497
5498 #if defined(DUAL_CORE)
5499 /**
5500 * @brief Check if RCC flag Software reset is set or not.
5501 * @rmtoll RSR SFT2RSTF LL_RCC_IsActiveFlag_SFT2RST
5502 * @retval State of bit (1 or 0).
5503 */
5504 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFT2RST(void)
5505 {
5506 return ((READ_BIT(RCC->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF))?1UL:0UL);
5507 }
5508 #endif /*DUAL_CORE*/
5509
5510 /**
5511 * @brief Check if RCC flag POR/PDR reset is set or not.
5512 * @rmtoll RSR PORRSTF LL_RCC_IsActiveFlag_PORRST
5513 * @retval State of bit (1 or 0).
5514 */
5515 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
5516 {
5517 return ((READ_BIT(RCC->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF))?1UL:0UL);
5518 }
5519
5520 /**
5521 * @brief Check if RCC flag Pin reset is set or not.
5522 * @rmtoll RSR PINRSTF LL_RCC_IsActiveFlag_PINRST
5523 * @retval State of bit (1 or 0).
5524 */
5525 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
5526 {
5527 return ((READ_BIT(RCC->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF))?1UL:0UL);
5528 }
5529
5530 /**
5531 * @brief Check if RCC flag BOR reset is set or not.
5532 * @rmtoll RSR BORRSTF LL_RCC_IsActiveFlag_BORRST
5533 * @retval State of bit (1 or 0).
5534 */
5535 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
5536 {
5537 return ((READ_BIT(RCC->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF))?1UL:0UL);
5538 }
5539
5540 #if defined(RCC_RSR_D1RSTF)
5541 /**
5542 * @brief Check if RCC flag D1 reset is set or not.
5543 * @rmtoll RSR D1RSTF LL_RCC_IsActiveFlag_D1RST
5544 * @retval State of bit (1 or 0).
5545 */
5546 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_D1RST(void)
5547 {
5548 return ((READ_BIT(RCC->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF))?1UL:0UL);
5549 }
5550 #endif /* RCC_RSR_D1RSTF */
5551
5552 #if defined(RCC_RSR_CDRSTF)
5553 /**
5554 * @brief Check if RCC flag CD reset is set or not.
5555 * @rmtoll RSR CDRSTF LL_RCC_IsActiveFlag_CDRST
5556 * @retval State of bit (1 or 0).
5557 */
5558 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CDRST(void)
5559 {
5560 return ((READ_BIT(RCC->RSR, RCC_RSR_CDRSTF) == (RCC_RSR_CDRSTF))?1UL:0UL);
5561 }
5562 #endif /* RCC_RSR_CDRSTF */
5563
5564 #if defined(RCC_RSR_D2RSTF)
5565 /**
5566 * @brief Check if RCC flag D2 reset is set or not.
5567 * @rmtoll RSR D2RSTF LL_RCC_IsActiveFlag_D2RST
5568 * @retval State of bit (1 or 0).
5569 */
5570 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_D2RST(void)
5571 {
5572 return ((READ_BIT(RCC->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF))?1UL:0UL);
5573 }
5574 #endif /* RCC_RSR_D2RSTF */
5575
5576 #if defined(RCC_RSR_C1RSTF) || defined(RCC_RSR_CPURSTF)
5577 /**
5578 * @brief Check if RCC flag CPU reset is set or not.
5579 * @rmtoll RSR CPURSTF LL_RCC_IsActiveFlag_CPURST (*)\n
5580 * RSR C1RSTF LL_RCC_IsActiveFlag_CPURST (**)
5581 *
5582 * (*) Only available for single core devices
5583 * (**) Only available for Dual core devices
5584 * @retval State of bit (1 or 0).
5585 */
5586 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CPURST(void)
5587 {
5588 #if defined(DUAL_CORE)
5589 return ((READ_BIT(RCC->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF))?1UL:0UL);
5590 #else
5591 return ((READ_BIT(RCC->RSR, RCC_RSR_CPURSTF) == (RCC_RSR_CPURSTF))?1UL:0UL);
5592 #endif/*DUAL_CORE*/
5593 }
5594 #endif /* defined(RCC_RSR_C1RSTF) || defined(RCC_RSR_CPURSTF) */
5595
5596 #if defined(DUAL_CORE)
5597 /**
5598 * @brief Check if RCC flag CPU2 reset is set or not.
5599 * @rmtoll RSR C2RSTF LL_RCC_IsActiveFlag_CPU2RST
5600 * @retval State of bit (1 or 0).
5601 */
5602 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CPU2RST(void)
5603 {
5604 return ((READ_BIT(RCC->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF))?1UL:0UL);
5605 }
5606 #endif /*DUAL_CORE*/
5607
5608 /**
5609 * @brief Set RMVF bit to clear all reset flags.
5610 * @rmtoll RSR RMVF LL_RCC_ClearResetFlags
5611 * @retval None
5612 */
5613 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
5614 {
5615 SET_BIT(RCC->RSR, RCC_RSR_RMVF);
5616 }
5617
5618 #if defined(DUAL_CORE)
5619 /**
5620 * @brief Check if RCC_C1 flag Low Power D1 reset is set or not.
5621 * @rmtoll RSR LPWR1RSTF LL_C1_RCC_IsActiveFlag_LPWRRST
5622 * @retval State of bit (1 or 0).
5623 */
5624 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_LPWRRST(void)
5625 {
5626 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF))?1UL:0UL);
5627 }
5628
5629 /**
5630 * @brief Check if RCC_C1 flag Low Power D2 reset is set or not.
5631 * @rmtoll RSR LPWR2RSTF LL_C1_RCC_IsActiveFlag_LPWR2RST
5632 * @retval State of bit (1 or 0).
5633 */
5634 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_LPWR2RST(void)
5635 {
5636 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF))?1UL:0UL);
5637 }
5638
5639 /**
5640 * @brief Check if RCC_C1 flag Window Watchdog 1 reset is set or not.
5641 * @rmtoll RSR WWDG1RSTF LL_C1_RCC_IsActiveFlag_WWDG1RST
5642 * @retval State of bit (1 or 0).
5643 */
5644 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_WWDG1RST(void)
5645 {
5646 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF))?1UL:0UL);
5647 }
5648
5649 /**
5650 * @brief Check if RCC_C1 flag Window Watchdog 2 reset is set or not.
5651 * @rmtoll RSR WWDG2RSTF LL_C1_RCC_IsActiveFlag_WWDG2RST
5652 * @retval State of bit (1 or 0).
5653 */
5654 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_WWDG2RST(void)
5655 {
5656 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF))?1UL:0UL);
5657 }
5658
5659 /**
5660 * @brief Check if RCC_C1 flag Independent Watchdog 1 reset is set or not.
5661 * @rmtoll RSR IWDG1RSTF LL_C1_RCC_IsActiveFlag_IWDG1RST
5662 * @retval State of bit (1 or 0).
5663 */
5664 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_IWDG1RST(void)
5665 {
5666 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF))?1UL:0UL);
5667 }
5668
5669 /**
5670 * @brief Check if RCC_C1 flag Independent Watchdog 2 reset is set or not.
5671 * @rmtoll RSR IWDG2RSTF LL_C1_RCC_IsActiveFlag_IWDG2RST
5672 * @retval State of bit (1 or 0).
5673 */
5674 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_IWDG2RST(void)
5675 {
5676 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF))?1UL:0UL);
5677 }
5678
5679 /**
5680 * @brief Check if RCC_C1 flag Software reset is set or not.
5681 * @rmtoll RSR SFT1RSTF LL_C1_RCC_IsActiveFlag_SFTRST
5682 * @retval State of bit (1 or 0).
5683 */
5684 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_SFTRST(void)
5685 {
5686 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF))?1UL:0UL);
5687 }
5688
5689 /**
5690 * @brief Check if RCC_C1 flag Software reset is set or not.
5691 * @rmtoll RSR SFT2RSTF LL_C1_RCC_IsActiveFlag_SFT2RST
5692 * @retval State of bit (1 or 0).
5693 */
5694 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_SFT2RST(void)
5695 {
5696 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF))?1UL:0UL);
5697 }
5698
5699 /**
5700 * @brief Check if RCC_C1 flag POR/PDR reset is set or not.
5701 * @rmtoll RSR PORRSTF LL_C1_RCC_IsActiveFlag_PORRST
5702 * @retval State of bit (1 or 0).
5703 */
5704 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_PORRST(void)
5705 {
5706 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF))?1UL:0UL);
5707 }
5708
5709 /**
5710 * @brief Check if RCC_C1 flag Pin reset is set or not.
5711 * @rmtoll RSR PINRSTF LL_C1_RCC_IsActiveFlag_PINRST
5712 * @retval State of bit (1 or 0).
5713 */
5714 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_PINRST(void)
5715 {
5716 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF))?1UL:0UL);
5717 }
5718
5719 /**
5720 * @brief Check if RCC_C1 flag BOR reset is set or not.
5721 * @rmtoll RSR BORRSTF LL_C1_RCC_IsActiveFlag_BORRST
5722 * @retval State of bit (1 or 0).
5723 */
5724 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_BORRST(void)
5725 {
5726 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF))?1UL:0UL);
5727 }
5728
5729 /**
5730 * @brief Check if RCC_C1 flag D1 reset is set or not.
5731 * @rmtoll RSR D1RSTF LL_C1_RCC_IsActiveFlag_D1RST
5732 * @retval State of bit (1 or 0).
5733 */
5734 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_D1RST(void)
5735 {
5736 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF))?1UL:0UL);
5737 }
5738
5739 /**
5740 * @brief Check if RCC_C1 flag D2 reset is set or not.
5741 * @rmtoll RSR D2RSTF LL_C1_RCC_IsActiveFlag_D2RST
5742 * @retval State of bit (1 or 0).
5743 */
5744 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_D2RST(void)
5745 {
5746 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF))?1UL:0UL);
5747 }
5748
5749 /**
5750 * @brief Check if RCC_C1 flag CPU reset is set or not.
5751 * @rmtoll RSR C1RSTF LL_C1_RCC_IsActiveFlag_CPURST
5752 * @retval State of bit (1 or 0).
5753 */
5754 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_CPURST(void)
5755 {
5756 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF))?1UL:0UL);
5757 }
5758
5759 /**
5760 * @brief Check if RCC_C1 flag CPU2 reset is set or not.
5761 * @rmtoll RSR C2RSTF LL_C1_RCC_IsActiveFlag_CPU2RST
5762 * @retval State of bit (1 or 0).
5763 */
5764 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_CPU2RST(void)
5765 {
5766 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF))?1UL:0UL);
5767 }
5768
5769 /**
5770 * @brief Set RMVF bit to clear the reset flags.
5771 * @rmtoll RSR RMVF LL_C1_RCC_ClearResetFlags
5772 * @retval None
5773 */
5774 __STATIC_INLINE void LL_C1_RCC_ClearResetFlags(void)
5775 {
5776 SET_BIT(RCC_C1->RSR, RCC_RSR_RMVF);
5777 }
5778
5779 /**
5780 * @brief Check if RCC_C2 flag Low Power D1 reset is set or not.
5781 * @rmtoll RSR LPWR1RSTF LL_C2_RCC_IsActiveFlag_LPWRRST
5782 * @retval State of bit (1 or 0).
5783 */
5784 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_LPWRRST(void)
5785 {
5786 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF))?1UL:0UL);
5787 }
5788
5789 /**
5790 * @brief Check if RCC_C2 flag Low Power D2 reset is set or not.
5791 * @rmtoll RSR LPWR2RSTF LL_C2_RCC_IsActiveFlag_LPWR2RST
5792 * @retval State of bit (1 or 0).
5793 */
5794 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_LPWR2RST(void)
5795 {
5796 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF))?1UL:0UL);
5797 }
5798
5799 /**
5800 * @brief Check if RCC_C2 flag Window Watchdog 1 reset is set or not.
5801 * @rmtoll RSR WWDG1RSTF LL_C2_RCC_IsActiveFlag_WWDG1RST
5802 * @retval State of bit (1 or 0).
5803 */
5804 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_WWDG1RST(void)
5805 {
5806 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF))?1UL:0UL);
5807 }
5808
5809 /**
5810 * @brief Check if RCC_C2 flag Window Watchdog 2 reset is set or not.
5811 * @rmtoll RSR WWDG2RSTF LL_C2_RCC_IsActiveFlag_WWDG2RST
5812 * @retval State of bit (1 or 0).
5813 */
5814 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_WWDG2RST(void)
5815 {
5816 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF))?1UL:0UL);
5817 }
5818
5819 /**
5820 * @brief Check if RCC_C2 flag Independent Watchdog 1 reset is set or not.
5821 * @rmtoll RSR IWDG1RSTF LL_C2_RCC_IsActiveFlag_IWDG1RST
5822 * @retval State of bit (1 or 0).
5823 */
5824 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_IWDG1RST(void)
5825 {
5826 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF))?1UL:0UL);
5827 }
5828
5829 /**
5830 * @brief Check if RCC_C2 flag Independent Watchdog 2 reset is set or not.
5831 * @rmtoll RSR IWDG2RSTF LL_C2_RCC_IsActiveFlag_IWDG2RST
5832 * @retval State of bit (1 or 0).
5833 */
5834 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_IWDG2RST(void)
5835 {
5836 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF))?1UL:0UL);
5837 }
5838
5839 /**
5840 * @brief Check if RCC_C2 flag Software reset is set or not.
5841 * @rmtoll RSR SFT1RSTF LL_C2_RCC_IsActiveFlag_SFTRST
5842 * @retval State of bit (1 or 0).
5843 */
5844 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_SFTRST(void)
5845 {
5846 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF))?1UL:0UL);
5847 }
5848
5849 /**
5850 * @brief Check if RCC_C2 flag Software reset is set or not.
5851 * @rmtoll RSR SFT2RSTF LL_C2_RCC_IsActiveFlag_SFT2RST
5852 * @retval State of bit (1 or 0).
5853 */
5854 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_SFT2RST(void)
5855 {
5856 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF))?1UL:0UL);
5857 }
5858
5859 /**
5860 * @brief Check if RCC_C2 flag POR/PDR reset is set or not.
5861 * @rmtoll RSR PORRSTF LL_C2_RCC_IsActiveFlag_PORRST
5862 * @retval State of bit (1 or 0).
5863 */
5864 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_PORRST(void)
5865 {
5866 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF))?1UL:0UL);
5867 }
5868
5869 /**
5870 * @brief Check if RCC_C2 flag Pin reset is set or not.
5871 * @rmtoll RSR PINRSTF LL_C2_RCC_IsActiveFlag_PINRST
5872 * @retval State of bit (1 or 0).
5873 */
5874 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_PINRST(void)
5875 {
5876 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF))?1UL:0UL);
5877 }
5878
5879 /**
5880 * @brief Check if RCC_C2 flag BOR reset is set or not.
5881 * @rmtoll RSR BORRSTF LL_C2_RCC_IsActiveFlag_BORRST
5882 * @retval State of bit (1 or 0).
5883 */
5884 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_BORRST(void)
5885 {
5886 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF))?1UL:0UL);
5887 }
5888
5889 /**
5890 * @brief Check if RCC_C2 flag D1 reset is set or not.
5891 * @rmtoll RSR D1RSTF LL_C2_RCC_IsActiveFlag_D1RST
5892 * @retval State of bit (1 or 0).
5893 */
5894 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_D1RST(void)
5895 {
5896 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF))?1UL:0UL);
5897 }
5898
5899 /**
5900 * @brief Check if RCC_C2 flag D2 reset is set or not.
5901 * @rmtoll RSR D2RSTF LL_C2_RCC_IsActiveFlag_D2RST
5902 * @retval State of bit (1 or 0).
5903 */
5904 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_D2RST(void)
5905 {
5906 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF))?1UL:0UL);
5907 }
5908
5909 /**
5910 * @brief Check if RCC_C2 flag CPU reset is set or not.
5911 * @rmtoll RSR C1RSTF LL_C2_RCC_IsActiveFlag_CPURST
5912 * @retval State of bit (1 or 0).
5913 */
5914 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_CPURST(void)
5915 {
5916 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF))?1UL:0UL);
5917 }
5918
5919 /**
5920 * @brief Check if RCC_C2 flag CPU2 reset is set or not.
5921 * @rmtoll RSR C2RSTF LL_C2_RCC_IsActiveFlag_CPU2RST
5922 * @retval State of bit (1 or 0).
5923 */
5924 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_CPU2RST(void)
5925 {
5926 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF))?1UL:0UL);
5927 }
5928
5929 /**
5930 * @brief Set RMVF bit to clear the reset flags.
5931 * @rmtoll RSR RMVF LL_C2_RCC_ClearResetFlags
5932 * @retval None
5933 */
5934 __STATIC_INLINE void LL_C2_RCC_ClearResetFlags(void)
5935 {
5936 SET_BIT(RCC_C2->RSR, RCC_RSR_RMVF);
5937 }
5938 #endif /*DUAL_CORE*/
5939
5940 /**
5941 * @}
5942 */
5943
5944 /** @defgroup RCC_LL_EF_IT_Management IT Management
5945 * @{
5946 */
5947
5948 /**
5949 * @brief Enable LSI ready interrupt
5950 * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY
5951 * @retval None
5952 */
5953 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
5954 {
5955 SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
5956 }
5957
5958 /**
5959 * @brief Enable LSE ready interrupt
5960 * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY
5961 * @retval None
5962 */
5963 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
5964 {
5965 SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
5966 }
5967
5968 /**
5969 * @brief Enable HSI ready interrupt
5970 * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
5971 * @retval None
5972 */
5973 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
5974 {
5975 SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
5976 }
5977
5978 /**
5979 * @brief Enable HSE ready interrupt
5980 * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY
5981 * @retval None
5982 */
5983 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
5984 {
5985 SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
5986 }
5987
5988 /**
5989 * @brief Enable CSI ready interrupt
5990 * @rmtoll CIER CSIRDYIE LL_RCC_EnableIT_CSIRDY
5991 * @retval None
5992 */
5993 __STATIC_INLINE void LL_RCC_EnableIT_CSIRDY(void)
5994 {
5995 SET_BIT(RCC->CIER, RCC_CIER_CSIRDYIE);
5996 }
5997
5998 /**
5999 * @brief Enable HSI48 ready interrupt
6000 * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY
6001 * @retval None
6002 */
6003 __STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
6004 {
6005 SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
6006 }
6007
6008 /**
6009 * @brief Enable PLL1 ready interrupt
6010 * @rmtoll CIER PLL1RDYIE LL_RCC_EnableIT_PLL1RDY
6011 * @retval None
6012 */
6013 __STATIC_INLINE void LL_RCC_EnableIT_PLL1RDY(void)
6014 {
6015 SET_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);
6016 }
6017
6018 /**
6019 * @brief Enable PLL2 ready interrupt
6020 * @rmtoll CIER PLL2RDYIE LL_RCC_EnableIT_PLL2RDY
6021 * @retval None
6022 */
6023 __STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void)
6024 {
6025 SET_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE);
6026 }
6027
6028 /**
6029 * @brief Enable PLL3 ready interrupt
6030 * @rmtoll CIER PLL3RDYIE LL_RCC_EnableIT_PLL3RDY
6031 * @retval None
6032 */
6033 __STATIC_INLINE void LL_RCC_EnableIT_PLL3RDY(void)
6034 {
6035 SET_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE);
6036 }
6037
6038 /**
6039 * @brief Enable LSECSS interrupt
6040 * @rmtoll CIER LSECSSIE LL_RCC_EnableIT_LSECSS
6041 * @retval None
6042 */
6043 __STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
6044 {
6045 SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
6046 }
6047
6048 /**
6049 * @brief Disable LSI ready interrupt
6050 * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY
6051 * @retval None
6052 */
6053 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
6054 {
6055 CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
6056 }
6057
6058 /**
6059 * @brief Disable LSE ready interrupt
6060 * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY
6061 * @retval None
6062 */
6063 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
6064 {
6065 CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
6066 }
6067
6068 /**
6069 * @brief Disable HSI ready interrupt
6070 * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
6071 * @retval None
6072 */
6073 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
6074 {
6075 CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
6076 }
6077
6078 /**
6079 * @brief Disable HSE ready interrupt
6080 * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY
6081 * @retval None
6082 */
6083 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
6084 {
6085 CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
6086 }
6087
6088 /**
6089 * @brief Disable CSI ready interrupt
6090 * @rmtoll CIER CSIRDYIE LL_RCC_DisableIT_CSIRDY
6091 * @retval None
6092 */
6093 __STATIC_INLINE void LL_RCC_DisableIT_CSIRDY(void)
6094 {
6095 CLEAR_BIT(RCC->CIER, RCC_CIER_CSIRDYIE);
6096 }
6097
6098 /**
6099 * @brief Disable HSI48 ready interrupt
6100 * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY
6101 * @retval None
6102 */
6103 __STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
6104 {
6105 CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
6106 }
6107
6108 /**
6109 * @brief Disable PLL1 ready interrupt
6110 * @rmtoll CIER PLL1RDYIE LL_RCC_DisableIT_PLL1RDY
6111 * @retval None
6112 */
6113 __STATIC_INLINE void LL_RCC_DisableIT_PLL1RDY(void)
6114 {
6115 CLEAR_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);
6116 }
6117
6118 /**
6119 * @brief Disable PLL2 ready interrupt
6120 * @rmtoll CIER PLL2RDYIE LL_RCC_DisableIT_PLL2RDY
6121 * @retval None
6122 */
6123 __STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void)
6124 {
6125 CLEAR_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE);
6126 }
6127
6128 /**
6129 * @brief Disable PLL3 ready interrupt
6130 * @rmtoll CIER PLL3RDYIE LL_RCC_DisableIT_PLL3RDY
6131 * @retval None
6132 */
6133 __STATIC_INLINE void LL_RCC_DisableIT_PLL3RDY(void)
6134 {
6135 CLEAR_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE);
6136 }
6137
6138 /**
6139 * @brief Disable LSECSS interrupt
6140 * @rmtoll CIER LSECSSIE LL_RCC_DisableIT_LSECSS
6141 * @retval None
6142 */
6143 __STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
6144 {
6145 CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
6146 }
6147
6148 /**
6149 * @brief Checks if LSI ready interrupt source is enabled or disabled.
6150 * @rmtoll CIER LSIRDYIE LL_RCC_IsEnableIT_LSIRDY
6151 * @retval State of bit (1 or 0).
6152 */
6153 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSIRDY(void)
6154 {
6155 return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE)?1UL:0UL);
6156 }
6157
6158 /**
6159 * @brief Checks if LSE ready interrupt source is enabled or disabled.
6160 * @rmtoll CIER LSERDYIE LL_RCC_IsEnableIT_LSERDY
6161 * @retval State of bit (1 or 0).
6162 */
6163 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSERDY(void)
6164 {
6165 return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE)?1UL:0UL);
6166 }
6167
6168 /**
6169 * @brief Checks if HSI ready interrupt source is enabled or disabled.
6170 * @rmtoll CIER HSIRDYIE LL_RCC_IsEnableIT_HSIRDY
6171 * @retval State of bit (1 or 0).
6172 */
6173 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSIRDY(void)
6174 {
6175 return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE)?1UL:0UL);
6176 }
6177
6178 /**
6179 * @brief Checks if HSE ready interrupt source is enabled or disabled.
6180 * @rmtoll CIER HSERDYIE LL_RCC_IsEnableIT_HSERDY
6181 * @retval State of bit (1 or 0).
6182 */
6183 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSERDY(void)
6184 {
6185 return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE)?1UL:0UL);
6186 }
6187
6188 /**
6189 * @brief Checks if CSI ready interrupt source is enabled or disabled.
6190 * @rmtoll CIER CSIRDYIE LL_RCC_IsEnableIT_CSIRDY
6191 * @retval State of bit (1 or 0).
6192 */
6193 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_CSIRDY(void)
6194 {
6195 return ((READ_BIT(RCC->CIER, RCC_CIER_CSIRDYIE) == RCC_CIER_CSIRDYIE)?1UL:0UL);
6196 }
6197
6198 /**
6199 * @brief Checks if HSI48 ready interrupt source is enabled or disabled.
6200 * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnableIT_HSI48RDY
6201 * @retval State of bit (1 or 0).
6202 */
6203 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSI48RDY(void)
6204 {
6205 return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == RCC_CIER_HSI48RDYIE)?1UL:0UL);
6206 }
6207
6208 /**
6209 * @brief Checks if PLL1 ready interrupt source is enabled or disabled.
6210 * @rmtoll CIER PLL1RDYIE LL_RCC_IsEnableIT_PLL1RDY
6211 * @retval State of bit (1 or 0).
6212 */
6213 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL1RDY(void)
6214 {
6215 return ((READ_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE) == RCC_CIER_PLL1RDYIE)?1UL:0UL);
6216 }
6217
6218 /**
6219 * @brief Checks if PLL2 ready interrupt source is enabled or disabled.
6220 * @rmtoll CIER PLL2RDYIE LL_RCC_IsEnableIT_PLL2RDY
6221 * @retval State of bit (1 or 0).
6222 */
6223 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL2RDY(void)
6224 {
6225 return ((READ_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE) == RCC_CIER_PLL2RDYIE)?1UL:0UL);
6226 }
6227
6228 /**
6229 * @brief Checks if PLL3 ready interrupt source is enabled or disabled.
6230 * @rmtoll CIER PLL3RDYIE LL_RCC_IsEnableIT_PLL3RDY
6231 * @retval State of bit (1 or 0).
6232 */
6233 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL3RDY(void)
6234 {
6235 return ((READ_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE) == RCC_CIER_PLL3RDYIE)?1UL:0UL);
6236 }
6237
6238 /**
6239 * @brief Checks if LSECSS interrupt source is enabled or disabled.
6240 * @rmtoll CIER LSECSSIE LL_RCC_IsEnableIT_LSECSS
6241 * @retval State of bit (1 or 0).
6242 */
6243 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSECSS(void)
6244 {
6245 return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == RCC_CIER_LSECSSIE)?1UL:0UL);
6246 }
6247 /**
6248 * @}
6249 */
6250
6251 #if defined(USE_FULL_LL_DRIVER)
6252 /** @defgroup RCC_LL_EF_Init De-initialization function
6253 * @{
6254 */
6255 void LL_RCC_DeInit(void);
6256 /**
6257 * @}
6258 */
6259
6260 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
6261 * @{
6262 */
6263 uint32_t LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t PQR);
6264
6265 void LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks);
6266 void LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks);
6267 void LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks);
6268 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
6269
6270 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
6271 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
6272 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
6273 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
6274 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
6275 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
6276 uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource);
6277 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
6278 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource);
6279 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
6280 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
6281 #if defined(DFSDM2_BASE)
6282 uint32_t LL_RCC_GetDFSDM2ClockFreq(uint32_t DFSDMxSource);
6283 #endif /* DFSDM2 */
6284 #if defined(DSI)
6285 uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);
6286 #endif /* DSI */
6287 uint32_t LL_RCC_GetSPDIFClockFreq(uint32_t SPDIFxSource);
6288 uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource);
6289 uint32_t LL_RCC_GetSWPClockFreq(uint32_t SWPxSource);
6290 uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource);
6291 uint32_t LL_RCC_GetFMCClockFreq(uint32_t FMCxSource);
6292 #if defined(QUADSPI)
6293 uint32_t LL_RCC_GetQSPIClockFreq(uint32_t QSPIxSource);
6294 #endif /* QUADSPI */
6295 #if defined(OCTOSPI1) || defined(OCTOSPI2)
6296 uint32_t LL_RCC_GetOSPIClockFreq(uint32_t OSPIxSource);
6297 #endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
6298 uint32_t LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource);
6299
6300
6301 /**
6302 * @}
6303 */
6304 #endif /* USE_FULL_LL_DRIVER */
6305
6306 /**
6307 * @}
6308 */
6309
6310
6311 /**
6312 * @}
6313 */
6314 #endif /* defined(RCC) */
6315
6316 /**
6317 * @}
6318 */
6319
6320 #ifdef __cplusplus
6321 }
6322 #endif
6323
6324 #endif /* STM32H7xx_LL_RCC_H */
6325
6326 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
INAV: Navigation-enabled flight control software