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Set blackbox file handler to NULL after closing file
[inav.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Src / stm32h7xx_hal.c
blobc52df22d8fde58ebfc3860efd550a5077a699e2a
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_hal.c
4 * @author MCD Application Team
5 * @brief HAL module driver.
6 * This is the common part of the HAL initialization
7 *
8 @verbatim
9 ==============================================================================
10 ##### How to use this driver #####
11 ==============================================================================
12 [..]
13 The common HAL driver contains a set of generic and common APIs that can be
14 used by the PPP peripheral drivers and the user to start using the HAL.
15 [..]
16 The HAL contains two APIs' categories:
17 (+) Common HAL APIs
18 (+) Services HAL APIs
19
20 @endverbatim
21 ******************************************************************************
22 * @attention
23 *
24 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
25 * All rights reserved.</center></h2>
26 *
27 * This software component is licensed by ST under BSD 3-Clause license,
28 * the "License"; You may not use this file except in compliance with the
29 * License. You may obtain a copy of the License at:
30 * opensource.org/licenses/BSD-3-Clause
31 *
32 ******************************************************************************
33 */
34
35 /* Includes ------------------------------------------------------------------*/
36 #include "stm32h7xx_hal.h"
37
38 /** @addtogroup STM32H7xx_HAL_Driver
39 * @{
40 */
41
42 /** @defgroup HAL HAL
43 * @brief HAL module driver.
44 * @{
45 */
46
47 /* Private typedef -----------------------------------------------------------*/
48 /* Private define ------------------------------------------------------------*/
49 /**
50 * @brief STM32H7xx HAL Driver version number V1.7.0
51 */
52 #define __STM32H7xx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */
53 #define __STM32H7xx_HAL_VERSION_SUB1 (0x07UL) /*!< [23:16] sub1 version */
54 #define __STM32H7xx_HAL_VERSION_SUB2 (0x00UL) /*!< [15:8] sub2 version */
55 #define __STM32H7xx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */
56 #define __STM32H7xx_HAL_VERSION ((__STM32H7xx_HAL_VERSION_MAIN << 24)\
57 |(__STM32H7xx_HAL_VERSION_SUB1 << 16)\
58 |(__STM32H7xx_HAL_VERSION_SUB2 << 8 )\
59 |(__STM32H7xx_HAL_VERSION_RC))
60
61 #define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
62 #define VREFBUF_TIMEOUT_VALUE (uint32_t)10 /* 10 ms */
63
64 /* Private macro -------------------------------------------------------------*/
65 /* Private variables ---------------------------------------------------------*/
66 /* Exported variables --------------------------------------------------------*/
67
68 /** @defgroup HAL_Exported_Variables HAL Exported Variables
69 * @{
70 */
71 __IO uint32_t uwTick;
72 uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
73 HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
74 /**
75 * @}
76 */
77
78 /* Private function prototypes -----------------------------------------------*/
79 /* Private functions ---------------------------------------------------------*/
80
81 /** @defgroup HAL_Private_Functions HAL Private Functions
82 * @{
83 */
84
85 /** @defgroup HAL_Group1 Initialization and de-initialization Functions
86 * @brief Initialization and de-initialization functions
87 *
88 @verbatim
89 ===============================================================================
90 ##### Initialization and de-initialization functions #####
91 ===============================================================================
92 [..] This section provides functions allowing to:
93 (+) Initializes the Flash interface the NVIC allocation and initial clock
94 configuration. It initializes the systick also when timeout is needed
95 and the backup domain when enabled.
96 (+) De-Initializes common part of the HAL.
97 (+) Configure The time base source to have 1ms time base with a dedicated
98 Tick interrupt priority.
99 (++) SysTick timer is used by default as source of time base, but user
100 can eventually implement his proper time base source (a general purpose
101 timer for example or other time source), keeping in mind that Time base
102 duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
103 handled in milliseconds basis.
104 (++) Time base configuration function (HAL_InitTick ()) is called automatically
105 at the beginning of the program after reset by HAL_Init() or at any time
106 when clock is configured, by HAL_RCC_ClockConfig().
107 (++) Source of time base is configured to generate interrupts at regular
108 time intervals. Care must be taken if HAL_Delay() is called from a
109 peripheral ISR process, the Tick interrupt line must have higher priority
110 (numerically lower) than the peripheral interrupt. Otherwise the caller
111 ISR process will be blocked.
112 (++) functions affecting time base configurations are declared as __weak
113 to make override possible in case of other implementations in user file.
114 @endverbatim
115 * @{
116 */
117
118 /**
119 * @brief This function is used to initialize the HAL Library; it must be the first
120 * instruction to be executed in the main program (before to call any other
121 * HAL function), it performs the following:
122 * Configures the SysTick to generate an interrupt each 1 millisecond,
123 * which is clocked by the HSI (at this stage, the clock is not yet
124 * configured and thus the system is running from the internal HSI at 16 MHz).
125 * Set NVIC Group Priority to 4.
126 * Calls the HAL_MspInit() callback function defined in user file
127 * "stm32h7xx_hal_msp.c" to do the global low level hardware initialization
128 *
129 * @note SysTick is used as time base for the HAL_Delay() function, the application
130 * need to ensure that the SysTick time base is always set to 1 millisecond
131 * to have correct HAL operation.
132 * @retval HAL status
133 */
134 HAL_StatusTypeDef HAL_Init(void)
135 {
136
137 #if defined(DUAL_CORE) && defined(CORE_CM4)
138 /* Configure Cortex-M4 Instruction cache through ART accelerator */
139 __HAL_RCC_ART_CLK_ENABLE(); /* Enable the Cortex-M4 ART Clock */
140 __HAL_ART_CONFIG_BASE_ADDRESS(0x08100000UL); /* Configure the Cortex-M4 ART Base address to the Flash Bank 2 : */
141 __HAL_ART_ENABLE(); /* Enable the Cortex-M4 ART */
142 #endif /* DUAL_CORE && CORE_CM4 */
143
144 /* Set Interrupt Group Priority */
145 HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
146
147 /* Update the SystemCoreClock global variable */
148 #if defined(RCC_D1CFGR_D1CPRE)
149 SystemCoreClock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
150 #else
151 SystemCoreClock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
152 #endif
153
154 /* Update the SystemD2Clock global variable */
155 #if defined(RCC_D1CFGR_HPRE)
156 SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
157 #else
158 SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
159 #endif
160
161 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
162 if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
163 {
164 return HAL_ERROR;
165 }
166
167 /* Init the low level hardware */
168 HAL_MspInit();
169
170 /* Return function status */
171 return HAL_OK;
172 }
173
174 /**
175 * @brief This function de-Initializes common part of the HAL and stops the systick.
176 * This function is optional.
177 * @retval HAL status
178 */
179 HAL_StatusTypeDef HAL_DeInit(void)
180 {
181 /* Reset of all peripherals */
182 __HAL_RCC_AHB3_FORCE_RESET();
183 __HAL_RCC_AHB3_RELEASE_RESET();
184
185 __HAL_RCC_AHB1_FORCE_RESET();
186 __HAL_RCC_AHB1_RELEASE_RESET();
187
188 __HAL_RCC_AHB2_FORCE_RESET();
189 __HAL_RCC_AHB2_RELEASE_RESET();
190
191 __HAL_RCC_AHB4_FORCE_RESET();
192 __HAL_RCC_AHB4_RELEASE_RESET();
193
194 __HAL_RCC_APB3_FORCE_RESET();
195 __HAL_RCC_APB3_RELEASE_RESET();
196
197 __HAL_RCC_APB1L_FORCE_RESET();
198 __HAL_RCC_APB1L_RELEASE_RESET();
199
200 __HAL_RCC_APB1H_FORCE_RESET();
201 __HAL_RCC_APB1H_RELEASE_RESET();
202
203 __HAL_RCC_APB2_FORCE_RESET();
204 __HAL_RCC_APB2_RELEASE_RESET();
205
206 __HAL_RCC_APB4_FORCE_RESET();
207 __HAL_RCC_APB4_RELEASE_RESET();
208
209 /* De-Init the low level hardware */
210 HAL_MspDeInit();
211
212 /* Return function status */
213 return HAL_OK;
214 }
215
216 /**
217 * @brief Initializes the MSP.
218 * @retval None
219 */
220 __weak void HAL_MspInit(void)
221 {
222 /* NOTE : This function Should not be modified, when the callback is needed,
223 the HAL_MspInit could be implemented in the user file
224 */
225 }
226
227 /**
228 * @brief DeInitializes the MSP.
229 * @retval None
230 */
231 __weak void HAL_MspDeInit(void)
232 {
233 /* NOTE : This function Should not be modified, when the callback is needed,
234 the HAL_MspDeInit could be implemented in the user file
235 */
236 }
237
238 /**
239 * @brief This function configures the source of the time base.
240 * The time source is configured to have 1ms time base with a dedicated
241 * Tick interrupt priority.
242 * @note This function is called automatically at the beginning of program after
243 * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
244 * @note In the default implementation, SysTick timer is the source of time base.
245 * It is used to generate interrupts at regular time intervals.
246 * Care must be taken if HAL_Delay() is called from a peripheral ISR process,
247 * The the SysTick interrupt must have higher priority (numerically lower)
248 * than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
249 * The function is declared as __weak to be overwritten in case of other
250 * implementation in user file.
251 * @param TickPriority: Tick interrupt priority.
252 * @retval HAL status
253 */
254 __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
255 {
256 /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/
257 if((uint32_t)uwTickFreq == 0UL)
258 {
259 return HAL_ERROR;
260 }
261
262 #if defined(DUAL_CORE)
263 if (HAL_GetCurrentCPUID() == CM7_CPUID)
264 {
265 /* Cortex-M7 detected */
266 /* Configure the SysTick to have interrupt in 1ms time basis*/
267 if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U)
268 {
269 return HAL_ERROR;
270 }
271 }
272 else
273 {
274 /* Cortex-M4 detected */
275 /* Configure the SysTick to have interrupt in 1ms time basis*/
276 if (HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / (1000UL / (uint32_t)uwTickFreq)) > 0U)
277 {
278 return HAL_ERROR;
279 }
280 }
281 #else
282 /* Configure the SysTick to have interrupt in 1ms time basis*/
283 if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U)
284 {
285 return HAL_ERROR;
286 }
287 #endif
288
289 /* Configure the SysTick IRQ priority */
290 if (TickPriority < (1UL << __NVIC_PRIO_BITS))
291 {
292 HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
293 uwTickPrio = TickPriority;
294 }
295 else
296 {
297 return HAL_ERROR;
298 }
299
300 /* Return function status */
301 return HAL_OK;
302 }
303
304 /**
305 * @}
306 */
307
308 /** @defgroup HAL_Group2 HAL Control functions
309 * @brief HAL Control functions
310 *
311 @verbatim
312 ===============================================================================
313 ##### HAL Control functions #####
314 ===============================================================================
315 [..] This section provides functions allowing to:
316 (+) Provide a tick value in millisecond
317 (+) Provide a blocking delay in millisecond
318 (+) Suspend the time base source interrupt
319 (+) Resume the time base source interrupt
320 (+) Get the HAL API driver version
321 (+) Get the device identifier
322 (+) Get the device revision identifier
323 (+) Enable/Disable Debug module during SLEEP mode
324 (+) Enable/Disable Debug module during STOP mode
325 (+) Enable/Disable Debug module during STANDBY mode
326
327 @endverbatim
328 * @{
329 */
330
331 /**
332 * @brief This function is called to increment a global variable "uwTick"
333 * used as application time base.
334 * @note In the default implementation, this variable is incremented each 1ms
335 * in Systick ISR.
336 * @note This function is declared as __weak to be overwritten in case of other
337 * implementations in user file.
338 * @retval None
339 */
340 __weak void HAL_IncTick(void)
341 {
342 uwTick += (uint32_t)uwTickFreq;
343 }
344
345 /**
346 * @brief Provides a tick value in millisecond.
347 * @note This function is declared as __weak to be overwritten in case of other
348 * implementations in user file.
349 * @retval tick value
350 */
351 __weak uint32_t HAL_GetTick(void)
352 {
353 return uwTick;
354 }
355
356 /**
357 * @brief This function returns a tick priority.
358 * @retval tick priority
359 */
360 uint32_t HAL_GetTickPrio(void)
361 {
362 return uwTickPrio;
363 }
364
365 /**
366 * @brief Set new tick Freq.
367 * @retval Status
368 */
369 HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
370 {
371 HAL_StatusTypeDef status = HAL_OK;
372 HAL_TickFreqTypeDef prevTickFreq;
373
374 assert_param(IS_TICKFREQ(Freq));
375
376 if (uwTickFreq != Freq)
377 {
378
379 /* Back up uwTickFreq frequency */
380 prevTickFreq = uwTickFreq;
381
382 /* Update uwTickFreq global variable used by HAL_InitTick() */
383 uwTickFreq = Freq;
384
385 /* Apply the new tick Freq */
386 status = HAL_InitTick(uwTickPrio);
387 if (status != HAL_OK)
388 {
389 /* Restore previous tick frequency */
390 uwTickFreq = prevTickFreq;
391 }
392 }
393
394 return status;
395 }
396
397 /**
398 * @brief Return tick frequency.
399 * @retval tick period in Hz
400 */
401 HAL_TickFreqTypeDef HAL_GetTickFreq(void)
402 {
403 return uwTickFreq;
404 }
405
406 /**
407 * @brief This function provides minimum delay (in milliseconds) based
408 * on variable incremented.
409 * @note In the default implementation , SysTick timer is the source of time base.
410 * It is used to generate interrupts at regular time intervals where uwTick
411 * is incremented.
412 * @note This function is declared as __weak to be overwritten in case of other
413 * implementations in user file.
414 * @param Delay specifies the delay time length, in milliseconds.
415 * @retval None
416 */
417 __weak void HAL_Delay(uint32_t Delay)
418 {
419 uint32_t tickstart = HAL_GetTick();
420 uint32_t wait = Delay;
421
422 /* Add a freq to guarantee minimum wait */
423 if (wait < HAL_MAX_DELAY)
424 {
425 wait += (uint32_t)(uwTickFreq);
426 }
427
428 while ((HAL_GetTick() - tickstart) < wait)
429 {
430 }
431 }
432
433 /**
434 * @brief Suspend Tick increment.
435 * @note In the default implementation , SysTick timer is the source of time base. It is
436 * used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
437 * is called, the the SysTick interrupt will be disabled and so Tick increment
438 * is suspended.
439 * @note This function is declared as __weak to be overwritten in case of other
440 * implementations in user file.
441 * @retval None
442 */
443 __weak void HAL_SuspendTick(void)
444 {
445 /* Disable SysTick Interrupt */
446 SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
447 }
448
449 /**
450 * @brief Resume Tick increment.
451 * @note In the default implementation , SysTick timer is the source of time base. It is
452 * used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
453 * is called, the the SysTick interrupt will be enabled and so Tick increment
454 * is resumed.
455 * @note This function is declared as __weak to be overwritten in case of other
456 * implementations in user file.
457 * @retval None
458 */
459 __weak void HAL_ResumeTick(void)
460 {
461 /* Enable SysTick Interrupt */
462 SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
463 }
464
465 /**
466 * @brief Returns the HAL revision
467 * @retval version : 0xXYZR (8bits for each decimal, R for RC)
468 */
469 uint32_t HAL_GetHalVersion(void)
470 {
471 return __STM32H7xx_HAL_VERSION;
472 }
473
474 /**
475 * @brief Returns the device revision identifier.
476 * @retval Device revision identifier
477 */
478 uint32_t HAL_GetREVID(void)
479 {
480 return((DBGMCU->IDCODE) >> 16);
481 }
482
483 /**
484 * @brief Returns the device identifier.
485 * @retval Device identifier
486 */
487 uint32_t HAL_GetDEVID(void)
488 {
489 return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
490 }
491
492 /**
493 * @brief Return the first word of the unique device identifier (UID based on 96 bits)
494 * @retval Device identifier
495 */
496 uint32_t HAL_GetUIDw0(void)
497 {
498 return(READ_REG(*((uint32_t *)UID_BASE)));
499 }
500
501 /**
502 * @brief Return the second word of the unique device identifier (UID based on 96 bits)
503 * @retval Device identifier
504 */
505 uint32_t HAL_GetUIDw1(void)
506 {
507 return(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
508 }
509
510 /**
511 * @brief Return the third word of the unique device identifier (UID based on 96 bits)
512 * @retval Device identifier
513 */
514 uint32_t HAL_GetUIDw2(void)
515 {
516 return(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
517 }
518
519 /**
520 * @brief Configure the internal voltage reference buffer voltage scale.
521 * @param VoltageScaling specifies the output voltage to achieve
522 * This parameter can be one of the following values:
523 * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.048 V.
524 * This requires VDDA equal to or higher than 2.4 V.
525 * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT2 around 2.5 V.
526 * This requires VDDA equal to or higher than 2.8 V.
527 * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE2: VREF_OUT3 around 1.5 V.
528 * This requires VDDA equal to or higher than 1.8 V.
529 * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE3: VREF_OUT4 around 1.8 V.
530 * This requires VDDA equal to or higher than 2.1 V.
531 * @retval None
532 */
533 void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling)
534 {
535 /* Check the parameters */
536 assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling));
537
538 MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling);
539 }
540
541 /**
542 * @brief Configure the internal voltage reference buffer high impedance mode.
543 * @param Mode specifies the high impedance mode
544 * This parameter can be one of the following values:
545 * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output.
546 * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance.
547 * @retval None
548 */
549 void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode)
550 {
551 /* Check the parameters */
552 assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode));
553
554 MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode);
555 }
556
557 /**
558 * @brief Tune the Internal Voltage Reference buffer (VREFBUF).
559 * @retval None
560 */
561 void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue)
562 {
563 /* Check the parameters */
564 assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue));
565
566 MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue);
567 }
568
569 /**
570 * @brief Enable the Internal Voltage Reference buffer (VREFBUF).
571 * @retval HAL_OK/HAL_TIMEOUT
572 */
573 HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void)
574 {
575 uint32_t tickstart;
576
577 SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
578
579 /* Get Start Tick*/
580 tickstart = HAL_GetTick();
581
582 /* Wait for VRR bit */
583 while(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0UL)
584 {
585 if((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE)
586 {
587 return HAL_TIMEOUT;
588 }
589 }
590
591 return HAL_OK;
592 }
593
594 /**
595 * @brief Disable the Internal Voltage Reference buffer (VREFBUF).
596 *
597 * @retval None
598 */
599 void HAL_SYSCFG_DisableVREFBUF(void)
600 {
601 CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
602 }
603
604 #if defined(SYSCFG_PMCR_EPIS_SEL)
605 /**
606 * @brief Ethernet PHY Interface Selection either MII or RMII
607 * @param SYSCFG_ETHInterface: Selects the Ethernet PHY interface
608 * This parameter can be one of the following values:
609 * @arg SYSCFG_ETH_MII : Select the Media Independent Interface
610 * @arg SYSCFG_ETH_RMII: Select the Reduced Media Independent Interface
611 * @retval None
612 */
613 void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface)
614 {
615 /* Check the parameter */
616 assert_param(IS_SYSCFG_ETHERNET_CONFIG(SYSCFG_ETHInterface));
617
618 MODIFY_REG(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL, (uint32_t)(SYSCFG_ETHInterface));
619 }
620 #endif /* SYSCFG_PMCR_EPIS_SEL */
621
622 /**
623 * @brief Analog Switch control for dual analog pads.
624 * @param SYSCFG_AnalogSwitch: Selects the analog pad
625 * This parameter can be one or a combination of the following values:
626 * @arg SYSCFG_SWITCH_PA0 : Select PA0 analog switch
627 * @arg SYSCFG_SWITCH_PA1: Select PA1 analog switch
628 * @arg SYSCFG_SWITCH_PC2 : Select PC2 analog switch
629 * @arg SYSCFG_SWITCH_PC3: Select PC3 analog switch
630 * @param SYSCFG_SwitchState: Open or Close the analog switch between dual pads (PXn and PXn_C)
631 * This parameter can be one or a combination of the following values:
632 * @arg SYSCFG_SWITCH_PA0_OPEN
633 * @arg SYSCFG_SWITCH_PA0_CLOSE
634 * @arg SYSCFG_SWITCH_PA1_OPEN
635 * @arg SYSCFG_SWITCH_PA1_CLOSE
636 * @arg SYSCFG_SWITCH_PC2_OPEN
637 * @arg SYSCFG_SWITCH_PC2_CLOSE
638 * @arg SYSCFG_SWITCH_PC3_OPEN
639 * @arg SYSCFG_SWITCH_PC3_CLOSE
640 * @retval None
641 */
642
643 void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState )
644 {
645 /* Check the parameter */
646 assert_param(IS_SYSCFG_ANALOG_SWITCH(SYSCFG_AnalogSwitch));
647 assert_param(IS_SYSCFG_SWITCH_STATE(SYSCFG_SwitchState));
648
649 MODIFY_REG(SYSCFG->PMCR, (uint32_t) SYSCFG_AnalogSwitch, (uint32_t)(SYSCFG_SwitchState));
650 }
651
652 #if defined(SYSCFG_PMCR_BOOSTEN)
653 /**
654 * @brief Enables the booster to reduce the total harmonic distortion of the analog
655 * switch when the supply voltage is lower than 2.7 V.
656 * @note Activating the booster allows to guaranty the analog switch AC performance
657 * when the supply voltage is below 2.7 V: in this case, the analog switch
658 * performance is the same on the full voltage range
659 * @retval None
660 */
661 void HAL_SYSCFG_EnableBOOST(void)
662 {
663 SET_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
664 }
665
666 /**
667 * @brief Disables the booster
668 * @note Activating the booster allows to guaranty the analog switch AC performance
669 * when the supply voltage is below 2.7 V: in this case, the analog switch
670 * performance is the same on the full voltage range
671 * @retval None
672 */
673 void HAL_SYSCFG_DisableBOOST(void)
674 {
675 CLEAR_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
676 }
677 #endif /* SYSCFG_PMCR_BOOSTEN */
678
679 #if defined (SYSCFG_UR2_BOOT_ADD0) || defined (SYSCFG_UR2_BCM7_ADD0)
680 /**
681 * @brief BootCM7 address 0 configuration
682 * @param BootRegister :Specifies the Boot Address register (Address0 or Address1)
683 * This parameter can be one of the following values:
684 * @arg SYSCFG_BOOT_ADDR0 : Select the boot address0
685 * @arg SYSCFG_BOOT_ADDR1: Select the boot address1
686 * @param BootAddress :Specifies the CM7 Boot Address to be loaded in Address0 or Address1
687 * @retval None
688 */
689 void HAL_SYSCFG_CM7BootAddConfig(uint32_t BootRegister, uint32_t BootAddress)
690 {
691 /* Check the parameters */
692 assert_param(IS_SYSCFG_BOOT_REGISTER(BootRegister));
693 assert_param(IS_SYSCFG_BOOT_ADDRESS(BootAddress));
694 if ( BootRegister == SYSCFG_BOOT_ADDR0 )
695 {
696 /* Configure CM7 BOOT ADD0 */
697 #if defined(DUAL_CORE)
698 MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0, ((BootAddress >> 16) << SYSCFG_UR2_BCM7_ADD0_Pos));
699 #else
700 MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0, ((BootAddress >> 16) << SYSCFG_UR2_BOOT_ADD0_Pos));
701 #endif /*DUAL_CORE*/
702 }
703 else
704 {
705 /* Configure CM7 BOOT ADD1 */
706 #if defined(DUAL_CORE)
707 MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1, (BootAddress >> 16));
708 #else
709 MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1, (BootAddress >> 16));
710 #endif /*DUAL_CORE*/
711 }
712 }
713 #endif /* SYSCFG_UR2_BOOT_ADD0 || SYSCFG_UR2_BCM7_ADD0 */
714
715 #if defined(DUAL_CORE)
716 /**
717 * @brief BootCM4 address 0 configuration
718 * @param BootRegister :Specifies the Boot Address register (Address0 or Address1)
719 * This parameter can be one of the following values:
720 * @arg SYSCFG_BOOT_ADDR0 : Select the boot address0
721 * @arg SYSCFG_BOOT_ADDR1: Select the boot address1
722 * @param BootAddress :Specifies the CM4 Boot Address to be loaded in Address0 or Address1
723 * @retval None
724 */
725 void HAL_SYSCFG_CM4BootAddConfig(uint32_t BootRegister, uint32_t BootAddress)
726 {
727 /* Check the parameters */
728 assert_param(IS_SYSCFG_BOOT_REGISTER(BootRegister));
729 assert_param(IS_SYSCFG_BOOT_ADDRESS(BootAddress));
730
731 if ( BootRegister == SYSCFG_BOOT_ADDR0 )
732 {
733 /* Configure CM4 BOOT ADD0 */
734 MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0, ((BootAddress >> 16)<< SYSCFG_UR3_BCM4_ADD0_Pos));
735 }
736
737 else
738 {
739 /* Configure CM4 BOOT ADD1 */
740 MODIFY_REG(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1, (BootAddress >> 16));
741 }
742 }
743
744 /**
745 * @brief Enables the Cortex-M7 boot
746 * @retval None
747 */
748 void HAL_SYSCFG_EnableCM7BOOT(void)
749 {
750 SET_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM7);
751 }
752
753 /**
754 * @brief Disables the Cortex-M7 boot
755 * @note Disabling the boot will gate the CPU clock
756 * @retval None
757 */
758 void HAL_SYSCFG_DisableCM7BOOT(void)
759 {
760 CLEAR_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM7) ;
761 }
762
763 /**
764 * @brief Enables the Cortex-M4 boot
765 * @retval None
766 */
767 void HAL_SYSCFG_EnableCM4BOOT(void)
768 {
769 SET_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4);
770 }
771
772 /**
773 * @brief Disables the Cortex-M4 boot
774 * @note Disabling the boot will gate the CPU clock
775 * @retval None
776 */
777 void HAL_SYSCFG_DisableCM4BOOT(void)
778 {
779 CLEAR_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4);
780 }
781 #endif /*DUAL_CORE*/
782 /**
783 * @brief Enables the I/O Compensation Cell.
784 * @note The I/O compensation cell can be used only when the device supply
785 * voltage ranges from 2.4 to 3.6 V.
786 * @retval None
787 */
788 void HAL_EnableCompensationCell(void)
789 {
790 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN) ;
791 }
792
793 /**
794 * @brief Power-down the I/O Compensation Cell.
795 * @note The I/O compensation cell can be used only when the device supply
796 * voltage ranges from 2.4 to 3.6 V.
797 * @retval None
798 */
799 void HAL_DisableCompensationCell(void)
800 {
801 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN);
802 }
803
804
805 /**
806 * @brief To Enable optimize the I/O speed when the product voltage is low.
807 * @note This bit is active only if PRODUCT_BELOW_25V user option bit is set. It must be
808 * used only if the product supply voltage is below 2.5 V. Setting this bit when VDD is
809 * higher than 2.5 V might be destructive.
810 * @retval None
811 */
812 void HAL_SYSCFG_EnableIOSpeedOptimize(void)
813 {
814 #if defined(SYSCFG_CCCSR_HSLV)
815 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
816 #else
817 SET_BIT(SYSCFG->CCCSR, (SYSCFG_CCCSR_HSLV0| SYSCFG_CCCSR_HSLV1 | SYSCFG_CCCSR_HSLV2 | SYSCFG_CCCSR_HSLV3));
818 #endif /* SYSCFG_CCCSR_HSLV */
819 }
820
821 /**
822 * @brief To Disable optimize the I/O speed when the product voltage is low.
823 * @note This bit is active only if PRODUCT_BELOW_25V user option bit is set. It must be
824 * used only if the product supply voltage is below 2.5 V. Setting this bit when VDD is
825 * higher than 2.5 V might be destructive.
826 * @retval None
827 */
828 void HAL_SYSCFG_DisableIOSpeedOptimize(void)
829 {
830 #if defined(SYSCFG_CCCSR_HSLV)
831 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
832 #else
833 CLEAR_BIT(SYSCFG->CCCSR, (SYSCFG_CCCSR_HSLV0| SYSCFG_CCCSR_HSLV1 | SYSCFG_CCCSR_HSLV2 | SYSCFG_CCCSR_HSLV3));
834 #endif /* SYSCFG_CCCSR_HSLV */
835 }
836
837 /**
838 * @brief Code selection for the I/O Compensation cell
839 * @param SYSCFG_CompCode: Selects the code to be applied for the I/O compensation cell
840 * This parameter can be one of the following values:
841 * @arg SYSCFG_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR)
842 * @arg SYSCFG_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)
843 * @retval None
844 */
845 void HAL_SYSCFG_CompensationCodeSelect(uint32_t SYSCFG_CompCode)
846 {
847 /* Check the parameter */
848 assert_param(IS_SYSCFG_CODE_SELECT(SYSCFG_CompCode));
849 MODIFY_REG(SYSCFG->CCCSR, SYSCFG_CCCSR_CS, (uint32_t)(SYSCFG_CompCode));
850 }
851
852 /**
853 * @brief Code selection for the I/O Compensation cell
854 * @param SYSCFG_PMOSCode: PMOS compensation code
855 * This code is applied to the I/O compensation cell when the CS bit of the
856 * SYSCFG_CMPCR is set
857 * @param SYSCFG_NMOSCode: NMOS compensation code
858 * This code is applied to the I/O compensation cell when the CS bit of the
859 * SYSCFG_CMPCR is set
860 * @retval None
861 */
862 void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode )
863 {
864 /* Check the parameter */
865 assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_PMOSCode));
866 assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_NMOSCode));
867 MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC|SYSCFG_CCCR_PCC, (((uint32_t)(SYSCFG_PMOSCode)<< 4)|(uint32_t)(SYSCFG_NMOSCode)) );
868 }
869
870 #if defined(SYSCFG_CCCR_NCC_MMC)
871 /**
872 * @brief Code selection for the I/O Compensation cell
873 * @param SYSCFG_PMOSCode: VDDMMC PMOS compensation code
874 * This code is applied to the I/O compensation cell when the CS bit of the
875 * SYSCFG_CMPCR is set
876 * @param SYSCFG_NMOSCode: VDDMMC NMOS compensation code
877 * This code is applied to the I/O compensation cell when the CS bit of the
878 * SYSCFG_CMPCR is set
879 * @retval None
880 */
881 void HAL_SYSCFG_VDDMMC_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode )
882 {
883 /* Check the parameter */
884 assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_PMOSCode));
885 assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_NMOSCode));
886 MODIFY_REG(SYSCFG->CCCR, (SYSCFG_CCCR_NCC_MMC | SYSCFG_CCCR_PCC_MMC), (((uint32_t)(SYSCFG_PMOSCode)<< 4)|(uint32_t)(SYSCFG_NMOSCode)) );
887 }
888 #endif /* SYSCFG_CCCR_NCC_MMC */
889
890 /**
891 * @brief Enable the Debug Module during Domain1/CDomain SLEEP mode
892 * @retval None
893 */
894 void HAL_EnableDBGSleepMode(void)
895 {
896 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
897 }
898
899 /**
900 * @brief Disable the Debug Module during Domain1/CDomain SLEEP mode
901 * @retval None
902 */
903 void HAL_DisableDBGSleepMode(void)
904 {
905 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
906 }
907
908
909 /**
910 * @brief Enable the Debug Module during Domain1/CDomain STOP mode
911 * @retval None
912 */
913 void HAL_EnableDBGStopMode(void)
914 {
915 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
916 }
917
918 /**
919 * @brief Disable the Debug Module during Domain1/CDomain STOP mode
920 * @retval None
921 */
922 void HAL_DisableDBGStopMode(void)
923 {
924 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
925 }
926
927 /**
928 * @brief Enable the Debug Module during Domain1/CDomain STANDBY mode
929 * @retval None
930 */
931 void HAL_EnableDBGStandbyMode(void)
932 {
933 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
934 }
935
936 /**
937 * @brief Disable the Debug Module during Domain1/CDomain STANDBY mode
938 * @retval None
939 */
940 void HAL_DisableDBGStandbyMode(void)
941 {
942 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
943 }
944
945 #if defined(DUAL_CORE)
946 /**
947 * @brief Enable the Debug Module during Domain1 SLEEP mode
948 * @retval None
949 */
950 void HAL_EnableDomain2DBGSleepMode(void)
951 {
952 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);
953 }
954
955 /**
956 * @brief Disable the Debug Module during Domain2 SLEEP mode
957 * @retval None
958 */
959 void HAL_DisableDomain2DBGSleepMode(void)
960 {
961 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);
962 }
963
964 /**
965 * @brief Enable the Debug Module during Domain2 STOP mode
966 * @retval None
967 */
968 void HAL_EnableDomain2DBGStopMode(void)
969 {
970 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);
971 }
972
973 /**
974 * @brief Disable the Debug Module during Domain2 STOP mode
975 * @retval None
976 */
977 void HAL_DisableDomain2DBGStopMode(void)
978 {
979 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);
980 }
981
982 /**
983 * @brief Enable the Debug Module during Domain2 STANDBY mode
984 * @retval None
985 */
986 void HAL_EnableDomain2DBGStandbyMode(void)
987 {
988 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);
989 }
990
991 /**
992 * @brief Disable the Debug Module during Domain2 STANDBY mode
993 * @retval None
994 */
995 void HAL_DisableDomain2DBGStandbyMode(void)
996 {
997 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);
998 }
999 #endif /*DUAL_CORE*/
1000
1001 /**
1002 * @brief Enable the Debug Module during Domain3/SRDomain STOP mode
1003 * @retval None
1004 */
1005 void HAL_EnableDomain3DBGStopMode(void)
1006 {
1007 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
1008 }
1009 /**
1010 * @brief Disable the Debug Module during Domain3/SRDomain STOP mode
1011 * @retval None
1012 */
1013 void HAL_DisableDomain3DBGStopMode(void)
1014 {
1015 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
1016 }
1017
1018 /**
1019 * @brief Enable the Debug Module during Domain3/SRDomain STANDBY mode
1020 * @retval None
1021 */
1022 void HAL_EnableDomain3DBGStandbyMode(void)
1023 {
1024 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
1025 }
1026
1027 /**
1028 * @brief Disable the Debug Module during Domain3/SRDomain STANDBY mode
1029 * @retval None
1030 */
1031 void HAL_DisableDomain3DBGStandbyMode(void)
1032 {
1033 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
1034 }
1035
1036 /**
1037 * @brief Set the FMC Memory Mapping Swapping config.
1038 * @param BankMapConfig: Defines the FMC Bank mapping configuration. This parameter can be
1039 FMC_SWAPBMAP_DISABLE, FMC_SWAPBMAP_SDRAM_SRAM, FMC_SWAPBMAP_SDRAMB2
1040 * @retval HAL state
1041 */
1042 void HAL_SetFMCMemorySwappingConfig(uint32_t BankMapConfig)
1043 {
1044 /* Check the parameter */
1045 assert_param(IS_FMC_SWAPBMAP_MODE(BankMapConfig));
1046 MODIFY_REG(FMC_Bank1_R->BTCR[0], FMC_BCR1_BMAP, BankMapConfig);
1047 }
1048
1049 /**
1050 * @brief Get FMC Bank mapping mode.
1051 * @retval The FMC Bank mapping mode. This parameter can be
1052 FMC_SWAPBMAP_DISABLE, FMC_SWAPBMAP_SDRAM_SRAM, FMC_SWAPBMAP_SDRAMB2
1053 */
1054 uint32_t HAL_GetFMCMemorySwappingConfig(void)
1055 {
1056 return READ_BIT(FMC_Bank1_R->BTCR[0], FMC_BCR1_BMAP);
1057 }
1058
1059 /**
1060 * @brief Configure the EXTI input event line edge
1061 * @note No edge configuration for direct lines but for configurable lines:(EXTI_LINE0..EXTI_LINE21),
1062 * EXTI_LINE49,EXTI_LINE51,EXTI_LINE82,EXTI_LINE84,EXTI_LINE85 and EXTI_LINE86.
1063 * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
1064 * (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
1065 * @param EXTI_Edge: Specifies EXTI line Edge used.
1066 * This parameter can be one of the following values :
1067 * @arg EXTI_RISING_EDGE : Configurable line, with Rising edge trigger detection
1068 * @arg EXTI_FALLING_EDGE: Configurable line, with Falling edge trigger detection
1069 * @retval None
1070 */
1071 void HAL_EXTI_EdgeConfig(uint32_t EXTI_Line , uint32_t EXTI_Edge )
1072 {
1073 /* Check the parameter */
1074 assert_param(IS_HAL_EXTI_CONFIG_LINE(EXTI_Line));
1075 assert_param(IS_EXTI_EDGE_LINE(EXTI_Edge));
1076
1077 /* Clear Rising Falling edge configuration */
1078 CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
1079 CLEAR_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
1080
1081 if( (EXTI_Edge & EXTI_RISING_EDGE) == EXTI_RISING_EDGE)
1082 {
1083 SET_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
1084 }
1085 if( (EXTI_Edge & EXTI_FALLING_EDGE) == EXTI_FALLING_EDGE)
1086 {
1087 SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
1088 }
1089 }
1090
1091 /**
1092 * @brief Generates a Software interrupt on selected EXTI line.
1093 * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
1094 * (EXTI_LINE0..EXTI_LINE21),EXTI_LINE49,EXTI_LINE51,EXTI_LINE82,EXTI_LINE84,EXTI_LINE85 and EXTI_LINE86.
1095 * @retval None
1096 */
1097 void HAL_EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
1098 {
1099 /* Check the parameters */
1100 assert_param(IS_HAL_EXTI_CONFIG_LINE(EXTI_Line));
1101
1102 SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->SWIER1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
1103 }
1104
1105
1106 /**
1107 * @brief Clears the EXTI's line pending flags for Domain D1
1108 * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
1109 * (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
1110 * @retval None
1111 */
1112 void HAL_EXTI_D1_ClearFlag(uint32_t EXTI_Line)
1113 {
1114 /* Check the parameters */
1115 assert_param(IS_EXTI_D1_LINE(EXTI_Line));
1116 WRITE_REG(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->PR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
1117
1118 }
1119
1120 #if defined(DUAL_CORE)
1121 /**
1122 * @brief Clears the EXTI's line pending flags for Domain D2
1123 * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
1124 * (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
1125 * @retval None
1126 */
1127 void HAL_EXTI_D2_ClearFlag(uint32_t EXTI_Line)
1128 {
1129 /* Check the parameters */
1130 assert_param(IS_EXTI_D2_LINE(EXTI_Line));
1131 WRITE_REG(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->PR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
1132 }
1133
1134 #endif /*DUAL_CORE*/
1135 /**
1136 * @brief Configure the EXTI input event line for Domain D1
1137 * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
1138 * (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
1139 * @param EXTI_Mode: Specifies which EXTI line is used as interrupt or an event.
1140 * This parameter can be one or a combination of the following values :
1141 * @arg EXTI_MODE_IT : Interrupt Mode selected
1142 * @arg EXTI_MODE_EVT : Event Mode selected
1143 * @param EXTI_LineCmd controls (Enable/Disable) the EXTI line.
1144
1145 * @retval None
1146 */
1147 void HAL_EXTI_D1_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode, uint32_t EXTI_LineCmd )
1148 {
1149 /* Check the parameter */
1150 assert_param(IS_EXTI_D1_LINE(EXTI_Line));
1151 assert_param(IS_EXTI_MODE_LINE(EXTI_Mode));
1152
1153 if( (EXTI_Mode & EXTI_MODE_IT) == EXTI_MODE_IT)
1154 {
1155 if( EXTI_LineCmd == 0UL)
1156 {
1157 /* Clear EXTI line configuration */
1158 CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)),(uint32_t)(1UL << (EXTI_Line & 0x1FUL)) );
1159 }
1160 else
1161 {
1162 SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
1163 }
1164 }
1165
1166 if( (EXTI_Mode & EXTI_MODE_EVT) == EXTI_MODE_EVT)
1167 {
1168 if( EXTI_LineCmd == 0UL)
1169 {
1170 /* Clear EXTI line configuration */
1171 CLEAR_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI_D1->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
1172 }
1173 else
1174 {
1175 SET_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI_D1->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
1176 }
1177 }
1178 }
1179
1180 #if defined(DUAL_CORE)
1181 /**
1182 * @brief Configure the EXTI input event line for Domain D2
1183 * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
1184 * (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
1185 * @param EXTI_Mode: Specifies which EXTI line is used as interrupt or an event.
1186 * This parameter can be one or a combination of the following values :
1187 * @arg EXTI_MODE_IT : Interrupt Mode selected
1188 * @arg EXTI_MODE_EVT : Event Mode selected
1189 * @param EXTI_LineCmd controls (Enable/Disable) the EXTI line.
1190
1191 * @retval None
1192 */
1193 void HAL_EXTI_D2_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode, uint32_t EXTI_LineCmd )
1194 {
1195 /* Check the parameter */
1196 assert_param(IS_EXTI_D2_LINE(EXTI_Line));
1197 assert_param(IS_EXTI_MODE_LINE(EXTI_Mode));
1198
1199 if( (EXTI_Mode & EXTI_MODE_IT) == EXTI_MODE_IT)
1200 {
1201 if( EXTI_LineCmd == 0UL)
1202 {
1203 /* Clear EXTI line configuration */
1204 CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)),(uint32_t)(1UL << (EXTI_Line & 0x1FUL)) );
1205 }
1206 else
1207 {
1208 SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
1209 }
1210 }
1211
1212 if( (EXTI_Mode & EXTI_MODE_EVT) == EXTI_MODE_EVT)
1213 {
1214 if( EXTI_LineCmd == 0UL)
1215 {
1216 /* Clear EXTI line configuration */
1217 CLEAR_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI_D2->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
1218 }
1219 else
1220 {
1221 SET_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI_D2->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
1222 }
1223 }
1224 }
1225 #endif /*DUAL_CORE*/
1226
1227 /**
1228 * @brief Configure the EXTI input event line for Domain D3
1229 * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
1230 * (EXTI_LINE0...EXTI_LINE15),(EXTI_LINE19...EXTI_LINE21),EXTI_LINE25, EXTI_LINE34,
1231 * EXTI_LINE35,EXTI_LINE41,(EXTI_LINE48...EXTI_LINE53)
1232 * @param EXTI_LineCmd controls (Enable/Disable) the EXTI line.
1233 * @param EXTI_ClearSrc: Specifies the clear source of D3 pending event.
1234 * This parameter can be one of the following values :
1235 * @arg BDMA_CH6_CLEAR : BDMA ch6 event selected as D3 domain pendclear source
1236 * @arg BDMA_CH7_CLEAR : BDMA ch7 event selected as D3 domain pendclear source
1237 * @arg LPTIM4_OUT_CLEAR : LPTIM4 out selected as D3 domain pendclear source
1238 * @arg LPTIM5_OUT_CLEAR : LPTIM5 out selected as D3 domain pendclear source
1239 * @retval None
1240 */
1241 void HAL_EXTI_D3_EventInputConfig(uint32_t EXTI_Line, uint32_t EXTI_LineCmd , uint32_t EXTI_ClearSrc )
1242 {
1243 __IO uint32_t *pRegv;
1244
1245 /* Check the parameter */
1246 assert_param(IS_EXTI_D3_LINE(EXTI_Line));
1247 assert_param(IS_EXTI_D3_CLEAR(EXTI_ClearSrc));
1248
1249 if( EXTI_LineCmd == 0UL)
1250 {
1251 /* Clear EXTI line configuration */
1252 CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->D3PMR1)) + ((EXTI_Line >> 5 ) * 0x20UL)),(uint32_t)(1UL << (EXTI_Line & 0x1FUL)) );
1253 }
1254 else
1255 {
1256 SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->D3PMR1)) +((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
1257 }
1258
1259 if(((EXTI_Line>>4)%2UL) == 0UL)
1260 {
1261 pRegv = (__IO uint32_t *) (((uint32_t) &(EXTI->D3PCR1L)) + ((EXTI_Line >> 5 ) * 0x20UL));
1262 }
1263 else
1264 {
1265 pRegv = (__IO uint32_t *) (((uint32_t) &(EXTI->D3PCR1H)) + ((EXTI_Line >> 5 ) * 0x20UL));
1266 }
1267 MODIFY_REG(*pRegv, (uint32_t)(3UL << ((EXTI_Line*2UL) & 0x1FUL)), (uint32_t)(EXTI_ClearSrc << ((EXTI_Line*2UL) & 0x1FUL)));
1268
1269 }
1270
1271
1272
1273 /**
1274 * @}
1275 */
1276
1277 /**
1278 * @}
1279 */
1280
1281 /**
1282 * @}
1283 */
1284
1285 /**
1286 * @}
1287 */
1288
1289 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
INAV: Navigation-enabled flight control software