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Set blackbox file handler to NULL after closing file
[inav.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Src / stm32h7xx_hal_eth.c
bloba34d44e1cc9520032d42f46967b1a45157e768e1
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_hal_eth.c
4 * @author MCD Application Team
5 * @brief ETH HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Ethernet (ETH) peripheral:
8 * + Initialization and deinitialization functions
9 * + IO operation functions
10 * + Peripheral Control functions
11 * + Peripheral State and Errors functions
12 *
13 @verbatim
14 ==============================================================================
15 ##### How to use this driver #####
16 ==============================================================================
17 [..]
18 The ETH HAL driver can be used as follows:
19
20 (#)Declare a ETH_HandleTypeDef handle structure, for example:
21 ETH_HandleTypeDef heth;
22
23 (#)Fill parameters of Init structure in heth handle
24
25 (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
26
27 (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
28 (##) Enable the Ethernet interface clock using
29 (+++) __HAL_RCC_ETH1MAC_CLK_ENABLE()
30 (+++) __HAL_RCC_ETH1TX_CLK_ENABLE()
31 (+++) __HAL_RCC_ETH1RX_CLK_ENABLE()
32
33 (##) Initialize the related GPIO clocks
34 (##) Configure Ethernet pinout
35 (##) Configure Ethernet NVIC interrupt (in Interrupt mode)
36
37 (#) Ethernet data reception is asynchronous, so call the following API
38 to start the listening mode:
39 (##) HAL_ETH_Start():
40 This API starts the MAC and DMA transmission and reception process,
41 without enabling end of transfer interrupts, in this mode user
42 has to poll for data availability by calling HAL_ETH_IsRxDataAvailable()
43 (##) HAL_ETH_Start_IT():
44 This API starts the MAC and DMA transmission and reception process,
45 end of transfer interrupts are enabled in this mode,
46 HAL_ETH_RxCpltCallback() will be executed when an Ethernet packet is received
47
48 (#) When data is received (HAL_ETH_IsRxDataAvailable() returns 1 or Rx interrupt
49 occurred), user can call the following APIs to get received data:
50 (##) HAL_ETH_GetRxDataBuffer(): Get buffer address of received frame
51 (##) HAL_ETH_GetRxDataLength(): Get received frame length
52 (##) HAL_ETH_GetRxDataInfo(): Get received frame additional info,
53 please refer to ETH_RxPacketInfo typedef structure
54
55 (#) For transmission path, two APIs are available:
56 (##) HAL_ETH_Transmit(): Transmit an ETH frame in blocking mode
57 (##) HAL_ETH_Transmit_IT(): Transmit an ETH frame in interrupt mode,
58 HAL_ETH_TxCpltCallback() will be executed when end of transfer occur
59
60 (#) Communication with an external PHY device:
61 (##) HAL_ETH_ReadPHYRegister(): Read a register from an external PHY
62 (##) HAL_ETH_WritePHYRegister(): Write data to an external RHY register
63
64 (#) Configure the Ethernet MAC after ETH peripheral initialization
65 (##) HAL_ETH_GetMACConfig(): Get MAC actual configuration into ETH_MACConfigTypeDef
66 (##) HAL_ETH_SetMACConfig(): Set MAC configuration based on ETH_MACConfigTypeDef
67
68 (#) Configure the Ethernet DMA after ETH peripheral initialization
69 (##) HAL_ETH_GetDMAConfig(): Get DMA actual configuration into ETH_DMAConfigTypeDef
70 (##) HAL_ETH_SetDMAConfig(): Set DMA configuration based on ETH_DMAConfigTypeDef
71
72 -@- The PTP protocol offload APIs are not supported in this driver.
73
74 *** Callback registration ***
75 =============================================
76
77 The compilation define USE_HAL_ETH_REGISTER_CALLBACKS when set to 1
78 allows the user to configure dynamically the driver callbacks.
79 Use Function @ref HAL_ETH_RegisterCallback() to register an interrupt callback.
80
81 Function @ref HAL_ETH_RegisterCallback() allows to register following callbacks:
82 (+) TxCpltCallback : Tx Complete Callback.
83 (+) RxCpltCallback : Rx Complete Callback.
84 (+) DMAErrorCallback : DMA Error Callback.
85 (+) MACErrorCallback : MAC Error Callback.
86 (+) PMTCallback : Power Management Callback
87 (+) EEECallback : EEE Callback.
88 (+) WakeUpCallback : Wake UP Callback
89 (+) MspInitCallback : MspInit Callback.
90 (+) MspDeInitCallback: MspDeInit Callback.
91
92 This function takes as parameters the HAL peripheral handle, the Callback ID
93 and a pointer to the user callback function.
94
95 Use function @ref HAL_ETH_UnRegisterCallback() to reset a callback to the default
96 weak function.
97 @ref HAL_ETH_UnRegisterCallback takes as parameters the HAL peripheral handle,
98 and the Callback ID.
99 This function allows to reset following callbacks:
100 (+) TxCpltCallback : Tx Complete Callback.
101 (+) RxCpltCallback : Rx Complete Callback.
102 (+) DMAErrorCallback : DMA Error Callback.
103 (+) MACErrorCallback : MAC Error Callback.
104 (+) PMTCallback : Power Management Callback
105 (+) EEECallback : EEE Callback.
106 (+) WakeUpCallback : Wake UP Callback
107 (+) MspInitCallback : MspInit Callback.
108 (+) MspDeInitCallback: MspDeInit Callback.
109
110 By default, after the HAL_ETH_Init and when the state is HAL_ETH_STATE_RESET
111 all callbacks are set to the corresponding weak functions:
112 examples @ref HAL_ETH_TxCpltCallback(), @ref HAL_ETH_RxCpltCallback().
113 Exception done for MspInit and MspDeInit functions that are
114 reset to the legacy weak function in the HAL_ETH_Init/ @ref HAL_ETH_DeInit only when
115 these callbacks are null (not registered beforehand).
116 if not, MspInit or MspDeInit are not null, the HAL_ETH_Init/ @ref HAL_ETH_DeInit
117 keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
118
119 Callbacks can be registered/unregistered in HAL_ETH_STATE_READY state only.
120 Exception done MspInit/MspDeInit that can be registered/unregistered
121 in HAL_ETH_STATE_READY or HAL_ETH_STATE_RESET state,
122 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
123 In that case first register the MspInit/MspDeInit user callbacks
124 using @ref HAL_ETH_RegisterCallback() before calling @ref HAL_ETH_DeInit
125 or HAL_ETH_Init function.
126
127 When The compilation define USE_HAL_ETH_REGISTER_CALLBACKS is set to 0 or
128 not defined, the callback registration feature is not available and all callbacks
129 are set to the corresponding weak functions.
130
131 @endverbatim
132 ******************************************************************************
133 * @attention
134 *
135 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
136 * All rights reserved.</center></h2>
137 *
138 * This software component is licensed by ST under BSD 3-Clause license,
139 * the "License"; You may not use this file except in compliance with the
140 * License. You may obtain a copy of the License at:
141 * opensource.org/licenses/BSD-3-Clause
142 *
143 ******************************************************************************
144 */
145
146 /* Includes ------------------------------------------------------------------*/
147 #include "stm32h7xx_hal.h"
148
149 /** @addtogroup STM32H7xx_HAL_Driver
150 * @{
151 */
152 #ifdef HAL_ETH_MODULE_ENABLED
153
154 #if defined(ETH)
155
156 /** @defgroup ETH ETH
157 * @brief ETH HAL module driver
158 * @{
159 */
160
161 /* Private typedef -----------------------------------------------------------*/
162 /* Private define ------------------------------------------------------------*/
163 /** @addtogroup ETH_Private_Constants ETH Private Constants
164 * @{
165 */
166 #define ETH_MACCR_MASK ((uint32_t)0xFFFB7F7CU)
167 #define ETH_MACECR_MASK ((uint32_t)0x3F077FFFU)
168 #define ETH_MACPFR_MASK ((uint32_t)0x800007FFU)
169 #define ETH_MACWTR_MASK ((uint32_t)0x0000010FU)
170 #define ETH_MACTFCR_MASK ((uint32_t)0xFFFF00F2U)
171 #define ETH_MACRFCR_MASK ((uint32_t)0x00000003U)
172 #define ETH_MTLTQOMR_MASK ((uint32_t)0x00000072U)
173 #define ETH_MTLRQOMR_MASK ((uint32_t)0x0000007BU)
174
175 #define ETH_DMAMR_MASK ((uint32_t)0x00007802U)
176 #define ETH_DMASBMR_MASK ((uint32_t)0x0000D001U)
177 #define ETH_DMACCR_MASK ((uint32_t)0x00013FFFU)
178 #define ETH_DMACTCR_MASK ((uint32_t)0x003F1010U)
179 #define ETH_DMACRCR_MASK ((uint32_t)0x803F0000U)
180 #define ETH_MACPCSR_MASK (ETH_MACPCSR_PWRDWN | ETH_MACPCSR_RWKPKTEN | \
181 ETH_MACPCSR_MGKPKTEN | ETH_MACPCSR_GLBLUCAST | \
182 ETH_MACPCSR_RWKPFE)
183
184 /* Timeout values */
185 #define ETH_SWRESET_TIMEOUT ((uint32_t)500U)
186 #define ETH_MDIO_BUS_TIMEOUT ((uint32_t)1000U)
187
188 #define ETH_DMARXNDESCWBF_ERRORS_MASK ((uint32_t)(ETH_DMARXNDESCWBF_DE | ETH_DMARXNDESCWBF_RE | \
189 ETH_DMARXNDESCWBF_OE | ETH_DMARXNDESCWBF_RWT |\
190 ETH_DMARXNDESCWBF_GP | ETH_DMARXNDESCWBF_CE))
191
192 #define ETH_MAC_US_TICK ((uint32_t)1000000U)
193 /**
194 * @}
195 */
196
197 /* Private macros ------------------------------------------------------------*/
198 /** @defgroup ETH_Private_Macros ETH Private Macros
199 * @{
200 */
201 /* Helper macros for TX descriptor handling */
202 #define INCR_TX_DESC_INDEX(inx, offset) do {\
203 (inx) += (offset);\
204 if ((inx) >= (uint32_t)ETH_TX_DESC_CNT){\
205 (inx) = ((inx) - (uint32_t)ETH_TX_DESC_CNT);}\
206 } while (0)
207
208 /* Helper macros for RX descriptor handling */
209 #define INCR_RX_DESC_INDEX(inx, offset) do {\
210 (inx) += (offset);\
211 if ((inx) >= (uint32_t)ETH_RX_DESC_CNT){\
212 (inx) = ((inx) - (uint32_t)ETH_RX_DESC_CNT);}\
213 } while (0)
214 /**
215 * @}
216 */
217 /* Private function prototypes -----------------------------------------------*/
218 /** @defgroup ETH_Private_Functions ETH Private Functions
219 * @{
220 */
221 static void ETH_MAC_MDIO_ClkConfig(ETH_HandleTypeDef *heth);
222 static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
223 static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
224 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth);
225 static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth);
226 static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth);
227 static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t ItMode);
228
229 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
230 static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth);
231 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
232 /**
233 * @}
234 */
235
236 /* Exported functions ---------------------------------------------------------*/
237 /** @defgroup ETH_Exported_Functions ETH Exported Functions
238 * @{
239 */
240
241 /** @defgroup ETH_Exported_Functions_Group1 Initialization and deinitialization functions
242 * @brief Initialization and Configuration functions
243 *
244 @verbatim
245 ===============================================================================
246 ##### Initialization and Configuration functions #####
247 ===============================================================================
248 [..] This subsection provides a set of functions allowing to initialize and
249 deinitialize the ETH peripheral:
250
251 (+) User must Implement HAL_ETH_MspInit() function in which he configures
252 all related peripherals resources (CLOCK, GPIO and NVIC ).
253
254 (+) Call the function HAL_ETH_Init() to configure the selected device with
255 the selected configuration:
256 (++) MAC address
257 (++) Media interface (MII or RMII)
258 (++) Rx DMA Descriptors Tab
259 (++) Tx DMA Descriptors Tab
260 (++) Length of Rx Buffers
261
262 (+) Call the function HAL_ETH_DescAssignMemory() to assign data buffers
263 for each Rx DMA Descriptor
264
265 (+) Call the function HAL_ETH_DeInit() to restore the default configuration
266 of the selected ETH peripheral.
267
268 @endverbatim
269 * @{
270 */
271
272 /**
273 * @brief Initialize the Ethernet peripheral registers.
274 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
275 * the configuration information for ETHERNET module
276 * @retval HAL status
277 */
278 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
279 {
280 uint32_t tickstart;
281
282 if(heth == NULL)
283 {
284 return HAL_ERROR;
285 }
286
287 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
288
289 if(heth->gState == HAL_ETH_STATE_RESET)
290 {
291 /* Allocate lock resource and initialize it */
292 heth->Lock = HAL_UNLOCKED;
293
294 ETH_InitCallbacksToDefault(heth);
295
296 if(heth->MspInitCallback == NULL)
297 {
298 heth->MspInitCallback = HAL_ETH_MspInit;
299 }
300
301 /* Init the low level hardware */
302 heth->MspInitCallback(heth);
303 }
304
305 #else
306
307 /* Check the ETH peripheral state */
308 if(heth->gState == HAL_ETH_STATE_RESET)
309 {
310 /* Init the low level hardware : GPIO, CLOCK, NVIC. */
311 HAL_ETH_MspInit(heth);
312 }
313 #endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */
314
315 heth->gState = HAL_ETH_STATE_BUSY;
316
317 __HAL_RCC_SYSCFG_CLK_ENABLE();
318
319 if(heth->Init.MediaInterface == HAL_ETH_MII_MODE)
320 {
321 HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_MII);
322 }
323 else
324 {
325 HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_RMII);
326 }
327
328 /* Ethernet Software reset */
329 /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
330 /* After reset all the registers holds their respective reset values */
331 SET_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR);
332
333 /* Get tick */
334 tickstart = HAL_GetTick();
335
336 /* Wait for software reset */
337 while (READ_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR) > 0U)
338 {
339 if(((HAL_GetTick() - tickstart ) > ETH_SWRESET_TIMEOUT))
340 {
341 /* Set Error Code */
342 heth->ErrorCode = HAL_ETH_ERROR_TIMEOUT;
343 /* Set State as Error */
344 heth->gState = HAL_ETH_STATE_ERROR;
345 /* Return Error */
346 return HAL_ERROR;
347 }
348 }
349
350 /*------------------ MDIO CSR Clock Range Configuration --------------------*/
351 ETH_MAC_MDIO_ClkConfig(heth);
352
353 /*------------------ MAC LPI 1US Tic Counter Configuration --------------------*/
354 WRITE_REG(heth->Instance->MAC1USTCR, (((uint32_t)HAL_RCC_GetHCLKFreq() / ETH_MAC_US_TICK) - 1U));
355
356 /*------------------ MAC, MTL and DMA default Configuration ----------------*/
357 ETH_MACDMAConfig(heth);
358
359 /* SET DSL to 64 bit */
360 MODIFY_REG(heth->Instance->DMACCR, ETH_DMACCR_DSL, ETH_DMACCR_DSL_64BIT);
361
362 /* Set Receive Buffers Length (must be a multiple of 4) */
363 if ((heth->Init.RxBuffLen % 0x4U) != 0x0U)
364 {
365 /* Set Error Code */
366 heth->ErrorCode = HAL_ETH_ERROR_PARAM;
367 /* Set State as Error */
368 heth->gState = HAL_ETH_STATE_ERROR;
369 /* Return Error */
370 return HAL_ERROR;
371 }
372 else
373 {
374 MODIFY_REG(heth->Instance->DMACRCR, ETH_DMACRCR_RBSZ, ((heth->Init.RxBuffLen) << 1));
375 }
376
377 /*------------------ DMA Tx Descriptors Configuration ----------------------*/
378 ETH_DMATxDescListInit(heth);
379
380 /*------------------ DMA Rx Descriptors Configuration ----------------------*/
381 ETH_DMARxDescListInit(heth);
382
383 /*--------------------- ETHERNET MAC Address Configuration ------------------*/
384 /* Set MAC addr bits 32 to 47 */
385 heth->Instance->MACA0HR = (((uint32_t)(heth->Init.MACAddr[5]) << 8) | (uint32_t)heth->Init.MACAddr[4]);
386 /* Set MAC addr bits 0 to 31 */
387 heth->Instance->MACA0LR = (((uint32_t)(heth->Init.MACAddr[3]) << 24) | ((uint32_t)(heth->Init.MACAddr[2]) << 16) |
388 ((uint32_t)(heth->Init.MACAddr[1]) << 8) | (uint32_t)heth->Init.MACAddr[0]);
389
390 heth->ErrorCode = HAL_ETH_ERROR_NONE;
391 heth->gState = HAL_ETH_STATE_READY;
392 heth->RxState = HAL_ETH_STATE_READY;
393
394 return HAL_OK;
395 }
396
397 /**
398 * @brief DeInitializes the ETH peripheral.
399 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
400 * the configuration information for ETHERNET module
401 * @retval HAL status
402 */
403 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
404 {
405 /* Set the ETH peripheral state to BUSY */
406 heth->gState = HAL_ETH_STATE_BUSY;
407
408 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
409
410 if(heth->MspDeInitCallback == NULL)
411 {
412 heth->MspDeInitCallback = HAL_ETH_MspDeInit;
413 }
414 /* DeInit the low level hardware */
415 heth->MspDeInitCallback(heth);
416 #else
417
418 /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
419 HAL_ETH_MspDeInit(heth);
420
421 #endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */
422
423 /* Set ETH HAL state to Disabled */
424 heth->gState= HAL_ETH_STATE_RESET;
425
426 /* Return function status */
427 return HAL_OK;
428 }
429
430 /**
431 * @brief Initializes the ETH MSP.
432 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
433 * the configuration information for ETHERNET module
434 * @retval None
435 */
436 __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
437 {
438 /* Prevent unused argument(s) compilation warning */
439 UNUSED(heth);
440 /* NOTE : This function Should not be modified, when the callback is needed,
441 the HAL_ETH_MspInit could be implemented in the user file
442 */
443 }
444
445 /**
446 * @brief DeInitializes ETH MSP.
447 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
448 * the configuration information for ETHERNET module
449 * @retval None
450 */
451 __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
452 {
453 /* Prevent unused argument(s) compilation warning */
454 UNUSED(heth);
455 /* NOTE : This function Should not be modified, when the callback is needed,
456 the HAL_ETH_MspDeInit could be implemented in the user file
457 */
458 }
459
460 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
461 /**
462 * @brief Register a User ETH Callback
463 * To be used instead of the weak predefined callback
464 * @param heth eth handle
465 * @param CallbackID ID of the callback to be registered
466 * This parameter can be one of the following values:
467 * @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID
468 * @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID
469 * @arg @ref HAL_ETH_DMA_ERROR_CB_ID DMA Error Callback ID
470 * @arg @ref HAL_ETH_MAC_ERROR_CB_ID MAC Error Callback ID
471 * @arg @ref HAL_ETH_PMT_CB_ID Power Management Callback ID
472 * @arg @ref HAL_ETH_EEE_CB_ID EEE Callback ID
473 * @arg @ref HAL_ETH_WAKEUP_CB_ID Wake UP Callback ID
474 * @arg @ref HAL_ETH_MSPINIT_CB_ID MspInit callback ID
475 * @arg @ref HAL_ETH_MSPDEINIT_CB_ID MspDeInit callback ID
476 * @param pCallback pointer to the Callback function
477 * @retval status
478 */
479 HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback)
480 {
481 HAL_StatusTypeDef status = HAL_OK;
482
483 if(pCallback == NULL)
484 {
485 /* Update the error code */
486 heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
487
488 return HAL_ERROR;
489 }
490 /* Process locked */
491 __HAL_LOCK(heth);
492
493 if(heth->gState == HAL_ETH_STATE_READY)
494 {
495 switch (CallbackID)
496 {
497 case HAL_ETH_TX_COMPLETE_CB_ID :
498 heth->TxCpltCallback = pCallback;
499 break;
500
501 case HAL_ETH_RX_COMPLETE_CB_ID :
502 heth->RxCpltCallback = pCallback;
503 break;
504
505 case HAL_ETH_DMA_ERROR_CB_ID :
506 heth->DMAErrorCallback = pCallback;
507 break;
508
509 case HAL_ETH_MAC_ERROR_CB_ID :
510 heth->MACErrorCallback = pCallback;
511 break;
512
513 case HAL_ETH_PMT_CB_ID :
514 heth->PMTCallback = pCallback;
515 break;
516
517 case HAL_ETH_EEE_CB_ID :
518 heth->EEECallback = pCallback;
519 break;
520
521 case HAL_ETH_WAKEUP_CB_ID :
522 heth->WakeUpCallback = pCallback;
523 break;
524
525 case HAL_ETH_MSPINIT_CB_ID :
526 heth->MspInitCallback = pCallback;
527 break;
528
529 case HAL_ETH_MSPDEINIT_CB_ID :
530 heth->MspDeInitCallback = pCallback;
531 break;
532
533 default :
534 /* Update the error code */
535 heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
536 /* Return error status */
537 status = HAL_ERROR;
538 break;
539 }
540 }
541 else if(heth->gState == HAL_ETH_STATE_RESET)
542 {
543 switch (CallbackID)
544 {
545 case HAL_ETH_MSPINIT_CB_ID :
546 heth->MspInitCallback = pCallback;
547 break;
548
549 case HAL_ETH_MSPDEINIT_CB_ID :
550 heth->MspDeInitCallback = pCallback;
551 break;
552
553 default :
554 /* Update the error code */
555 heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
556 /* Return error status */
557 status = HAL_ERROR;
558 break;
559 }
560 }
561 else
562 {
563 /* Update the error code */
564 heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
565 /* Return error status */
566 status = HAL_ERROR;
567 }
568
569 /* Release Lock */
570 __HAL_UNLOCK(heth);
571
572 return status;
573 }
574
575 /**
576 * @brief Unregister an ETH Callback
577 * ETH callabck is redirected to the weak predefined callback
578 * @param heth eth handle
579 * @param CallbackID ID of the callback to be unregistered
580 * This parameter can be one of the following values:
581 * @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID
582 * @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID
583 * @arg @ref HAL_ETH_DMA_ERROR_CB_ID DMA Error Callback ID
584 * @arg @ref HAL_ETH_MAC_ERROR_CB_ID MAC Error Callback ID
585 * @arg @ref HAL_ETH_PMT_CB_ID Power Management Callback ID
586 * @arg @ref HAL_ETH_EEE_CB_ID EEE Callback ID
587 * @arg @ref HAL_ETH_WAKEUP_CB_ID Wake UP Callback ID
588 * @arg @ref HAL_ETH_MSPINIT_CB_ID MspInit callback ID
589 * @arg @ref HAL_ETH_MSPDEINIT_CB_ID MspDeInit callback ID
590 * @retval status
591 */
592 HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID)
593 {
594 HAL_StatusTypeDef status = HAL_OK;
595
596 /* Process locked */
597 __HAL_LOCK(heth);
598
599 if(heth->gState == HAL_ETH_STATE_READY)
600 {
601 switch (CallbackID)
602 {
603 case HAL_ETH_TX_COMPLETE_CB_ID :
604 heth->TxCpltCallback = HAL_ETH_TxCpltCallback;
605 break;
606
607 case HAL_ETH_RX_COMPLETE_CB_ID :
608 heth->RxCpltCallback = HAL_ETH_RxCpltCallback;
609 break;
610
611 case HAL_ETH_DMA_ERROR_CB_ID :
612 heth->DMAErrorCallback = HAL_ETH_DMAErrorCallback;
613 break;
614
615 case HAL_ETH_MAC_ERROR_CB_ID :
616 heth->MACErrorCallback = HAL_ETH_MACErrorCallback;
617 break;
618
619 case HAL_ETH_PMT_CB_ID :
620 heth->PMTCallback = HAL_ETH_PMTCallback;
621 break;
622
623 case HAL_ETH_EEE_CB_ID :
624 heth->EEECallback = HAL_ETH_EEECallback;
625 break;
626
627 case HAL_ETH_WAKEUP_CB_ID :
628 heth->WakeUpCallback = HAL_ETH_WakeUpCallback;
629 break;
630
631 case HAL_ETH_MSPINIT_CB_ID :
632 heth->MspInitCallback = HAL_ETH_MspInit;
633 break;
634
635 case HAL_ETH_MSPDEINIT_CB_ID :
636 heth->MspDeInitCallback = HAL_ETH_MspDeInit;
637 break;
638
639 default :
640 /* Update the error code */
641 heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
642 /* Return error status */
643 status = HAL_ERROR;
644 break;
645 }
646 }
647 else if(heth->gState == HAL_ETH_STATE_RESET)
648 {
649 switch (CallbackID)
650 {
651 case HAL_ETH_MSPINIT_CB_ID :
652 heth->MspInitCallback = HAL_ETH_MspInit;
653 break;
654
655 case HAL_ETH_MSPDEINIT_CB_ID :
656 heth->MspDeInitCallback = HAL_ETH_MspDeInit;
657 break;
658
659 default :
660 /* Update the error code */
661 heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
662 /* Return error status */
663 status = HAL_ERROR;
664 break;
665 }
666 }
667 else
668 {
669 /* Update the error code */
670 heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
671 /* Return error status */
672 status = HAL_ERROR;
673 }
674
675 /* Release Lock */
676 __HAL_UNLOCK(heth);
677
678 return status;
679 }
680 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
681
682 /**
683 * @brief Assign memory buffers to a DMA Rx descriptor
684 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
685 * the configuration information for ETHERNET module
686 * @param Index : index of the DMA Rx descriptor
687 * this parameter can be a value from 0x0 to (ETH_RX_DESC_CNT -1)
688 * @param pBuffer1: address of buffer 1
689 * @param pBuffer2: address of buffer 2 if available
690 * @retval HAL status
691 */
692 HAL_StatusTypeDef HAL_ETH_DescAssignMemory(ETH_HandleTypeDef *heth, uint32_t Index, uint8_t *pBuffer1, uint8_t *pBuffer2)
693 {
694 ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[Index];
695
696 if((pBuffer1 == NULL) || (Index >= (uint32_t)ETH_RX_DESC_CNT))
697 {
698 /* Set Error Code */
699 heth->ErrorCode = HAL_ETH_ERROR_PARAM;
700 /* Return Error */
701 return HAL_ERROR;
702 }
703
704 /* write buffer address to RDES0 */
705 WRITE_REG(dmarxdesc->DESC0, (uint32_t)pBuffer1);
706 /* store buffer address */
707 WRITE_REG(dmarxdesc->BackupAddr0, (uint32_t)pBuffer1);
708 /* set buffer address valid bit to RDES3 */
709 SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF1V);
710
711 if(pBuffer2 != NULL)
712 {
713 /* write buffer 2 address to RDES1 */
714 WRITE_REG(dmarxdesc->DESC2, (uint32_t)pBuffer2);
715 /* store buffer 2 address */
716 WRITE_REG(dmarxdesc->BackupAddr1, (uint32_t)pBuffer2);
717 /* set buffer 2 address valid bit to RDES3 */
718 SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF2V);
719 }
720 /* set OWN bit to RDES3 */
721 SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN);
722
723 return HAL_OK;
724 }
725
726 /**
727 * @}
728 */
729
730 /** @defgroup ETH_Exported_Functions_Group2 IO operation functions
731 * @brief ETH Transmit and Receive functions
732 *
733 @verbatim
734 ==============================================================================
735 ##### IO operation functions #####
736 ==============================================================================
737 [..]
738 This subsection provides a set of functions allowing to manage the ETH
739 data transfer.
740
741 @endverbatim
742 * @{
743 */
744
745 /**
746 * @brief Enables Ethernet MAC and DMA reception and transmission
747 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
748 * the configuration information for ETHERNET module
749 * @retval HAL status
750 */
751 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
752 {
753 if(heth->gState == HAL_ETH_STATE_READY)
754 {
755 heth->gState = HAL_ETH_STATE_BUSY;
756
757 /* Enable the MAC transmission */
758 SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
759
760 /* Enable the MAC reception */
761 SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
762
763 /* Set the Flush Transmit FIFO bit */
764 SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
765
766 /* Enable the DMA transmission */
767 SET_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
768
769 /* Enable the DMA reception */
770 SET_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR);
771
772 /* Clear Tx and Rx process stopped flags */
773 heth->Instance->DMACSR |= (ETH_DMACSR_TPS | ETH_DMACSR_RPS);
774
775 heth->gState = HAL_ETH_STATE_READY;
776 heth->RxState = HAL_ETH_STATE_BUSY_RX;
777
778 return HAL_OK;
779 }
780 else
781 {
782 return HAL_ERROR;
783 }
784 }
785
786 /**
787 * @brief Enables Ethernet MAC and DMA reception/transmission in Interrupt mode
788 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
789 * the configuration information for ETHERNET module
790 * @retval HAL status
791 */
792 HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth)
793 {
794 uint32_t descindex = 0, counter;
795 ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descindex];
796
797 if(heth->gState == HAL_ETH_STATE_READY)
798 {
799 heth->gState = HAL_ETH_STATE_BUSY;
800
801 /* Set IOC bit to all Rx descriptors */
802 for(counter= 0; counter < (uint32_t)ETH_RX_DESC_CNT; counter++)
803 {
804 SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
805 INCR_RX_DESC_INDEX(descindex, 1U);
806 dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descindex];
807 }
808
809 /* save IT mode to ETH Handle */
810 heth->RxDescList.ItMode = 1U;
811
812 /* Enable the MAC transmission */
813 SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
814
815 /* Enable the MAC reception */
816 SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
817
818 /* Set the Flush Transmit FIFO bit */
819 SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
820
821 /* Enable the DMA transmission */
822 SET_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
823
824 /* Enable the DMA reception */
825 SET_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR);
826
827 /* Clear Tx and Rx process stopped flags */
828 heth->Instance->DMACSR |= (ETH_DMACSR_TPS | ETH_DMACSR_RPS);
829
830 heth->gState = HAL_ETH_STATE_READY;
831 heth->RxState = HAL_ETH_STATE_BUSY_RX;
832
833 /* Enable ETH DMA interrupts:
834 - Tx complete interrupt
835 - Rx complete interrupt
836 - Fatal bus interrupt
837 */
838 __HAL_ETH_DMA_ENABLE_IT(heth, (ETH_DMACIER_NIE | ETH_DMACIER_RIE | ETH_DMACIER_TIE |
839 ETH_DMACIER_FBEE | ETH_DMACIER_AIE));
840
841 return HAL_OK;
842 }
843 else
844 {
845 return HAL_ERROR;
846 }
847 }
848
849 /**
850 * @brief Stop Ethernet MAC and DMA reception/transmission
851 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
852 * the configuration information for ETHERNET module
853 * @retval HAL status
854 */
855 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
856 {
857 if(heth->gState != HAL_ETH_STATE_RESET)
858 {
859 /* Set the ETH peripheral state to BUSY */
860 heth->gState = HAL_ETH_STATE_BUSY;
861
862 /* Disable the DMA transmission */
863 CLEAR_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
864
865 /* Disable the DMA reception */
866 CLEAR_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR);
867
868 /* Disable the MAC reception */
869 CLEAR_BIT( heth->Instance->MACCR, ETH_MACCR_RE);
870
871 /* Set the Flush Transmit FIFO bit */
872 SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
873
874 /* Disable the MAC transmission */
875 CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
876
877 heth->gState = HAL_ETH_STATE_READY;
878 heth->RxState = HAL_ETH_STATE_READY;
879
880 /* Return function status */
881 return HAL_OK;
882 }
883 else
884 {
885 return HAL_ERROR;
886 }
887 }
888
889 /**
890 * @brief Stop Ethernet MAC and DMA reception/transmission in Interrupt mode
891 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
892 * the configuration information for ETHERNET module
893 * @retval HAL status
894 */
895 HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth)
896 {
897 ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[0];
898 uint32_t index;
899
900 if(heth->gState != HAL_ETH_STATE_RESET)
901 {
902 /* Set the ETH peripheral state to BUSY */
903 heth->gState = HAL_ETH_STATE_BUSY;
904
905 /* Disable intrrupts:
906 - Tx complete interrupt
907 - Rx complete interrupt */
908 __HAL_ETH_DMA_DISABLE_IT(heth, (ETH_DMA_NORMAL_IT | ETH_DMA_RX_IT | ETH_DMA_TX_IT));
909
910 /* Disable the DMA transmission */
911 CLEAR_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
912
913 /* Disable the DMA reception */
914 CLEAR_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR);
915
916 /* Disable the MAC reception */
917 CLEAR_BIT( heth->Instance->MACCR, ETH_MACCR_RE);
918
919 /* Set the Flush Transmit FIFO bit */
920 SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
921
922 /* Disable the MAC transmission */
923 CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
924
925 /* Clear IOC bit to all Rx descriptors */
926 for(index = 0; index < (uint32_t)ETH_RX_DESC_CNT; index++)
927 {
928 CLEAR_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
929 }
930
931 heth->RxDescList.ItMode = 0U;
932
933 heth->gState = HAL_ETH_STATE_READY;
934 heth->RxState = HAL_ETH_STATE_READY;
935
936 /* Return function status */
937 return HAL_OK;
938 }
939 else
940 {
941 return HAL_ERROR;
942 }
943 }
944
945 /**
946 * @brief Sends an Ethernet Packet in polling mode.
947 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
948 * the configuration information for ETHERNET module
949 * @param pTxConfig: Hold the configuration of packet to be transmitted
950 * @param Timeout: timeout value
951 * @retval HAL status
952 */
953 HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout)
954 {
955 uint32_t tickstart;
956 const ETH_DMADescTypeDef *dmatxdesc;
957
958 if(pTxConfig == NULL)
959 {
960 heth->ErrorCode |= HAL_ETH_ERROR_PARAM;
961 return HAL_ERROR;
962 }
963
964 if(heth->gState == HAL_ETH_STATE_READY)
965 {
966 /* Config DMA Tx descriptor by Tx Packet info */
967 if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 0) != HAL_ETH_ERROR_NONE)
968 {
969 /* Set the ETH error code */
970 heth->ErrorCode |= HAL_ETH_ERROR_BUSY;
971 return HAL_ERROR;
972 }
973
974 dmatxdesc = (ETH_DMADescTypeDef *)(&heth->TxDescList)->TxDesc[heth->TxDescList.CurTxDesc];
975
976 /* Incr current tx desc index */
977 INCR_TX_DESC_INDEX(heth->TxDescList.CurTxDesc, 1U);
978
979 /* Start transmission */
980 /* issue a poll command to Tx DMA by writing address of next immediate free descriptor */
981 WRITE_REG(heth->Instance->DMACTDTPR, (uint32_t)(heth->TxDescList.TxDesc[heth->TxDescList.CurTxDesc]));
982
983 tickstart = HAL_GetTick();
984
985 /* Wait for data to be transmitted or timeout occured */
986 while((dmatxdesc->DESC3 & ETH_DMATXNDESCWBF_OWN) != (uint32_t)RESET)
987 {
988 if((heth->Instance->DMACSR & ETH_DMACSR_FBE) != (uint32_t)RESET)
989 {
990 heth->ErrorCode |= HAL_ETH_ERROR_DMA;
991 heth->DMAErrorCode = heth->Instance->DMACSR;
992 /* Set ETH HAL State to Ready */
993 heth->gState = HAL_ETH_STATE_ERROR;
994 /* Return function status */
995 return HAL_ERROR;
996 }
997
998 /* Check for the Timeout */
999 if(Timeout != HAL_MAX_DELAY)
1000 {
1001 if(((HAL_GetTick() - tickstart ) > Timeout) || (Timeout == 0U))
1002 {
1003 heth->ErrorCode |= HAL_ETH_ERROR_TIMEOUT;
1004 heth->gState = HAL_ETH_STATE_READY;
1005 return HAL_ERROR;
1006 }
1007 }
1008 }
1009
1010 /* Set ETH HAL State to Ready */
1011 heth->gState = HAL_ETH_STATE_READY;
1012
1013 /* Return function status */
1014 return HAL_OK;
1015 }
1016 else
1017 {
1018 return HAL_ERROR;
1019 }
1020 }
1021
1022 /**
1023 * @brief Sends an Ethernet Packet in interrupt mode.
1024 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1025 * the configuration information for ETHERNET module
1026 * @param pTxConfig: Hold the configuration of packet to be transmitted
1027 * @retval HAL status
1028 */
1029 HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig)
1030 {
1031 if(pTxConfig == NULL)
1032 {
1033 return HAL_ERROR;
1034 }
1035
1036 if(heth->gState == HAL_ETH_STATE_READY)
1037 {
1038 /* Config DMA Tx descriptor by Tx Packet info */
1039 if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 1) != HAL_ETH_ERROR_NONE)
1040 {
1041 heth->ErrorCode = HAL_ETH_ERROR_BUSY;
1042 return HAL_ERROR;
1043 }
1044
1045 /* Incr current tx desc index */
1046 INCR_TX_DESC_INDEX(heth->TxDescList.CurTxDesc, 1U);
1047
1048 /* Start transmission */
1049 /* issue a poll command to Tx DMA by writing address of next immediate free descriptor */
1050 WRITE_REG(heth->Instance->DMACTDTPR, (uint32_t)(heth->TxDescList.TxDesc[heth->TxDescList.CurTxDesc]));
1051
1052 return HAL_OK;
1053
1054 }
1055 else
1056 {
1057 return HAL_ERROR;
1058 }
1059 }
1060
1061 /**
1062 * @brief Checks for received Packets.
1063 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1064 * the configuration information for ETHERNET module
1065 * @retval 1: A Packet is received
1066 * 0: no Packet received
1067 */
1068 uint8_t HAL_ETH_IsRxDataAvailable(ETH_HandleTypeDef *heth)
1069 {
1070 ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
1071 uint32_t descidx = dmarxdesclist->CurRxDesc;
1072 ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
1073 uint32_t descscancnt = 0;
1074 uint32_t appdesccnt = 0, firstappdescidx = 0;
1075
1076 if(dmarxdesclist->AppDescNbr != 0U)
1077 {
1078 /* data already received by not yet processed*/
1079 return 0;
1080 }
1081
1082 /* Check if descriptor is not owned by DMA */
1083 while((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_OWN) == (uint32_t)RESET) && (descscancnt < (uint32_t)ETH_RX_DESC_CNT))
1084 {
1085 descscancnt++;
1086
1087 /* Check if last descriptor */
1088 if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_LD) != (uint32_t)RESET)
1089 {
1090 /* Increment the number of descriptors to be passed to the application */
1091 appdesccnt += 1U;
1092
1093 if(appdesccnt == 1U)
1094 {
1095 WRITE_REG(firstappdescidx, descidx);
1096 }
1097
1098 /* Increment current rx descriptor index */
1099 INCR_RX_DESC_INDEX(descidx, 1U);
1100
1101 /* Check for Context descriptor */
1102 /* Get current descriptor address */
1103 dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
1104
1105 if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_OWN) == (uint32_t)RESET)
1106 {
1107 if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_CTXT) != (uint32_t)RESET)
1108 {
1109 /* Increment the number of descriptors to be passed to the application */
1110 dmarxdesclist->AppContextDesc = 1;
1111 /* Increment current rx descriptor index */
1112 INCR_RX_DESC_INDEX(descidx, 1U);
1113 }
1114 }
1115 /* Fill information to Rx descriptors list */
1116 dmarxdesclist->CurRxDesc = descidx;
1117 dmarxdesclist->FirstAppDesc = firstappdescidx;
1118 dmarxdesclist->AppDescNbr = appdesccnt;
1119
1120 /* Return function status */
1121 return 1;
1122 }
1123 /* Check if first descriptor */
1124 else if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_FD) != (uint32_t)RESET)
1125 {
1126 WRITE_REG(firstappdescidx, descidx);
1127 /* Increment the number of descriptors to be passed to the application */
1128 appdesccnt = 1U;
1129
1130 /* Increment current rx descriptor index */
1131 INCR_RX_DESC_INDEX(descidx, 1U);
1132 /* Get current descriptor address */
1133 dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
1134 }
1135 /* It should be an intermediate descriptor */
1136 else
1137 {
1138 /* Increment the number of descriptors to be passed to the application */
1139 appdesccnt += 1U;
1140
1141 /* Increment current rx descriptor index */
1142 INCR_RX_DESC_INDEX(descidx, 1U);
1143 /* Get current descriptor address */
1144 dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
1145 }
1146 }
1147
1148 /* Build Descriptors if an incomplete Packet is received */
1149 if(appdesccnt > 0U)
1150 {
1151 descidx = firstappdescidx;
1152 dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
1153
1154 for(descscancnt = 0; descscancnt < appdesccnt; descscancnt++)
1155 {
1156 WRITE_REG(dmarxdesc->DESC0, dmarxdesc->BackupAddr0);
1157 WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF1V);
1158
1159 if (READ_REG(dmarxdesc->BackupAddr1) != ((uint32_t)RESET))
1160 {
1161 WRITE_REG(dmarxdesc->DESC2, dmarxdesc->BackupAddr1);
1162 SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF2V);
1163 }
1164
1165 SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN);
1166
1167 if(dmarxdesclist->ItMode != ((uint32_t)RESET))
1168 {
1169 SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
1170 }
1171
1172 /* Increment rx descriptor index */
1173 INCR_RX_DESC_INDEX(descidx, 1U);
1174 /* Get descriptor address */
1175 dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
1176 }
1177 }
1178
1179 /* Fill information to Rx descriptors list: No received Packet */
1180 dmarxdesclist->AppDescNbr = 0U;
1181
1182 return 0;
1183 }
1184
1185 /**
1186 * @brief This function gets the buffer address of last received Packet.
1187 * @note Please insure to allocate the RxBuffer structure before calling this function
1188 * how to use example:
1189 * HAL_ETH_GetRxDataLength(heth, &Length);
1190 * BuffersNbr = (Length / heth->Init.RxBuffLen) + 1;
1191 * RxBuffer = (ETH_BufferTypeDef *)malloc(BuffersNbr * sizeof(ETH_BufferTypeDef));
1192 * HAL_ETH_GetRxDataBuffer(heth, RxBuffer);
1193 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1194 * the configuration information for ETHERNET module
1195 * @param RxBuffer: Pointer to a ETH_BufferTypeDef structure
1196 * @retval HAL status
1197 */
1198 HAL_StatusTypeDef HAL_ETH_GetRxDataBuffer(ETH_HandleTypeDef *heth, ETH_BufferTypeDef *RxBuffer)
1199 {
1200 ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
1201 uint32_t descidx = dmarxdesclist->FirstAppDesc;
1202 uint32_t index, accumulatedlen = 0, lastdesclen;
1203 __IO const ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
1204 ETH_BufferTypeDef *rxbuff = RxBuffer;
1205
1206 if(rxbuff == NULL)
1207 {
1208 heth->ErrorCode = HAL_ETH_ERROR_PARAM;
1209 return HAL_ERROR;
1210 }
1211
1212 if(dmarxdesclist->AppDescNbr == 0U)
1213 {
1214 if(HAL_ETH_IsRxDataAvailable(heth) == 0U)
1215 {
1216 /* No data to be transferred to the application */
1217 return HAL_ERROR;
1218 }
1219 else
1220 {
1221 descidx = dmarxdesclist->FirstAppDesc;
1222 dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
1223 }
1224 }
1225
1226 /* Get intermediate descriptors buffers: in case of the Packet is splitted into multi descriptors */
1227 for(index = 0; index < (dmarxdesclist->AppDescNbr - 1U); index++)
1228 {
1229 /* Get Address and length of the first buffer address */
1230 rxbuff->buffer = (uint8_t *) dmarxdesc->BackupAddr0;
1231 rxbuff->len = heth->Init.RxBuffLen;
1232
1233 /* Check if the second buffer address of this descriptor is valid */
1234 if(dmarxdesc->BackupAddr1 != 0U)
1235 {
1236 /* Point to next buffer */
1237 rxbuff = (struct __ETH_BufferTypeDef *)rxbuff->next;
1238 /* Get Address and length of the second buffer address */
1239 rxbuff->buffer = (uint8_t *) dmarxdesc->BackupAddr1;
1240 rxbuff->len = heth->Init.RxBuffLen;
1241 }
1242 else
1243 {
1244 /* Nothing to do here */
1245 }
1246
1247 /* get total length until this descriptor */
1248 accumulatedlen = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL);
1249
1250 /* Increment to next descriptor */
1251 INCR_RX_DESC_INDEX(descidx, 1U);
1252 dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
1253
1254 /* Point to next buffer */
1255 rxbuff = (struct __ETH_BufferTypeDef *)rxbuff->next;
1256 }
1257
1258 /* last descriptor data length */
1259 lastdesclen = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL) - accumulatedlen;
1260
1261 /* Get Address of the first buffer address */
1262 rxbuff->buffer = (uint8_t *) dmarxdesc->BackupAddr0;
1263
1264 /* data is in only one buffer */
1265 if(lastdesclen <= heth->Init.RxBuffLen)
1266 {
1267 rxbuff->len = lastdesclen;
1268 }
1269 /* data is in two buffers */
1270 else if(dmarxdesc->BackupAddr1 != 0U)
1271 {
1272 /* Get the Length of the first buffer address */
1273 rxbuff->len = heth->Init.RxBuffLen;
1274 /* Point to next buffer */
1275 rxbuff = (struct __ETH_BufferTypeDef *)rxbuff->next;
1276 /* Get the Address the Length of the second buffer address */
1277 rxbuff->buffer = (uint8_t *) dmarxdesc->BackupAddr1;
1278 rxbuff->len = lastdesclen - (heth->Init.RxBuffLen);
1279 }
1280 else /* Buffer 2 not valid*/
1281 {
1282 return HAL_ERROR;
1283 }
1284
1285 return HAL_OK;
1286 }
1287
1288 /**
1289 * @brief This function gets the length of last received Packet.
1290 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1291 * the configuration information for ETHERNET module
1292 * @param Length: parameter to hold Rx packet length
1293 * @retval HAL Status
1294 */
1295 HAL_StatusTypeDef HAL_ETH_GetRxDataLength(ETH_HandleTypeDef *heth, uint32_t *Length)
1296 {
1297 ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
1298 uint32_t descidx = dmarxdesclist->FirstAppDesc;
1299 __IO const ETH_DMADescTypeDef *dmarxdesc;
1300
1301 if(dmarxdesclist->AppDescNbr == 0U)
1302 {
1303 if(HAL_ETH_IsRxDataAvailable(heth) == 0U)
1304 {
1305 /* No data to be transferred to the application */
1306 return HAL_ERROR;
1307 }
1308 }
1309
1310 /* Get index of last descriptor */
1311 INCR_RX_DESC_INDEX(descidx, (dmarxdesclist->AppDescNbr - 1U));
1312 /* Point to last descriptor */
1313 dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
1314
1315 *Length = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL);
1316
1317 return HAL_OK;
1318 }
1319
1320 /**
1321 * @brief Get the Rx data info (Packet type, VLAN tag, Filters status, ...)
1322 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1323 * the configuration information for ETHERNET module
1324 * @param RxPacketInfo: parameter to hold info of received buffer
1325 * @retval HAL status
1326 */
1327 HAL_StatusTypeDef HAL_ETH_GetRxDataInfo(ETH_HandleTypeDef *heth, ETH_RxPacketInfo *RxPacketInfo)
1328 {
1329 ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
1330 uint32_t descidx = dmarxdesclist->FirstAppDesc;
1331 __IO const ETH_DMADescTypeDef *dmarxdesc;
1332
1333 if(dmarxdesclist->AppDescNbr == 0U)
1334 {
1335 if(HAL_ETH_IsRxDataAvailable(heth) == 0U)
1336 {
1337 /* No data to be transferred to the application */
1338 return HAL_ERROR;
1339 }
1340 }
1341
1342 /* Get index of last descriptor */
1343 INCR_RX_DESC_INDEX(descidx, ((dmarxdesclist->AppDescNbr) - 1U));
1344 /* Point to last descriptor */
1345 dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
1346
1347 if((dmarxdesc->DESC3 & ETH_DMARXNDESCWBF_ES) != (uint32_t)RESET)
1348 {
1349 RxPacketInfo->ErrorCode = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_ERRORS_MASK);
1350 }
1351 else
1352 {
1353 if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_RS0V) != 0U)
1354 {
1355
1356 if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_LT) == ETH_DMARXNDESCWBF_LT_DVLAN)
1357 {
1358 RxPacketInfo->VlanTag = READ_BIT(dmarxdesc->DESC0, ETH_DMARXNDESCWBF_OVT);
1359 RxPacketInfo->InnerVlanTag = READ_BIT(dmarxdesc->DESC0, ETH_DMARXNDESCWBF_IVT) >> 16;
1360 }
1361 else
1362 {
1363 RxPacketInfo->VlanTag = READ_BIT(dmarxdesc->DESC0, ETH_DMARXNDESCWBF_OVT);
1364 }
1365 }
1366
1367 if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_RS1V) != 0U)
1368 {
1369 /* Get Payload type */
1370 RxPacketInfo->PayloadType =READ_BIT( dmarxdesc->DESC1, ETH_DMARXNDESCWBF_PT);
1371 /* Get Header type */
1372 RxPacketInfo->HeaderType = READ_BIT(dmarxdesc->DESC1, (ETH_DMARXNDESCWBF_IPV4 | ETH_DMARXNDESCWBF_IPV6));
1373 /* Get Checksum status */
1374 RxPacketInfo->Checksum = READ_BIT(dmarxdesc->DESC1, (ETH_DMARXNDESCWBF_IPCE | ETH_DMARXNDESCWBF_IPCB | ETH_DMARXNDESCWBF_IPHE));
1375 }
1376
1377 if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_RS2V) != 0U)
1378 {
1379 RxPacketInfo->MacFilterStatus = READ_BIT(dmarxdesc->DESC2, (ETH_DMARXNDESCWBF_HF | ETH_DMARXNDESCWBF_DAF | ETH_DMARXNDESCWBF_SAF | ETH_DMARXNDESCWBF_VF));
1380 RxPacketInfo->L3FilterStatus = READ_BIT(dmarxdesc->DESC2, (ETH_DMARXNDESCWBF_L3FM | ETH_DMARXNDESCWBF_L3L4FM));
1381 RxPacketInfo->L4FilterStatus = READ_BIT(dmarxdesc->DESC2, (ETH_DMARXNDESCWBF_L4FM | ETH_DMARXNDESCWBF_L3L4FM));
1382 }
1383 }
1384
1385 /* Get the segment count */
1386 WRITE_REG(RxPacketInfo->SegmentCnt, dmarxdesclist->AppDescNbr);
1387
1388 return HAL_OK;
1389 }
1390
1391 /**
1392 * @brief This function gives back Rx Desc of the last received Packet
1393 * to the DMA, so ETH DMA will be able to use these descriptors
1394 * to receive next Packets.
1395 * It should be called after processing the received Packet.
1396 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1397 * the configuration information for ETHERNET module
1398 * @retval HAL status.
1399 */
1400 HAL_StatusTypeDef HAL_ETH_BuildRxDescriptors(ETH_HandleTypeDef *heth)
1401 {
1402 ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
1403 uint32_t descindex = dmarxdesclist->FirstAppDesc;
1404 __IO ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descindex];
1405 uint32_t totalappdescnbr = dmarxdesclist->AppDescNbr;
1406 uint32_t descscan;
1407
1408 if(dmarxdesclist->AppDescNbr == 0U)
1409 {
1410 /* No Rx descriptors to build */
1411 return HAL_ERROR;
1412 }
1413
1414 if(dmarxdesclist->AppContextDesc != 0U)
1415 {
1416 /* A context descriptor is available */
1417 totalappdescnbr += 1U;
1418 }
1419
1420 for(descscan =0; descscan < totalappdescnbr; descscan++)
1421 {
1422 WRITE_REG(dmarxdesc->DESC0, dmarxdesc->BackupAddr0);
1423 WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF1V);
1424
1425 if (READ_REG(dmarxdesc->BackupAddr1) != 0U)
1426 {
1427 WRITE_REG(dmarxdesc->DESC2, dmarxdesc->BackupAddr1);
1428 SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF2V);
1429 }
1430
1431 SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN);
1432
1433 if(dmarxdesclist->ItMode != 0U)
1434 {
1435 SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
1436 }
1437
1438 if(descscan < (dmarxdesclist->AppDescNbr - 1U))
1439 {
1440 /* Increment rx descriptor index */
1441 INCR_RX_DESC_INDEX(descindex, 1U);
1442 /* Get descriptor address */
1443 dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descindex];
1444 }
1445 }
1446
1447 /* Set the Tail pointer address to the last rx descriptor hold by the app */
1448 WRITE_REG(heth->Instance->DMACRDTPR, (uint32_t)dmarxdesc);
1449
1450 /* reset the Application desc number */
1451 WRITE_REG(dmarxdesclist->AppDescNbr, 0);
1452
1453 return HAL_OK;
1454 }
1455
1456
1457 /**
1458 * @brief This function handles ETH interrupt request.
1459 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1460 * the configuration information for ETHERNET module
1461 * @retval HAL status
1462 */
1463 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
1464 {
1465 /* Packet received */
1466 if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_RI))
1467 {
1468 if(__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_RIE))
1469 {
1470
1471 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1472 /*Call registered Receive complete callback*/
1473 heth->RxCpltCallback(heth);
1474 #else
1475 /* Receive complete callback */
1476 HAL_ETH_RxCpltCallback(heth);
1477 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
1478
1479 /* Clear the Eth DMA Rx IT pending bits */
1480 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_RI | ETH_DMACSR_NIS);
1481 }
1482 }
1483
1484 /* Packet transmitted */
1485 if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_TI))
1486 {
1487 if(__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_TIE))
1488 {
1489 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1490 /*Call registered Transmit complete callback*/
1491 heth->TxCpltCallback(heth);
1492 #else
1493 /* Transfer complete callback */
1494 HAL_ETH_TxCpltCallback(heth);
1495 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
1496
1497 /* Clear the Eth DMA Tx IT pending bits */
1498 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_TI | ETH_DMACSR_NIS);
1499 }
1500 }
1501
1502
1503 /* ETH DMA Error */
1504 if(__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_AIS))
1505 {
1506 if(__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_AIE))
1507 {
1508 heth->ErrorCode |= HAL_ETH_ERROR_DMA;
1509
1510 /* if fatal bus error occured */
1511 if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_FBE))
1512 {
1513 /* Get DMA error code */
1514 heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_FBE | ETH_DMACSR_TPS | ETH_DMACSR_RPS));
1515
1516 /* Disable all interrupts */
1517 __HAL_ETH_DMA_DISABLE_IT(heth, ETH_DMACIER_NIE | ETH_DMACIER_AIE);
1518
1519 /* Set HAL state to ERROR */
1520 heth->gState = HAL_ETH_STATE_ERROR;
1521 }
1522 else
1523 {
1524 /* Get DMA error status */
1525 heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT |
1526 ETH_DMACSR_RBU | ETH_DMACSR_AIS));
1527
1528 /* Clear the interrupt summary flag */
1529 __HAL_ETH_DMA_CLEAR_IT(heth, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT |
1530 ETH_DMACSR_RBU | ETH_DMACSR_AIS));
1531 }
1532 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1533 /* Call registered DMA Error callback*/
1534 heth->DMAErrorCallback(heth);
1535 #else
1536 /* Ethernet DMA Error callback */
1537 HAL_ETH_DMAErrorCallback(heth);
1538 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
1539
1540 }
1541 }
1542
1543 /* ETH MAC Error IT */
1544 if(__HAL_ETH_MAC_GET_IT(heth, (ETH_MACIER_RXSTSIE | ETH_MACIER_TXSTSIE)))
1545 {
1546 /* Get MAC Rx Tx status and clear Status register pending bit */
1547 heth->MACErrorCode = READ_REG(heth->Instance->MACRXTXSR);
1548
1549 heth->gState = HAL_ETH_STATE_ERROR;
1550
1551 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1552 /* Call registered MAC Error callback*/
1553 heth->DMAErrorCallback(heth);
1554 #else
1555 /* Ethernet MAC Error callback */
1556 HAL_ETH_MACErrorCallback(heth);
1557 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
1558
1559 heth->MACErrorCode = (uint32_t)(0x0U);
1560 }
1561
1562 /* ETH PMT IT */
1563 if(__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_PMT_IT))
1564 {
1565 /* Get MAC Wake-up source and clear the status register pending bit */
1566 heth->MACWakeUpEvent = READ_BIT(heth->Instance->MACPCSR, (ETH_MACPCSR_RWKPRCVD | ETH_MACPCSR_MGKPRCVD));
1567
1568 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1569 /* Call registered PMT callback*/
1570 heth->PMTCallback(heth);
1571 #else
1572 /* Ethernet PMT callback */
1573 HAL_ETH_PMTCallback(heth);
1574 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
1575
1576 heth->MACWakeUpEvent = (uint32_t)(0x0U);
1577 }
1578
1579 /* ETH EEE IT */
1580 if(__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_LPI_IT))
1581 {
1582 /* Get MAC LPI interrupt source and clear the status register pending bit */
1583 heth->MACLPIEvent = READ_BIT(heth->Instance->MACPCSR, 0x0000000FU);
1584
1585 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1586 /* Call registered EEE callback*/
1587 heth->EEECallback(heth);
1588 #else
1589 /* Ethernet EEE callback */
1590 HAL_ETH_EEECallback(heth);
1591 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
1592
1593 heth->MACLPIEvent = (uint32_t)(0x0U);
1594 }
1595
1596 #if defined(DUAL_CORE)
1597 if (HAL_GetCurrentCPUID() == CM7_CPUID)
1598 {
1599 /* check ETH WAKEUP exti flag */
1600 if(__HAL_ETH_WAKEUP_EXTI_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
1601 {
1602 /* Clear ETH WAKEUP Exti pending bit */
1603 __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE);
1604 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1605 /* Call registered WakeUp callback*/
1606 heth->WakeUpCallback(heth);
1607 #else
1608 /* ETH WAKEUP callback */
1609 HAL_ETH_WakeUpCallback(heth);
1610 #endif
1611 }
1612 }
1613 else
1614 {
1615 /* check ETH WAKEUP exti flag */
1616 if(__HAL_ETH_WAKEUP_EXTID2_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
1617 {
1618 /* Clear ETH WAKEUP Exti pending bit */
1619 __HAL_ETH_WAKEUP_EXTID2_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE);
1620 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1621 /* Call registered WakeUp callback*/
1622 heth->WakeUpCallback(heth);
1623 #else
1624 /* ETH WAKEUP callback */
1625 HAL_ETH_WakeUpCallback(heth);
1626 #endif
1627 }
1628 }
1629 #else
1630 /* check ETH WAKEUP exti flag */
1631 if(__HAL_ETH_WAKEUP_EXTI_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
1632 {
1633 /* Clear ETH WAKEUP Exti pending bit */
1634 __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE);
1635 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1636 /* Call registered WakeUp callback*/
1637 heth->WakeUpCallback(heth);
1638 #else
1639 /* ETH WAKEUP callback */
1640 HAL_ETH_WakeUpCallback(heth);
1641 #endif
1642 }
1643 #endif
1644 }
1645
1646 /**
1647 * @brief Tx Transfer completed callbacks.
1648 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1649 * the configuration information for ETHERNET module
1650 * @retval None
1651 */
1652 __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
1653 {
1654 /* Prevent unused argument(s) compilation warning */
1655 UNUSED(heth);
1656 /* NOTE : This function Should not be modified, when the callback is needed,
1657 the HAL_ETH_TxCpltCallback could be implemented in the user file
1658 */
1659 }
1660
1661 /**
1662 * @brief Rx Transfer completed callbacks.
1663 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1664 * the configuration information for ETHERNET module
1665 * @retval None
1666 */
1667 __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
1668 {
1669 /* Prevent unused argument(s) compilation warning */
1670 UNUSED(heth);
1671 /* NOTE : This function Should not be modified, when the callback is needed,
1672 the HAL_ETH_RxCpltCallback could be implemented in the user file
1673 */
1674 }
1675
1676 /**
1677 * @brief Ethernet DMA transfer error callbacks
1678 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1679 * the configuration information for ETHERNET module
1680 * @retval None
1681 */
1682 __weak void HAL_ETH_DMAErrorCallback(ETH_HandleTypeDef *heth)
1683 {
1684 /* Prevent unused argument(s) compilation warning */
1685 UNUSED(heth);
1686 /* NOTE : This function Should not be modified, when the callback is needed,
1687 the HAL_ETH_DMAErrorCallback could be implemented in the user file
1688 */
1689 }
1690
1691 /**
1692 * @brief Ethernet MAC transfer error callbacks
1693 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1694 * the configuration information for ETHERNET module
1695 * @retval None
1696 */
1697 __weak void HAL_ETH_MACErrorCallback(ETH_HandleTypeDef *heth)
1698 {
1699 /* Prevent unused argument(s) compilation warning */
1700 UNUSED(heth);
1701 /* NOTE : This function Should not be modified, when the callback is needed,
1702 the HAL_ETH_MACErrorCallback could be implemented in the user file
1703 */
1704 }
1705
1706 /**
1707 * @brief Ethernet Power Management module IT callback
1708 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1709 * the configuration information for ETHERNET module
1710 * @retval None
1711 */
1712 __weak void HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth)
1713 {
1714 /* Prevent unused argument(s) compilation warning */
1715 UNUSED(heth);
1716 /* NOTE : This function Should not be modified, when the callback is needed,
1717 the HAL_ETH_PMTCallback could be implemented in the user file
1718 */
1719 }
1720
1721 /**
1722 * @brief Energy Efficient Etherent IT callback
1723 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1724 * the configuration information for ETHERNET module
1725 * @retval None
1726 */
1727 __weak void HAL_ETH_EEECallback(ETH_HandleTypeDef *heth)
1728 {
1729 /* Prevent unused argument(s) compilation warning */
1730 UNUSED(heth);
1731 /* NOTE : This function Should not be modified, when the callback is needed,
1732 the HAL_ETH_EEECallback could be implemented in the user file
1733 */
1734 }
1735
1736 /**
1737 * @brief ETH WAKEUP interrupt callback
1738 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1739 * the configuration information for ETHERNET module
1740 * @retval None
1741 */
1742 __weak void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth)
1743 {
1744 /* Prevent unused argument(s) compilation warning */
1745 UNUSED(heth);
1746 /* NOTE : This function Should not be modified, when the callback is needed,
1747 the HAL_ETH_WakeUpCallback could be implemented in the user file
1748 */
1749 }
1750
1751 /**
1752 * @brief Read a PHY register
1753 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1754 * the configuration information for ETHERNET module
1755 * @param PHYAddr: PHY port address, must be a value from 0 to 31
1756 * @param PHYReg: PHY register address, must be a value from 0 to 31
1757 * @param pRegValue: parameter to hold read value
1758 * @retval HAL status
1759 */
1760 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t *pRegValue)
1761 {
1762 uint32_t tmpreg, tickstart;
1763
1764 /* Check for the Busy flag */
1765 if(READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) != 0U)
1766 {
1767 return HAL_ERROR;
1768 }
1769
1770 /* Get the MACMDIOAR value */
1771 WRITE_REG(tmpreg, heth->Instance->MACMDIOAR);
1772
1773 /* Prepare the MDIO Address Register value
1774 - Set the PHY device address
1775 - Set the PHY register address
1776 - Set the read mode
1777 - Set the MII Busy bit */
1778
1779 MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (PHYAddr <<21));
1780 MODIFY_REG(tmpreg, ETH_MACMDIOAR_RDA, (PHYReg << 16));
1781 MODIFY_REG(tmpreg, ETH_MACMDIOAR_MOC, ETH_MACMDIOAR_MOC_RD);
1782 SET_BIT(tmpreg, ETH_MACMDIOAR_MB);
1783
1784 /* Write the result value into the MDII Address register */
1785 WRITE_REG(heth->Instance->MACMDIOAR, tmpreg);
1786
1787 tickstart = HAL_GetTick();
1788
1789 /* Wait for the Busy flag */
1790 while(READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U)
1791 {
1792 if(((HAL_GetTick() - tickstart ) > ETH_MDIO_BUS_TIMEOUT))
1793 {
1794 return HAL_ERROR;
1795 }
1796 }
1797
1798 /* Get MACMIIDR value */
1799 WRITE_REG(*pRegValue, (uint16_t)heth->Instance->MACMDIODR);
1800
1801 return HAL_OK;
1802 }
1803
1804
1805 /**
1806 * @brief Writes to a PHY register.
1807 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1808 * the configuration information for ETHERNET module
1809 * @param PHYAddr: PHY port address, must be a value from 0 to 31
1810 * @param PHYReg: PHY register address, must be a value from 0 to 31
1811 * @param RegValue: the value to write
1812 * @retval HAL status
1813 */
1814 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t RegValue)
1815 {
1816 uint32_t tmpreg, tickstart;
1817
1818 /* Check for the Busy flag */
1819 if(READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) != 0U)
1820 {
1821 return HAL_ERROR;
1822 }
1823
1824 /* Get the MACMDIOAR value */
1825 WRITE_REG(tmpreg, heth->Instance->MACMDIOAR);
1826
1827 /* Prepare the MDIO Address Register value
1828 - Set the PHY device address
1829 - Set the PHY register address
1830 - Set the write mode
1831 - Set the MII Busy bit */
1832
1833 MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (PHYAddr <<21));
1834 MODIFY_REG(tmpreg, ETH_MACMDIOAR_RDA, (PHYReg << 16));
1835 MODIFY_REG(tmpreg, ETH_MACMDIOAR_MOC, ETH_MACMDIOAR_MOC_WR);
1836 SET_BIT(tmpreg, ETH_MACMDIOAR_MB);
1837
1838
1839 /* Give the value to the MII data register */
1840 WRITE_REG(ETH->MACMDIODR, (uint16_t)RegValue);
1841
1842 /* Write the result value into the MII Address register */
1843 WRITE_REG(ETH->MACMDIOAR, tmpreg);
1844
1845 tickstart = HAL_GetTick();
1846
1847 /* Wait for the Busy flag */
1848 while(READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U)
1849 {
1850 if(((HAL_GetTick() - tickstart ) > ETH_MDIO_BUS_TIMEOUT))
1851 {
1852 return HAL_ERROR;
1853 }
1854 }
1855
1856 return HAL_OK;
1857 }
1858
1859 /**
1860 * @}
1861 */
1862
1863 /** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
1864 * @brief ETH control functions
1865 *
1866 @verbatim
1867 ==============================================================================
1868 ##### Peripheral Control functions #####
1869 ==============================================================================
1870 [..]
1871 This subsection provides a set of functions allowing to control the ETH
1872 peripheral.
1873
1874 @endverbatim
1875 * @{
1876 */
1877 /**
1878 * @brief Get the configuration of the MAC and MTL subsystems.
1879 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1880 * the configuration information for ETHERNET module
1881 * @param macconf: pointer to a ETH_MACConfigTypeDef structure that will hold
1882 * the configuration of the MAC.
1883 * @retval HAL Status
1884 */
1885 HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
1886 {
1887 if (macconf == NULL)
1888 {
1889 return HAL_ERROR;
1890 }
1891
1892 /* Get MAC parameters */
1893 macconf->PreambleLength = READ_BIT(heth->Instance->MACCR, ETH_MACCR_PRELEN);
1894 macconf->DeferralCheck = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DC)>> 4) > 0U) ? ENABLE : DISABLE;
1895 macconf->BackOffLimit = READ_BIT(heth->Instance->MACCR, ETH_MACCR_BL);
1896 macconf->RetryTransmission = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DR) >> 8) == 0U) ? ENABLE : DISABLE;
1897 macconf->CarrierSenseDuringTransmit = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DCRS) >> 9) > 0U) ? ENABLE : DISABLE;
1898 macconf->ReceiveOwn = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DO) >> 10) == 0U) ? ENABLE : DISABLE;
1899 macconf->CarrierSenseBeforeTransmit = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_ECRSFD) >> 11) > 0U) ? ENABLE : DISABLE;
1900 macconf->LoopbackMode = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_LM) >> 12) > 0U) ? ENABLE : DISABLE;
1901 macconf->DuplexMode = READ_BIT(heth->Instance->MACCR, ETH_MACCR_DM);
1902 macconf->Speed = READ_BIT(heth->Instance->MACCR, ETH_MACCR_FES);
1903 macconf->JumboPacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_JE) >> 16) > 0U) ? ENABLE : DISABLE;
1904 macconf->Jabber = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_JD) >>17) == 0U) ? ENABLE : DISABLE;
1905 macconf->Watchdog = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_WD) >>19) == 0U) ? ENABLE : DISABLE;
1906 macconf->AutomaticPadCRCStrip = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_ACS) >> 20) > 0U) ? ENABLE : DISABLE;
1907 macconf->CRCStripTypePacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_CST) >> 21) > 0U) ? ENABLE : DISABLE;
1908 macconf->Support2KPacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_S2KP) >> 22) > 0U) ? ENABLE : DISABLE;
1909 macconf->GiantPacketSizeLimitControl = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_GPSLCE) >> 23) > 0U) ? ENABLE : DISABLE;
1910 macconf->InterPacketGapVal = READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPG);
1911 macconf->ChecksumOffload = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPC) >> 27) > 0U) ? ENABLE : DISABLE;
1912 macconf->SourceAddrControl = READ_BIT(heth->Instance->MACCR, ETH_MACCR_SARC);
1913
1914 macconf->GiantPacketSizeLimit = READ_BIT(heth->Instance->MACECR, ETH_MACECR_GPSL);
1915 macconf->CRCCheckingRxPackets = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_DCRCC) >> 16) == 0U) ? ENABLE : DISABLE;
1916 macconf->SlowProtocolDetect = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_SPEN) >> 17) > 0U) ? ENABLE : DISABLE;
1917 macconf->UnicastSlowProtocolPacketDetect = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_USP) >> 18) > 0U) ? ENABLE : DISABLE;
1918 macconf->ExtendedInterPacketGap = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPGEN) >> 24) > 0U) ? ENABLE : DISABLE;
1919 macconf->ExtendedInterPacketGapVal = READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPG) >> 25;
1920
1921
1922 macconf->ProgrammableWatchdog = ((READ_BIT(heth->Instance->MACWTR, ETH_MACWTR_PWE) >> 8) > 0U) ? ENABLE : DISABLE;
1923 macconf->WatchdogTimeout = READ_BIT(heth->Instance->MACWTR, ETH_MACWTR_WTO);
1924
1925 macconf->TransmitFlowControl = ((READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_TFE) >> 1) > 0U) ? ENABLE : DISABLE;
1926 macconf->ZeroQuantaPause = ((READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_DZPQ) >> 7) == 0U) ? ENABLE : DISABLE;
1927 macconf->PauseLowThreshold = READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_PLT);
1928 macconf->PauseTime = (READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_PT) >> 16);
1929
1930
1931 macconf->ReceiveFlowControl = (READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_RFE) > 0U) ? ENABLE : DISABLE;
1932 macconf->UnicastPausePacketDetect = ((READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_UP) >> 1) > 0U) ? ENABLE : DISABLE;
1933
1934 macconf->TransmitQueueMode = READ_BIT(heth->Instance->MTLTQOMR, (ETH_MTLTQOMR_TTC | ETH_MTLTQOMR_TSF));
1935
1936 macconf->ReceiveQueueMode = READ_BIT(heth->Instance->MTLRQOMR, (ETH_MTLRQOMR_RTC | ETH_MTLRQOMR_RSF));
1937 macconf->ForwardRxUndersizedGoodPacket = ((READ_BIT(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_FUP) >> 3) > 0U) ? ENABLE : DISABLE;
1938 macconf->ForwardRxErrorPacket = ((READ_BIT(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_FEP) >> 4) > 0U) ? ENABLE : DISABLE;
1939 macconf->DropTCPIPChecksumErrorPacket = ((READ_BIT(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_DISTCPEF) >> 6) == 0U) ? ENABLE : DISABLE;
1940
1941 return HAL_OK;
1942 }
1943
1944 /**
1945 * @brief Get the configuration of the DMA.
1946 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1947 * the configuration information for ETHERNET module
1948 * @param dmaconf: pointer to a ETH_DMAConfigTypeDef structure that will hold
1949 * the configuration of the ETH DMA.
1950 * @retval HAL Status
1951 */
1952 HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)
1953 {
1954 if (dmaconf == NULL)
1955 {
1956 return HAL_ERROR;
1957 }
1958
1959 dmaconf->AddressAlignedBeats = ((READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_AAL) >> 12) > 0U) ? ENABLE : DISABLE;
1960 dmaconf->BurstMode = READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_FB | ETH_DMASBMR_MB);
1961 dmaconf->RebuildINCRxBurst = ((READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_RB)>> 15) > 0U) ? ENABLE : DISABLE;
1962
1963 dmaconf->DMAArbitration = READ_BIT(heth->Instance->DMAMR, (ETH_DMAMR_TXPR |ETH_DMAMR_PR | ETH_DMAMR_DA));
1964
1965 dmaconf->PBLx8Mode = ((READ_BIT(heth->Instance->DMACCR, ETH_DMACCR_8PBL)>> 16) > 0U) ? ENABLE : DISABLE;
1966 dmaconf->MaximumSegmentSize = READ_BIT(heth->Instance->DMACCR, ETH_DMACCR_MSS);
1967
1968 dmaconf->FlushRxPacket = ((READ_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_RPF) >> 31) > 0U) ? ENABLE : DISABLE;
1969 dmaconf->RxDMABurstLength = READ_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_RPBL);
1970
1971 dmaconf->SecondPacketOperate = ((READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_OSP) >> 4) > 0U) ? ENABLE : DISABLE;
1972 dmaconf->TCPSegmentation = ((READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_TSE) >> 12) > 0U) ? ENABLE : DISABLE;
1973 dmaconf->TxDMABurstLength = READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_TPBL);
1974
1975 return HAL_OK;
1976 }
1977
1978 /**
1979 * @brief Set the MAC configuration.
1980 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1981 * the configuration information for ETHERNET module
1982 * @param macconf: pointer to a ETH_MACConfigTypeDef structure that contains
1983 * the configuration of the MAC.
1984 * @retval HAL status
1985 */
1986 HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
1987 {
1988 if(macconf == NULL)
1989 {
1990 return HAL_ERROR;
1991 }
1992
1993 if(heth->RxState == HAL_ETH_STATE_READY)
1994 {
1995 ETH_SetMACConfig(heth, macconf);
1996
1997 return HAL_OK;
1998 }
1999 else
2000 {
2001 return HAL_ERROR;
2002 }
2003 }
2004
2005 /**
2006 * @brief Set the ETH DMA configuration.
2007 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2008 * the configuration information for ETHERNET module
2009 * @param dmaconf: pointer to a ETH_DMAConfigTypeDef structure that will hold
2010 * the configuration of the ETH DMA.
2011 * @retval HAL status
2012 */
2013 HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)
2014 {
2015 if(dmaconf == NULL)
2016 {
2017 return HAL_ERROR;
2018 }
2019
2020 if(heth->RxState == HAL_ETH_STATE_READY)
2021 {
2022 ETH_SetDMAConfig(heth, dmaconf);
2023
2024 return HAL_OK;
2025 }
2026 else
2027 {
2028 return HAL_ERROR;
2029 }
2030 }
2031
2032 /**
2033 * @brief Configures the Clock range of ETH MDIO interface.
2034 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2035 * the configuration information for ETHERNET module
2036 * @retval None
2037 */
2038 void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth)
2039 {
2040 uint32_t tmpreg, hclk;
2041
2042 /* Get the ETHERNET MACMDIOAR value */
2043 tmpreg = (heth->Instance)->MACMDIOAR;
2044
2045 /* Clear CSR Clock Range bits */
2046 tmpreg &= ~ETH_MACMDIOAR_CR;
2047
2048 /* Get hclk frequency value */
2049 hclk = HAL_RCC_GetHCLKFreq();
2050
2051 /* Set CR bits depending on hclk value */
2052 if((hclk >= 20000000U)&&(hclk < 35000000U))
2053 {
2054 /* CSR Clock Range between 20-35 MHz */
2055 tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV16;
2056 }
2057 else if((hclk >= 35000000U)&&(hclk < 60000000U))
2058 {
2059 /* CSR Clock Range between 35-60 MHz */
2060 tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV26;
2061 }
2062 else if((hclk >= 60000000U)&&(hclk < 100000000U))
2063 {
2064 /* CSR Clock Range between 60-100 MHz */
2065 tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV42;
2066 }
2067 else if((hclk >= 100000000U)&&(hclk < 150000000U))
2068 {
2069 /* CSR Clock Range between 100-150 MHz */
2070 tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV62;
2071 }
2072 else /* (hclk >= 150000000)&&(hclk <= 200000000) */
2073 {
2074 /* CSR Clock Range between 150-200 MHz */
2075 tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV102;
2076 }
2077
2078 /* Configure the CSR Clock Range */
2079 (heth->Instance)->MACMDIOAR = (uint32_t)tmpreg;
2080 }
2081
2082 /**
2083 * @brief Set the ETH MAC (L2) Filters configuration.
2084 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2085 * the configuration information for ETHERNET module
2086 * @param pFilterConfig: pointer to a ETH_MACFilterConfigTypeDef structure that contains
2087 * the configuration of the ETH MAC filters.
2088 * @retval HAL status
2089 */
2090 HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig)
2091 {
2092 uint32_t filterconfig;
2093
2094 if(pFilterConfig == NULL)
2095 {
2096 return HAL_ERROR;
2097 }
2098
2099 filterconfig = ((uint32_t)pFilterConfig->PromiscuousMode |
2100 ((uint32_t)pFilterConfig->HashUnicast << 1) |
2101 ((uint32_t)pFilterConfig->HashMulticast << 2) |
2102 ((uint32_t)pFilterConfig->DestAddrInverseFiltering << 3) |
2103 ((uint32_t)pFilterConfig->PassAllMulticast << 4) |
2104 ((uint32_t)((pFilterConfig->BroadcastFilter == DISABLE) ? 1U : 0U) << 5) |
2105 ((uint32_t)pFilterConfig->SrcAddrInverseFiltering << 8) |
2106 ((uint32_t)pFilterConfig->SrcAddrFiltering << 9) |
2107 ((uint32_t)pFilterConfig->HachOrPerfectFilter << 10) |
2108 ((uint32_t)pFilterConfig->ReceiveAllMode << 31) |
2109 pFilterConfig->ControlPacketsFilter);
2110
2111 MODIFY_REG(heth->Instance->MACPFR, ETH_MACPFR_MASK, filterconfig);
2112
2113 return HAL_OK;
2114 }
2115
2116 /**
2117 * @brief Get the ETH MAC (L2) Filters configuration.
2118 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2119 * the configuration information for ETHERNET module
2120 * @param pFilterConfig: pointer to a ETH_MACFilterConfigTypeDef structure that will hold
2121 * the configuration of the ETH MAC filters.
2122 * @retval HAL status
2123 */
2124 HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig)
2125 {
2126 if(pFilterConfig == NULL)
2127 {
2128 return HAL_ERROR;
2129 }
2130
2131 pFilterConfig->PromiscuousMode = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PR)) > 0U) ? ENABLE : DISABLE;
2132 pFilterConfig->HashUnicast = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HUC) >> 1) > 0U) ? ENABLE : DISABLE;
2133 pFilterConfig->HashMulticast = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HMC) >> 2) > 0U) ? ENABLE : DISABLE;
2134 pFilterConfig->DestAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DAIF) >> 3) > 0U) ? ENABLE : DISABLE;
2135 pFilterConfig->PassAllMulticast = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PM) >> 4) > 0U) ? ENABLE : DISABLE;
2136 pFilterConfig->BroadcastFilter = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DBF) >> 5) == 0U) ? ENABLE : DISABLE;
2137 pFilterConfig->ControlPacketsFilter = READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PCF);
2138 pFilterConfig->SrcAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_SAIF) >> 8) > 0U) ? ENABLE : DISABLE;
2139 pFilterConfig->SrcAddrFiltering = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_SAF) >> 9) > 0U) ? ENABLE : DISABLE;
2140 pFilterConfig->HachOrPerfectFilter = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HPF) >> 10) > 0U) ? ENABLE : DISABLE;
2141 pFilterConfig->ReceiveAllMode = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_RA) >> 31) > 0U) ? ENABLE : DISABLE;
2142
2143 return HAL_OK;
2144 }
2145
2146 /**
2147 * @brief Set the source MAC Address to be matched.
2148 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2149 * the configuration information for ETHERNET module
2150 * @param AddrNbr: The MAC address to configure
2151 * This parameter must be a value of the following:
2152 * ETH_MAC_ADDRESS1
2153 * ETH_MAC_ADDRESS2
2154 * ETH_MAC_ADDRESS3
2155 * @param pMACAddr: Pointer to MAC address buffer data (6 bytes)
2156 * @retval HAL status
2157 */
2158 HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr)
2159 {
2160 uint32_t macaddrhr, macaddrlr;
2161
2162 if(pMACAddr == NULL)
2163 {
2164 return HAL_ERROR;
2165 }
2166
2167 /* Get mac addr high reg offset */
2168 macaddrhr = ((uint32_t)&(heth->Instance->MACA0HR) + AddrNbr);
2169 /* Get mac addr low reg offset */
2170 macaddrlr = ((uint32_t)&(heth->Instance->MACA0LR) + AddrNbr);
2171
2172 /* Set MAC addr bits 32 to 47 */
2173 (*(__IO uint32_t *)macaddrhr) = (((uint32_t)(pMACAddr[5]) << 8) | (uint32_t)pMACAddr[4]);
2174 /* Set MAC addr bits 0 to 31 */
2175 (*(__IO uint32_t *)macaddrlr) = (((uint32_t)(pMACAddr[3]) << 24) | ((uint32_t)(pMACAddr[2]) << 16) |
2176 ((uint32_t)(pMACAddr[1]) << 8) | (uint32_t)pMACAddr[0]);
2177
2178 /* Enable address and set source address bit */
2179 (*(__IO uint32_t *)macaddrhr) |= (ETH_MACAHR_SA | ETH_MACAHR_AE);
2180
2181 return HAL_OK;
2182 }
2183
2184 /**
2185 * @brief Set the ETH Hash Table Value.
2186 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2187 * the configuration information for ETHERNET module
2188 * @param pHashTable: pointer to a table of two 32 bit values, that contains
2189 * the 64 bits of the hash table.
2190 * @retval HAL status
2191 */
2192 HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable)
2193 {
2194 if(pHashTable == NULL)
2195 {
2196 return HAL_ERROR;
2197 }
2198
2199 heth->Instance->MACHT0R = pHashTable[0];
2200 heth->Instance->MACHT1R = pHashTable[1];
2201
2202 return HAL_OK;
2203 }
2204
2205 /**
2206 * @brief Set the VLAN Identifier for Rx packets
2207 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2208 * the configuration information for ETHERNET module
2209 * @param ComparisonBits: 12 or 16 bit comparison mode
2210 must be a value of @ref ETH_VLAN_Tag_Comparison
2211 * @param VLANIdentifier: VLAN Identifier value
2212 * @retval None
2213 */
2214 void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, uint32_t VLANIdentifier)
2215 {
2216 if(ComparisonBits == ETH_VLANTAGCOMPARISON_16BIT)
2217 {
2218 MODIFY_REG(heth->Instance->MACVTR, ETH_MACVTR_VL , VLANIdentifier);
2219 CLEAR_BIT(heth->Instance->MACVTR, ETH_MACVTR_ETV);
2220 }
2221 else
2222 {
2223 MODIFY_REG(heth->Instance->MACVTR, ETH_MACVTR_VL_VID , VLANIdentifier);
2224 SET_BIT(heth->Instance->MACVTR, ETH_MACVTR_ETV);
2225 }
2226 }
2227
2228 /**
2229 * @brief Enters the Power down mode.
2230 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2231 * the configuration information for ETHERNET module
2232 * @param pPowerDownConfig: a pointer to ETH_PowerDownConfigTypeDef structure
2233 * that contains the Power Down configration
2234 * @retval None.
2235 */
2236 void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig)
2237 {
2238 uint32_t powerdownconfig;
2239
2240 powerdownconfig = (((uint32_t)pPowerDownConfig->MagicPacket << 1) |
2241 ((uint32_t)pPowerDownConfig->WakeUpPacket << 2) |
2242 ((uint32_t)pPowerDownConfig->GlobalUnicast << 9) |
2243 ((uint32_t)pPowerDownConfig->WakeUpForward << 10) |
2244 ETH_MACPCSR_PWRDWN);
2245
2246 /* Enable PMT interrupt */
2247 __HAL_ETH_MAC_ENABLE_IT(heth, ETH_MACIER_PMTIE);
2248
2249 MODIFY_REG(heth->Instance->MACPCSR, ETH_MACPCSR_MASK, powerdownconfig);
2250 }
2251
2252 /**
2253 * @brief Exits from the Power down mode.
2254 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2255 * the configuration information for ETHERNET module
2256 * @retval None.
2257 */
2258 void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth)
2259 {
2260 /* clear wake up sources */
2261 CLEAR_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_RWKPKTEN | ETH_MACPCSR_MGKPKTEN | ETH_MACPCSR_GLBLUCAST | ETH_MACPCSR_RWKPFE);
2262
2263 if(READ_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_PWRDWN) != 0U)
2264 {
2265 /* Exit power down mode */
2266 CLEAR_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_PWRDWN);
2267 }
2268
2269 /* Disable PMT interrupt */
2270 __HAL_ETH_MAC_DISABLE_IT(heth, ETH_MACIER_PMTIE);
2271 }
2272
2273 /**
2274 * @brief Set the WakeUp filter.
2275 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2276 * the configuration information for ETHERNET module
2277 * @param pFilter: pointer to filter registers values
2278 * @param Count: number of filter registers, must be from 1 to 8.
2279 * @retval None.
2280 */
2281 HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count)
2282 {
2283 uint32_t regindex;
2284
2285 if(pFilter == NULL)
2286 {
2287 return HAL_ERROR;
2288 }
2289
2290 /* Reset Filter Pointer */
2291 SET_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_RWKFILTRST);
2292
2293 /* Wake up packet filter config */
2294 for(regindex = 0; regindex < Count; regindex++)
2295 {
2296 /* Write filter regs */
2297 WRITE_REG(heth->Instance->MACRWKPFR, pFilter[regindex]);
2298 }
2299
2300 return HAL_OK;
2301 }
2302
2303 /**
2304 * @}
2305 */
2306
2307 /** @defgroup ETH_Exported_Functions_Group4 Peripheral State and Errors functions
2308 * @brief ETH State and Errors functions
2309 *
2310 @verbatim
2311 ==============================================================================
2312 ##### Peripheral State and Errors functions #####
2313 ==============================================================================
2314 [..]
2315 This subsection provides a set of functions allowing to return the State of
2316 ETH communication process, return Peripheral Errors occurred during communication
2317 process
2318
2319
2320 @endverbatim
2321 * @{
2322 */
2323
2324 /**
2325 * @brief Returns the ETH state.
2326 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2327 * the configuration information for ETHERNET module
2328 * @retval HAL state
2329 */
2330 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
2331 {
2332 HAL_ETH_StateTypeDef ret;
2333 HAL_ETH_StateTypeDef gstate = heth->gState;
2334 HAL_ETH_StateTypeDef rxstate =heth->RxState;
2335
2336 ret = gstate;
2337 ret |= rxstate;
2338 return ret;
2339 }
2340
2341 /**
2342 * @brief Returns the ETH error code
2343 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2344 * the configuration information for ETHERNET module
2345 * @retval ETH Error Code
2346 */
2347 uint32_t HAL_ETH_GetError(ETH_HandleTypeDef *heth)
2348 {
2349 return heth->ErrorCode;
2350 }
2351
2352 /**
2353 * @brief Returns the ETH DMA error code
2354 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2355 * the configuration information for ETHERNET module
2356 * @retval ETH DMA Error Code
2357 */
2358 uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth)
2359 {
2360 return heth->DMAErrorCode;
2361 }
2362
2363 /**
2364 * @brief Returns the ETH MAC error code
2365 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2366 * the configuration information for ETHERNET module
2367 * @retval ETH MAC Error Code
2368 */
2369 uint32_t HAL_ETH_GetMACError(ETH_HandleTypeDef *heth)
2370 {
2371 return heth->MACErrorCode;
2372 }
2373
2374 /**
2375 * @brief Returns the ETH MAC WakeUp event source
2376 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2377 * the configuration information for ETHERNET module
2378 * @retval ETH MAC WakeUp event source
2379 */
2380 uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth)
2381 {
2382 return heth->MACWakeUpEvent;
2383 }
2384
2385 /**
2386 * @}
2387 */
2388
2389 /**
2390 * @}
2391 */
2392
2393 static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
2394 {
2395 uint32_t macregval;
2396
2397 /*------------------------ MACCR Configuration --------------------*/
2398 macregval =(macconf->InterPacketGapVal |
2399 macconf->SourceAddrControl |
2400 ((uint32_t)macconf->ChecksumOffload<< 27) |
2401 ((uint32_t)macconf->GiantPacketSizeLimitControl << 23) |
2402 ((uint32_t)macconf->Support2KPacket << 22) |
2403 ((uint32_t)macconf->CRCStripTypePacket << 21) |
2404 ((uint32_t)macconf->AutomaticPadCRCStrip << 20) |
2405 ((uint32_t)((macconf->Watchdog == DISABLE) ? 1U : 0U) << 19) |
2406 ((uint32_t)((macconf->Jabber == DISABLE) ? 1U : 0U) << 17) |
2407 ((uint32_t)macconf->JumboPacket << 16) |
2408 macconf->Speed |
2409 macconf->DuplexMode |
2410 ((uint32_t)macconf->LoopbackMode << 12) |
2411 ((uint32_t)macconf->CarrierSenseBeforeTransmit << 11)|
2412 ((uint32_t)((macconf->ReceiveOwn == DISABLE) ? 1U : 0U) << 10)|
2413 ((uint32_t)macconf->CarrierSenseDuringTransmit << 9)|
2414 ((uint32_t)((macconf->RetryTransmission == DISABLE) ? 1U : 0U) << 8)|
2415 macconf->BackOffLimit |
2416 ((uint32_t)macconf->DeferralCheck << 4)|
2417 macconf->PreambleLength);
2418
2419 /* Write to MACCR */
2420 MODIFY_REG(heth->Instance->MACCR, ETH_MACCR_MASK, macregval);
2421
2422 /*------------------------ MACECR Configuration --------------------*/
2423 macregval = ((macconf->ExtendedInterPacketGapVal << 25)|
2424 ((uint32_t)macconf->ExtendedInterPacketGap << 24)|
2425 ((uint32_t)macconf->UnicastSlowProtocolPacketDetect << 18)|
2426 ((uint32_t)macconf->SlowProtocolDetect << 17)|
2427 ((uint32_t)((macconf->CRCCheckingRxPackets == DISABLE) ? 1U : 0U)<< 16) |
2428 macconf->GiantPacketSizeLimit);
2429
2430 /* Write to MACECR */
2431 MODIFY_REG(heth->Instance->MACECR, ETH_MACECR_MASK, macregval);
2432
2433 /*------------------------ MACWTR Configuration --------------------*/
2434 macregval = (((uint32_t)macconf->ProgrammableWatchdog << 8) |
2435 macconf->WatchdogTimeout);
2436
2437 /* Write to MACWTR */
2438 MODIFY_REG(heth->Instance->MACWTR, ETH_MACWTR_MASK, macregval);
2439
2440 /*------------------------ MACTFCR Configuration --------------------*/
2441 macregval = (((uint32_t)macconf->TransmitFlowControl << 1) |
2442 macconf->PauseLowThreshold |
2443 ((uint32_t)((macconf->ZeroQuantaPause == DISABLE) ? 1U : 0U)<< 7) |
2444 (macconf->PauseTime << 16));
2445
2446 /* Write to MACTFCR */
2447 MODIFY_REG(heth->Instance->MACTFCR, ETH_MACTFCR_MASK, macregval);
2448
2449 /*------------------------ MACRFCR Configuration --------------------*/
2450 macregval = ((uint32_t)macconf->ReceiveFlowControl |
2451 ((uint32_t)macconf->UnicastPausePacketDetect << 1));
2452
2453 /* Write to MACRFCR */
2454 MODIFY_REG(heth->Instance->MACRFCR, ETH_MACRFCR_MASK, macregval);
2455
2456 /*------------------------ MTLTQOMR Configuration --------------------*/
2457 /* Write to MTLTQOMR */
2458 MODIFY_REG(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_MASK, macconf->TransmitQueueMode);
2459
2460 /*------------------------ MTLRQOMR Configuration --------------------*/
2461 macregval = (macconf->ReceiveQueueMode |
2462 ((uint32_t)((macconf->DropTCPIPChecksumErrorPacket == DISABLE) ? 1U : 0U) << 6) |
2463 ((uint32_t)macconf->ForwardRxErrorPacket << 4) |
2464 ((uint32_t)macconf->ForwardRxUndersizedGoodPacket << 3));
2465
2466 /* Write to MTLRQOMR */
2467 MODIFY_REG(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_MASK, macregval);
2468 }
2469
2470 static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)
2471 {
2472 uint32_t dmaregval;
2473
2474 /*------------------------ DMAMR Configuration --------------------*/
2475 MODIFY_REG(heth->Instance->DMAMR, ETH_DMAMR_MASK, dmaconf->DMAArbitration);
2476
2477 /*------------------------ DMASBMR Configuration --------------------*/
2478 dmaregval = (((uint32_t)dmaconf->AddressAlignedBeats << 12) |
2479 dmaconf->BurstMode |
2480 ((uint32_t)dmaconf->RebuildINCRxBurst << 15));
2481
2482 MODIFY_REG(heth->Instance->DMASBMR, ETH_DMASBMR_MASK, dmaregval);
2483
2484 /*------------------------ DMACCR Configuration --------------------*/
2485 dmaregval = (((uint32_t)dmaconf->PBLx8Mode << 16) |
2486 dmaconf->MaximumSegmentSize);
2487
2488 MODIFY_REG(heth->Instance->DMACCR, ETH_DMACCR_MASK, dmaregval);
2489
2490 /*------------------------ DMACTCR Configuration --------------------*/
2491 dmaregval = (dmaconf->TxDMABurstLength |
2492 ((uint32_t)dmaconf->SecondPacketOperate << 4)|
2493 ((uint32_t)dmaconf->TCPSegmentation << 12));
2494
2495 MODIFY_REG(heth->Instance->DMACTCR, ETH_DMACTCR_MASK, dmaregval);
2496
2497 /*------------------------ DMACRCR Configuration --------------------*/
2498 dmaregval = (((uint32_t)dmaconf->FlushRxPacket << 31) |
2499 dmaconf->RxDMABurstLength);
2500
2501 /* Write to DMACRCR */
2502 MODIFY_REG(heth->Instance->DMACRCR, ETH_DMACRCR_MASK, dmaregval);
2503 }
2504
2505 /**
2506 * @brief Configures Ethernet MAC and DMA with default parameters.
2507 * called by HAL_ETH_Init() API.
2508 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2509 * the configuration information for ETHERNET module
2510 * @retval HAL status
2511 */
2512 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth)
2513 {
2514 ETH_MACConfigTypeDef macDefaultConf;
2515 ETH_DMAConfigTypeDef dmaDefaultConf;
2516
2517 /*--------------- ETHERNET MAC registers default Configuration --------------*/
2518 macDefaultConf.AutomaticPadCRCStrip = ENABLE;
2519 macDefaultConf.BackOffLimit = ETH_BACKOFFLIMIT_10;
2520 macDefaultConf.CarrierSenseBeforeTransmit = DISABLE;
2521 macDefaultConf.CarrierSenseDuringTransmit = DISABLE;
2522 macDefaultConf.ChecksumOffload = ENABLE;
2523 macDefaultConf.CRCCheckingRxPackets = ENABLE;
2524 macDefaultConf.CRCStripTypePacket = ENABLE;
2525 macDefaultConf.DeferralCheck = DISABLE;
2526 macDefaultConf.DropTCPIPChecksumErrorPacket = ENABLE;
2527 macDefaultConf.DuplexMode = ETH_FULLDUPLEX_MODE;
2528 macDefaultConf.ExtendedInterPacketGap = DISABLE;
2529 macDefaultConf.ExtendedInterPacketGapVal = 0x0;
2530 macDefaultConf.ForwardRxErrorPacket = DISABLE;
2531 macDefaultConf.ForwardRxUndersizedGoodPacket = DISABLE;
2532 macDefaultConf.GiantPacketSizeLimit = 0x618;
2533 macDefaultConf.GiantPacketSizeLimitControl = DISABLE;
2534 macDefaultConf.InterPacketGapVal = ETH_INTERPACKETGAP_96BIT;
2535 macDefaultConf.Jabber = ENABLE;
2536 macDefaultConf.JumboPacket = DISABLE;
2537 macDefaultConf.LoopbackMode = DISABLE;
2538 macDefaultConf.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS_4;
2539 macDefaultConf.PauseTime = 0x0;
2540 macDefaultConf.PreambleLength = ETH_PREAMBLELENGTH_7;
2541 macDefaultConf.ProgrammableWatchdog = DISABLE;
2542 macDefaultConf.ReceiveFlowControl = DISABLE;
2543 macDefaultConf.ReceiveOwn = ENABLE;
2544 macDefaultConf.ReceiveQueueMode = ETH_RECEIVESTOREFORWARD;
2545 macDefaultConf.RetryTransmission = ENABLE;
2546 macDefaultConf.SlowProtocolDetect = DISABLE;
2547 macDefaultConf.SourceAddrControl = ETH_SOURCEADDRESS_REPLACE_ADDR0;
2548 macDefaultConf.Speed = ETH_SPEED_100M;
2549 macDefaultConf.Support2KPacket = DISABLE;
2550 macDefaultConf.TransmitQueueMode = ETH_TRANSMITSTOREFORWARD;
2551 macDefaultConf.TransmitFlowControl = DISABLE;
2552 macDefaultConf.UnicastPausePacketDetect = DISABLE;
2553 macDefaultConf.UnicastSlowProtocolPacketDetect = DISABLE;
2554 macDefaultConf.Watchdog = ENABLE;
2555 macDefaultConf.WatchdogTimeout = ETH_MACWTR_WTO_2KB;
2556 macDefaultConf.ZeroQuantaPause = ENABLE;
2557
2558 /* MAC default configuration */
2559 ETH_SetMACConfig(heth, &macDefaultConf);
2560
2561 /*--------------- ETHERNET DMA registers default Configuration --------------*/
2562 dmaDefaultConf.AddressAlignedBeats = ENABLE;
2563 dmaDefaultConf.BurstMode = ETH_BURSTLENGTH_FIXED;
2564 dmaDefaultConf.DMAArbitration = ETH_DMAARBITRATION_RX1_TX1;
2565 dmaDefaultConf.FlushRxPacket = DISABLE;
2566 dmaDefaultConf.PBLx8Mode = DISABLE;
2567 dmaDefaultConf.RebuildINCRxBurst = DISABLE;
2568 dmaDefaultConf.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
2569 dmaDefaultConf.SecondPacketOperate = DISABLE;
2570 dmaDefaultConf.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
2571 dmaDefaultConf.TCPSegmentation = DISABLE;
2572 dmaDefaultConf.MaximumSegmentSize = 536;
2573
2574 /* DMA default configuration */
2575 ETH_SetDMAConfig(heth, &dmaDefaultConf);
2576 }
2577
2578 /**
2579 * @brief Configures the Clock range of SMI interface.
2580 * called by HAL_ETH_Init() API.
2581 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2582 * the configuration information for ETHERNET module
2583 * @retval None
2584 */
2585 static void ETH_MAC_MDIO_ClkConfig(ETH_HandleTypeDef *heth)
2586 {
2587 uint32_t tmpreg, hclk;
2588
2589 /* Get the ETHERNET MACMDIOAR value */
2590 tmpreg = (heth->Instance)->MACMDIOAR;
2591
2592 /* Clear CSR Clock Range bits */
2593 tmpreg &= ~ETH_MACMDIOAR_CR;
2594
2595 /* Get hclk frequency value */
2596 hclk = HAL_RCC_GetHCLKFreq();
2597
2598 /* Set CR bits depending on hclk value */
2599 if((hclk >= 20000000U)&&(hclk < 35000000U))
2600 {
2601 /* CSR Clock Range between 20-35 MHz */
2602 tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV16;
2603 }
2604 else if((hclk >= 35000000U)&&(hclk < 60000000U))
2605 {
2606 /* CSR Clock Range between 35-60 MHz */
2607 tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV26;
2608 }
2609 else if((hclk >= 60000000U)&&(hclk < 100000000U))
2610 {
2611 /* CSR Clock Range between 60-100 MHz */
2612 tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV42;
2613 }
2614 else if((hclk >= 100000000U)&&(hclk < 150000000U))
2615 {
2616 /* CSR Clock Range between 100-150 MHz */
2617 tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV62;
2618 }
2619 else /* (hclk >= 150000000)&&(hclk <= 200000000) */
2620 {
2621 /* CSR Clock Range between 150-200 MHz */
2622 tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV102;
2623 }
2624
2625 /* Configure the CSR Clock Range */
2626 (heth->Instance)->MACMDIOAR = (uint32_t)tmpreg;
2627 }
2628
2629 /**
2630 * @brief Initializes the DMA Tx descriptors.
2631 * called by HAL_ETH_Init() API.
2632 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2633 * the configuration information for ETHERNET module
2634 * @retval None
2635 */
2636 static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth)
2637 {
2638 ETH_DMADescTypeDef *dmatxdesc;
2639 uint32_t i;
2640
2641 /* Fill each DMATxDesc descriptor with the right values */
2642 for(i=0; i < (uint32_t)ETH_TX_DESC_CNT; i++)
2643 {
2644 dmatxdesc = heth->Init.TxDesc + i;
2645
2646 WRITE_REG(dmatxdesc->DESC0, 0x0);
2647 WRITE_REG(dmatxdesc->DESC1, 0x0);
2648 WRITE_REG(dmatxdesc->DESC2, 0x0);
2649 WRITE_REG(dmatxdesc->DESC3, 0x0);
2650
2651 WRITE_REG(heth->TxDescList.TxDesc[i], (uint32_t)dmatxdesc);
2652 }
2653
2654 heth->TxDescList.CurTxDesc = 0;
2655
2656 /* Set Transmit Descriptor Ring Length */
2657 WRITE_REG(heth->Instance->DMACTDRLR, (ETH_TX_DESC_CNT -1));
2658
2659 /* Set Transmit Descriptor List Address */
2660 WRITE_REG(heth->Instance->DMACTDLAR, (uint32_t) heth->Init.TxDesc);
2661
2662 /* Set Transmit Descriptor Tail pointer */
2663 WRITE_REG(heth->Instance->DMACTDTPR, (uint32_t) heth->Init.TxDesc);
2664 }
2665
2666 /**
2667 * @brief Initializes the DMA Rx descriptors in chain mode.
2668 * called by HAL_ETH_Init() API.
2669 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2670 * the configuration information for ETHERNET module
2671 * @retval None
2672 */
2673 static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth)
2674 {
2675 ETH_DMADescTypeDef *dmarxdesc;
2676 uint32_t i;
2677
2678 for(i = 0; i < (uint32_t)ETH_RX_DESC_CNT; i++)
2679 {
2680 dmarxdesc = heth->Init.RxDesc + i;
2681
2682 WRITE_REG(dmarxdesc->DESC0, 0x0);
2683 WRITE_REG(dmarxdesc->DESC1, 0x0);
2684 WRITE_REG(dmarxdesc->DESC2, 0x0);
2685 WRITE_REG(dmarxdesc->DESC3, 0x0);
2686 WRITE_REG(dmarxdesc->BackupAddr0, 0x0);
2687 WRITE_REG(dmarxdesc->BackupAddr1, 0x0);
2688
2689 /* Set Rx descritors adresses */
2690 WRITE_REG(heth->RxDescList.RxDesc[i], (uint32_t)dmarxdesc);
2691 }
2692
2693 WRITE_REG(heth->RxDescList.CurRxDesc, 0);
2694 WRITE_REG(heth->RxDescList.FirstAppDesc, 0);
2695 WRITE_REG(heth->RxDescList.AppDescNbr, 0);
2696 WRITE_REG(heth->RxDescList.ItMode, 0);
2697 WRITE_REG(heth->RxDescList.AppContextDesc, 0);
2698
2699 /* Set Receive Descriptor Ring Length */
2700 WRITE_REG(heth->Instance->DMACRDRLR, ((uint32_t)(ETH_RX_DESC_CNT - 1)));
2701
2702 /* Set Receive Descriptor List Address */
2703 WRITE_REG(heth->Instance->DMACRDLAR, (uint32_t) heth->Init.RxDesc);
2704
2705 /* Set Receive Descriptor Tail pointer Address */
2706 WRITE_REG(heth->Instance->DMACRDTPR, ((uint32_t)(heth->Init.RxDesc + (((uint32_t)(ETH_RX_DESC_CNT - 1))*sizeof(ETH_DMADescTypeDef)))));
2707 }
2708
2709 /**
2710 * @brief Prepare Tx DMA descriptor before transmission.
2711 * called by HAL_ETH_Transmit_IT and HAL_ETH_Transmit_IT() API.
2712 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2713 * the configuration information for ETHERNET module
2714 * @param pTxConfig: Tx packet configuration
2715 * @param ItMode: Enable or disable Tx EOT interrept
2716 * @retval Status
2717 */
2718 static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t ItMode)
2719 {
2720 ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList;
2721 uint32_t descidx = dmatxdesclist->CurTxDesc;
2722 uint32_t firstdescidx = dmatxdesclist->CurTxDesc;
2723 uint32_t descnbr = 0, idx;
2724 ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
2725
2726 ETH_BufferTypeDef *txbuffer = pTxConfig->TxBuffer;
2727
2728 /* Current Tx Descriptor Owned by DMA: cannot be used by the application */
2729 if(READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN)
2730 {
2731 return HAL_ETH_ERROR_BUSY;
2732 }
2733
2734 /***************************************************************************/
2735 /***************** Context descriptor configuration (Optional) **********/
2736 /***************************************************************************/
2737 /* If VLAN tag is enabled for this packet */
2738 if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != 0U)
2739 {
2740 /* Set vlan tag value */
2741 MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXCDESC_VT, pTxConfig->VlanTag);
2742 /* Set vlan tag valid bit */
2743 SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_VLTV);
2744 /* Set the descriptor as the vlan input source */
2745 SET_BIT(heth->Instance->MACVIR, ETH_MACVIR_VLTI);
2746
2747 /* if inner VLAN is enabled */
2748 if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_INNERVLANTAG) != 0U)
2749 {
2750 /* Set inner vlan tag value */
2751 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_IVT, (pTxConfig->InnerVlanTag << 16));
2752 /* Set inner vlan tag valid bit */
2753 SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_IVLTV);
2754
2755 /* Set Vlan Tag control */
2756 MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXCDESC_IVTIR, pTxConfig->InnerVlanCtrl);
2757
2758 /* Set the descriptor as the inner vlan input source */
2759 SET_BIT(heth->Instance->MACIVIR, ETH_MACIVIR_VLTI);
2760 /* Enable double VLAN processing */
2761 SET_BIT(heth->Instance->MACVTR, ETH_MACVTR_EDVLP);
2762 }
2763 }
2764
2765 /* if tcp segementation is enabled for this packet */
2766 if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != 0U)
2767 {
2768 /* Set MSS value */
2769 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_MSS, pTxConfig->MaxSegmentSize);
2770 /* Set MSS valid bit */
2771 SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_TCMSSV);
2772 }
2773
2774 if((READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != 0U)|| (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != 0U))
2775 {
2776 /* Set as context descriptor */
2777 SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_CTXT);
2778 /* Set own bit */
2779 SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_OWN);
2780 /* Increment current tx descriptor index */
2781 INCR_TX_DESC_INDEX(descidx, 1U);
2782 /* Get current descriptor address */
2783 dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
2784
2785 descnbr += 1U;
2786
2787 /* Current Tx Descriptor Owned by DMA: cannot be used by the application */
2788 if(READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN)
2789 {
2790 dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[firstdescidx];
2791 /* Clear own bit */
2792 CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_OWN);
2793
2794 return HAL_ETH_ERROR_BUSY;
2795 }
2796 }
2797
2798 /***************************************************************************/
2799 /***************** Normal descriptors configuration *****************/
2800 /***************************************************************************/
2801
2802 descnbr += 1U;
2803
2804 /* Set header or buffer 1 address */
2805 WRITE_REG(dmatxdesc->DESC0, (uint32_t)txbuffer->buffer);
2806 /* Set header or buffer 1 Length */
2807 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B1L, txbuffer->len);
2808
2809 if(txbuffer->next != NULL)
2810 {
2811 txbuffer = txbuffer->next;
2812 /* Set buffer 2 address */
2813 WRITE_REG(dmatxdesc->DESC1, (uint32_t)txbuffer->buffer);
2814 /* Set buffer 2 Length */
2815 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, (txbuffer->len << 16));
2816 }
2817 else
2818 {
2819 WRITE_REG(dmatxdesc->DESC1, 0x0);
2820 /* Set buffer 2 Length */
2821 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U);
2822 }
2823
2824 if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != 0U)
2825 {
2826 /* Set TCP Header length */
2827 MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_THL, (pTxConfig->TCPHeaderLen << 19));
2828 /* Set TCP payload length */
2829 MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TPL, pTxConfig->PayloadLen);
2830 /* Set TCP Segmentation Enabled bit */
2831 SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TSE);
2832 }
2833 else
2834 {
2835 MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FL, pTxConfig->Length);
2836
2837 if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != 0U)
2838 {
2839 MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CIC, pTxConfig->ChecksumCtrl);
2840 }
2841
2842 if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CRCPAD) != 0U)
2843 {
2844 MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CPC, pTxConfig->CRCPadCtrl);
2845 }
2846 }
2847
2848 if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != 0U)
2849 {
2850 /* Set Vlan Tag control */
2851 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_VTIR, pTxConfig->VlanCtrl);
2852 }
2853
2854 /* Mark it as First Descriptor */
2855 SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FD);
2856 /* Mark it as NORMAL descriptor */
2857 CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CTXT);
2858 /* set OWN bit of FIRST descriptor */
2859 SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN);
2860
2861 /* If source address insertion/replacement is enabled for this packet */
2862 if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_SAIC) != 0U)
2863 {
2864 MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_SAIC, pTxConfig->SrcAddrCtrl);
2865 }
2866
2867 /* only if the packet is splitted into more than one descriptors > 1 */
2868 while (txbuffer->next != NULL)
2869 {
2870 /* Clear the LD bit of previous descriptor */
2871 CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_LD);
2872 /* Increment current tx descriptor index */
2873 INCR_TX_DESC_INDEX(descidx, 1U);
2874 /* Get current descriptor address */
2875 dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
2876
2877 /* Clear the FD bit of new Descriptor */
2878 CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FD);
2879
2880 /* Current Tx Descriptor Owned by DMA: cannot be used by the application */
2881 if(READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN) == ETH_DMATXNDESCRF_OWN)
2882 {
2883 descidx = firstdescidx;
2884 dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
2885
2886 /* clear previous desc own bit */
2887 for(idx = 0; idx < descnbr; idx ++)
2888 {
2889 CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN);
2890
2891 /* Increment current tx descriptor index */
2892 INCR_TX_DESC_INDEX(descidx, 1U);
2893 /* Get current descriptor address */
2894 dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
2895 }
2896
2897 return HAL_ETH_ERROR_BUSY;
2898 }
2899
2900 descnbr += 1U;
2901
2902 /* Get the next Tx buffer in the list */
2903 txbuffer = (struct __ETH_BufferTypeDef *)txbuffer->next;
2904
2905 /* Set header or buffer 1 address */
2906 WRITE_REG(dmatxdesc->DESC0, (uint32_t)txbuffer->buffer);
2907 /* Set header or buffer 1 Length */
2908 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B1L, txbuffer->len);
2909
2910 if (txbuffer->next != NULL)
2911 {
2912 /* Get the next Tx buffer in the list */
2913 txbuffer = (struct __ETH_BufferTypeDef *)txbuffer->next;
2914 /* Set buffer 2 address */
2915 WRITE_REG(dmatxdesc->DESC1, (uint32_t)txbuffer->buffer);
2916 /* Set buffer 2 Length */
2917 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, (txbuffer->len << 16));
2918 }
2919 else
2920 {
2921 WRITE_REG(dmatxdesc->DESC1, 0x0);
2922 /* Set buffer 2 Length */
2923 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U);
2924 }
2925
2926 if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != 0U)
2927 {
2928 /* Set TCP payload length */
2929 MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TPL, pTxConfig->PayloadLen);
2930 /* Set TCP Segmentation Enabled bit */
2931 SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TSE);
2932 }
2933 else
2934 {
2935 /* Set the packet length */
2936 MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FL, pTxConfig->Length);
2937
2938 if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != 0U)
2939 {
2940 /* Checksum Insertion Control */
2941 MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CIC, pTxConfig->ChecksumCtrl);
2942 }
2943 }
2944
2945 /* Set Own bit */
2946 SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN);
2947 /* Mark it as NORMAL descriptor */
2948 CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CTXT);
2949 }
2950
2951 if(ItMode != ((uint32_t)RESET))
2952 {
2953 /* Set Interrupt on completition bit */
2954 SET_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_IOC);
2955 }
2956 else
2957 {
2958 /* Clear Interrupt on completition bit */
2959 CLEAR_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_IOC);
2960 }
2961
2962 /* Mark it as LAST descriptor */
2963 SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_LD);
2964
2965 dmatxdesclist->CurTxDesc = descidx;
2966
2967 /* Return function status */
2968 return HAL_ETH_ERROR_NONE;
2969 }
2970
2971 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
2972 static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth)
2973 {
2974 /* Init the ETH Callback settings */
2975 heth->TxCpltCallback = HAL_ETH_TxCpltCallback; /* Legacy weak TxCpltCallback */
2976 heth->RxCpltCallback = HAL_ETH_RxCpltCallback; /* Legacy weak RxCpltCallback */
2977 heth->DMAErrorCallback = HAL_ETH_DMAErrorCallback; /* Legacy weak DMAErrorCallback */
2978 heth->MACErrorCallback = HAL_ETH_MACErrorCallback; /* Legacy weak MACErrorCallback */
2979 heth->PMTCallback = HAL_ETH_PMTCallback; /* Legacy weak PMTCallback */
2980 heth->EEECallback = HAL_ETH_EEECallback; /* Legacy weak EEECallback */
2981 heth->WakeUpCallback = HAL_ETH_WakeUpCallback; /* Legacy weak WakeUpCallback */
2982 }
2983 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
2984
2985
2986 /**
2987 * @}
2988 */
2989
2990 #endif /* ETH */
2991
2992 #endif /* HAL_ETH_MODULE_ENABLED */
2993
2994 /**
2995 * @}
2996 */
2997
2998 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
INAV: Navigation-enabled flight control software