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Set blackbox file handler to NULL after closing file
[inav.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Src / stm32h7xx_ll_spi.c
blob05a6e5e993c035f683f8270a289582b1cd066752
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_spi.c
4 * @author MCD Application Team
5 * @brief SPI LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19 #if defined(USE_FULL_LL_DRIVER)
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32h7xx_ll_spi.h"
23 #include "stm32h7xx_ll_bus.h"
24 #include "stm32h7xx_ll_rcc.h"
25 #ifdef GENERATOR_I2S_PRESENT
26 #include "stm32h7xx_ll_rcc.h"
27 #endif /* GENERATOR_I2S_PRESENT*/
28 #ifdef USE_FULL_ASSERT
29 #include "stm32_assert.h"
30 #else
31 #ifndef assert_param
32 #define assert_param(expr) ((void)0U)
33 #endif
34 #endif
35
36 /** @addtogroup STM32H7xx_LL_Driver
37 * @{
38 */
39
40 #if defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6)
41
42 /** @addtogroup SPI_LL
43 * @{
44 */
45
46 /* Private types -------------------------------------------------------------*/
47 /* Private variables ---------------------------------------------------------*/
48 /* Private constants ---------------------------------------------------------*/
49 /* Private macros ------------------------------------------------------------*/
50 /** @addtogroup SPI_LL_Private_Macros
51 * @{
52 */
53
54 #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
55 || ((__VALUE__) == LL_SPI_MODE_SLAVE))
56
57 #define IS_LL_SPI_SS_IDLENESS(__VALUE__) (((__VALUE__) == LL_SPI_SS_IDLENESS_00CYCLE) \
58 || ((__VALUE__) == LL_SPI_SS_IDLENESS_01CYCLE) \
59 || ((__VALUE__) == LL_SPI_SS_IDLENESS_02CYCLE) \
60 || ((__VALUE__) == LL_SPI_SS_IDLENESS_03CYCLE) \
61 || ((__VALUE__) == LL_SPI_SS_IDLENESS_04CYCLE) \
62 || ((__VALUE__) == LL_SPI_SS_IDLENESS_05CYCLE) \
63 || ((__VALUE__) == LL_SPI_SS_IDLENESS_06CYCLE) \
64 || ((__VALUE__) == LL_SPI_SS_IDLENESS_07CYCLE) \
65 || ((__VALUE__) == LL_SPI_SS_IDLENESS_08CYCLE) \
66 || ((__VALUE__) == LL_SPI_SS_IDLENESS_09CYCLE) \
67 || ((__VALUE__) == LL_SPI_SS_IDLENESS_10CYCLE) \
68 || ((__VALUE__) == LL_SPI_SS_IDLENESS_11CYCLE) \
69 || ((__VALUE__) == LL_SPI_SS_IDLENESS_12CYCLE) \
70 || ((__VALUE__) == LL_SPI_SS_IDLENESS_13CYCLE) \
71 || ((__VALUE__) == LL_SPI_SS_IDLENESS_14CYCLE) \
72 || ((__VALUE__) == LL_SPI_SS_IDLENESS_15CYCLE))
73
74 #define IS_LL_SPI_ID_IDLENESS(__VALUE__) (((__VALUE__) == LL_SPI_ID_IDLENESS_00CYCLE) \
75 || ((__VALUE__) == LL_SPI_ID_IDLENESS_01CYCLE) \
76 || ((__VALUE__) == LL_SPI_ID_IDLENESS_02CYCLE) \
77 || ((__VALUE__) == LL_SPI_ID_IDLENESS_03CYCLE) \
78 || ((__VALUE__) == LL_SPI_ID_IDLENESS_04CYCLE) \
79 || ((__VALUE__) == LL_SPI_ID_IDLENESS_05CYCLE) \
80 || ((__VALUE__) == LL_SPI_ID_IDLENESS_06CYCLE) \
81 || ((__VALUE__) == LL_SPI_ID_IDLENESS_07CYCLE) \
82 || ((__VALUE__) == LL_SPI_ID_IDLENESS_08CYCLE) \
83 || ((__VALUE__) == LL_SPI_ID_IDLENESS_09CYCLE) \
84 || ((__VALUE__) == LL_SPI_ID_IDLENESS_10CYCLE) \
85 || ((__VALUE__) == LL_SPI_ID_IDLENESS_11CYCLE) \
86 || ((__VALUE__) == LL_SPI_ID_IDLENESS_12CYCLE) \
87 || ((__VALUE__) == LL_SPI_ID_IDLENESS_13CYCLE) \
88 || ((__VALUE__) == LL_SPI_ID_IDLENESS_14CYCLE) \
89 || ((__VALUE__) == LL_SPI_ID_IDLENESS_15CYCLE))
90
91 #define IS_LL_SPI_TXCRCINIT_PATTERN(__VALUE__) (((__VALUE__) == LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN) \
92 || ((__VALUE__) == LL_SPI_TXCRCINIT_ALL_ONES_PATTERN))
93
94 #define IS_LL_SPI_RXCRCINIT_PATTERN(__VALUE__) (((__VALUE__) == LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN) \
95 || ((__VALUE__) == LL_SPI_RXCRCINIT_ALL_ONES_PATTERN))
96
97 #define IS_LL_SPI_UDR_CONFIG_REGISTER(__VALUE__) (((__VALUE__) == LL_SPI_UDR_CONFIG_REGISTER_PATTERN) \
98 || ((__VALUE__) == LL_SPI_UDR_CONFIG_LAST_RECEIVED) \
99 || ((__VALUE__) == LL_SPI_UDR_CONFIG_LAST_TRANSMITTED))
100
101 #define IS_LL_SPI_UDR_DETECT_BEGIN_DATA(__VALUE__) (((__VALUE__) == LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME) \
102 || ((__VALUE__) == LL_SPI_UDR_DETECT_END_DATA_FRAME) \
103 || ((__VALUE__) == LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS))
104
105 #define IS_LL_SPI_PROTOCOL(__VALUE__) (((__VALUE__) == LL_SPI_PROTOCOL_MOTOROLA) \
106 || ((__VALUE__) == LL_SPI_PROTOCOL_TI))
107
108 #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
109 || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
110
111 #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
112 || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
113
114 #define IS_LL_SPI_BAUDRATEPRESCALER(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
115 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
116 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
117 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
118 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
119 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
120 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
121 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
122
123 #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
124 || ((__VALUE__) == LL_SPI_MSB_FIRST))
125
126 #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
127 || ((__VALUE__) == LL_SPI_SIMPLEX_TX) \
128 || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
129 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
130 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
131
132 #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) \
133 || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) \
134 || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) \
135 || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) \
136 || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
137 || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) \
138 || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
139 || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
140 || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
141 || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
142 || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
143 || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
144 || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT) \
145 || ((__VALUE__) == LL_SPI_DATAWIDTH_17BIT) \
146 || ((__VALUE__) == LL_SPI_DATAWIDTH_18BIT) \
147 || ((__VALUE__) == LL_SPI_DATAWIDTH_19BIT) \
148 || ((__VALUE__) == LL_SPI_DATAWIDTH_20BIT) \
149 || ((__VALUE__) == LL_SPI_DATAWIDTH_21BIT) \
150 || ((__VALUE__) == LL_SPI_DATAWIDTH_22BIT) \
151 || ((__VALUE__) == LL_SPI_DATAWIDTH_23BIT) \
152 || ((__VALUE__) == LL_SPI_DATAWIDTH_24BIT) \
153 || ((__VALUE__) == LL_SPI_DATAWIDTH_25BIT) \
154 || ((__VALUE__) == LL_SPI_DATAWIDTH_26BIT) \
155 || ((__VALUE__) == LL_SPI_DATAWIDTH_27BIT) \
156 || ((__VALUE__) == LL_SPI_DATAWIDTH_28BIT) \
157 || ((__VALUE__) == LL_SPI_DATAWIDTH_29BIT) \
158 || ((__VALUE__) == LL_SPI_DATAWIDTH_30BIT) \
159 || ((__VALUE__) == LL_SPI_DATAWIDTH_31BIT) \
160 || ((__VALUE__) == LL_SPI_DATAWIDTH_32BIT))
161
162 #define IS_LL_SPI_FIFO_TH(__VALUE__) (((__VALUE__) == LL_SPI_FIFO_TH_01DATA) \
163 || ((__VALUE__) == LL_SPI_FIFO_TH_02DATA) \
164 || ((__VALUE__) == LL_SPI_FIFO_TH_03DATA) \
165 || ((__VALUE__) == LL_SPI_FIFO_TH_04DATA) \
166 || ((__VALUE__) == LL_SPI_FIFO_TH_05DATA) \
167 || ((__VALUE__) == LL_SPI_FIFO_TH_06DATA) \
168 || ((__VALUE__) == LL_SPI_FIFO_TH_07DATA) \
169 || ((__VALUE__) == LL_SPI_FIFO_TH_08DATA) \
170 || ((__VALUE__) == LL_SPI_FIFO_TH_09DATA) \
171 || ((__VALUE__) == LL_SPI_FIFO_TH_10DATA) \
172 || ((__VALUE__) == LL_SPI_FIFO_TH_11DATA) \
173 || ((__VALUE__) == LL_SPI_FIFO_TH_12DATA) \
174 || ((__VALUE__) == LL_SPI_FIFO_TH_13DATA) \
175 || ((__VALUE__) == LL_SPI_FIFO_TH_14DATA) \
176 || ((__VALUE__) == LL_SPI_FIFO_TH_15DATA) \
177 || ((__VALUE__) == LL_SPI_FIFO_TH_16DATA))
178
179 #define IS_LL_SPI_CRC(__VALUE__) (((__VALUE__) == LL_SPI_CRC_4BIT) \
180 || ((__VALUE__) == LL_SPI_CRC_5BIT) \
181 || ((__VALUE__) == LL_SPI_CRC_6BIT) \
182 || ((__VALUE__) == LL_SPI_CRC_7BIT) \
183 || ((__VALUE__) == LL_SPI_CRC_8BIT) \
184 || ((__VALUE__) == LL_SPI_CRC_9BIT) \
185 || ((__VALUE__) == LL_SPI_CRC_10BIT) \
186 || ((__VALUE__) == LL_SPI_CRC_11BIT) \
187 || ((__VALUE__) == LL_SPI_CRC_12BIT) \
188 || ((__VALUE__) == LL_SPI_CRC_13BIT) \
189 || ((__VALUE__) == LL_SPI_CRC_14BIT) \
190 || ((__VALUE__) == LL_SPI_CRC_15BIT) \
191 || ((__VALUE__) == LL_SPI_CRC_16BIT) \
192 || ((__VALUE__) == LL_SPI_CRC_17BIT) \
193 || ((__VALUE__) == LL_SPI_CRC_18BIT) \
194 || ((__VALUE__) == LL_SPI_CRC_19BIT) \
195 || ((__VALUE__) == LL_SPI_CRC_20BIT) \
196 || ((__VALUE__) == LL_SPI_CRC_21BIT) \
197 || ((__VALUE__) == LL_SPI_CRC_22BIT) \
198 || ((__VALUE__) == LL_SPI_CRC_23BIT) \
199 || ((__VALUE__) == LL_SPI_CRC_24BIT) \
200 || ((__VALUE__) == LL_SPI_CRC_25BIT) \
201 || ((__VALUE__) == LL_SPI_CRC_26BIT) \
202 || ((__VALUE__) == LL_SPI_CRC_27BIT) \
203 || ((__VALUE__) == LL_SPI_CRC_28BIT) \
204 || ((__VALUE__) == LL_SPI_CRC_29BIT) \
205 || ((__VALUE__) == LL_SPI_CRC_30BIT) \
206 || ((__VALUE__) == LL_SPI_CRC_31BIT) \
207 || ((__VALUE__) == LL_SPI_CRC_32BIT))
208
209 #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
210 || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
211 || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
212
213 #define IS_LL_SPI_RX_FIFO(__VALUE__) (((__VALUE__) == LL_SPI_RX_FIFO_0PACKET) \
214 || ((__VALUE__) == LL_SPI_RX_FIFO_1PACKET) \
215 || ((__VALUE__) == LL_SPI_RX_FIFO_2PACKET) \
216 || ((__VALUE__) == LL_SPI_RX_FIFO_3PACKET))
217
218 #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
219 || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
220
221 #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1UL)
222
223 /**
224 * @}
225 */
226
227 /* Private function prototypes -----------------------------------------------*/
228
229 /* Exported functions --------------------------------------------------------*/
230 /** @addtogroup SPI_LL_Exported_Functions
231 * @{
232 */
233
234 /** @addtogroup SPI_LL_EF_Init
235 * @{
236 */
237
238 /**
239 * @brief De-initialize the SPI registers to their default reset values.
240 * @param SPIx SPI Instance
241 * @retval An ErrorStatus enumeration value:
242 * - SUCCESS: SPI registers are de-initialized
243 * - ERROR: SPI registers are not de-initialized
244 */
245 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
246 {
247 ErrorStatus status = ERROR;
248
249 /* Check the parameters */
250 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
251
252 #if defined(SPI1)
253 if (SPIx == SPI1)
254 {
255 /* Force reset of SPI clock */
256 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
257
258 /* Release reset of SPI clock */
259 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
260
261 status = SUCCESS;
262 }
263 #endif /* SPI1 */
264 #if defined(SPI2)
265 if (SPIx == SPI2)
266 {
267 /* Force reset of SPI clock */
268 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
269
270 /* Release reset of SPI clock */
271 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
272
273 status = SUCCESS;
274 }
275 #endif /* SPI2 */
276 #if defined(SPI3)
277 if (SPIx == SPI3)
278 {
279 /* Force reset of SPI clock */
280 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
281
282 /* Release reset of SPI clock */
283 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
284
285 status = SUCCESS;
286 }
287 #endif /* SPI3 */
288 #if defined(SPI4)
289 if (SPIx == SPI4)
290 {
291 /* Force reset of SPI clock */
292 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4);
293
294 /* Release reset of SPI clock */
295 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4);
296
297 status = SUCCESS;
298 }
299 #endif /* SPI4 */
300 #if defined(SPI5)
301 if (SPIx == SPI5)
302 {
303 /* Force reset of SPI clock */
304 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI5);
305
306 /* Release reset of SPI clock */
307 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI5);
308
309 status = SUCCESS;
310 }
311 #endif /* SPI5 */
312 #if defined(SPI6)
313 if (SPIx == SPI6)
314 {
315 /* Force reset of SPI clock */
316 LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_SPI6);
317
318 /* Release reset of SPI clock */
319 LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_SPI6);
320
321 status = SUCCESS;
322 }
323 #endif /* SPI6 */
324
325 return status;
326 }
327
328 /**
329 * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
330 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
331 * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
332 * @param SPIx SPI Instance
333 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
334 * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
335 */
336 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
337 {
338 ErrorStatus status = ERROR;
339 uint32_t tmp_nss;
340 uint32_t tmp_mode;
341
342 /* Check the SPI Instance SPIx*/
343 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
344
345 /* Check the SPI parameters from SPI_InitStruct*/
346 assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
347 assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
348 assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
349 assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
350 assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
351 assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
352 assert_param(IS_LL_SPI_BAUDRATEPRESCALER(SPI_InitStruct->BaudRate));
353 assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
354 assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
355
356 if (LL_SPI_IsEnabled(SPIx) == 0x00000000UL)
357 {
358 /*---------------------------- SPIx CFG1 Configuration ------------------------
359 * Configure SPIx CFG1 with parameters:
360 * - Master Baud Rate : SPI_CFG1_MBR[2:0] bits
361 * - CRC Computation Enable : SPI_CFG1_CRCEN bit
362 * - Length of data frame : SPI_CFG1_DSIZE[4:0] bits
363 */
364 MODIFY_REG(SPIx->CFG1, SPI_CFG1_MBR | SPI_CFG1_CRCEN | SPI_CFG1_DSIZE,
365 SPI_InitStruct->BaudRate | SPI_InitStruct->CRCCalculation | SPI_InitStruct->DataWidth);
366
367 tmp_nss = SPI_InitStruct->NSS;
368 tmp_mode = SPI_InitStruct->Mode;
369
370 /* Checks to setup Internal SS signal level and avoid a MODF Error */
371 if ((LL_SPI_GetNSSPolarity(SPIx) == LL_SPI_NSS_POLARITY_LOW) && (tmp_nss == LL_SPI_NSS_SOFT) && (tmp_mode == LL_SPI_MODE_MASTER))
372 {
373 LL_SPI_SetInternalSSLevel(SPIx, LL_SPI_SS_LEVEL_HIGH);
374 }
375
376 /*---------------------------- SPIx CFG2 Configuration ------------------------
377 * Configure SPIx CFG2 with parameters:
378 * - NSS management : SPI_CFG2_SSM, SPI_CFG2_SSOE bits
379 * - ClockPolarity : SPI_CFG2_CPOL bit
380 * - ClockPhase : SPI_CFG2_CPHA bit
381 * - BitOrder : SPI_CFG2_LSBFRST bit
382 * - Master/Slave Mode : SPI_CFG2_MASTER bit
383 * - SPI Mode : SPI_CFG2_COMM[1:0] bits
384 */
385 MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE |
386 SPI_CFG2_CPOL | SPI_CFG2_CPHA |
387 SPI_CFG2_LSBFRST | SPI_CFG2_MASTER | SPI_CFG2_COMM,
388 SPI_InitStruct->NSS | SPI_InitStruct->ClockPolarity |
389 SPI_InitStruct->ClockPhase | SPI_InitStruct->BitOrder |
390 SPI_InitStruct->Mode | (SPI_InitStruct->TransferDirection & SPI_CFG2_COMM));
391
392 /*---------------------------- SPIx CR1 Configuration ------------------------
393 * Configure SPIx CR1 with parameter:
394 * - Half Duplex Direction : SPI_CR1_HDDIR bit
395 */
396 MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, SPI_InitStruct->TransferDirection & SPI_CR1_HDDIR);
397
398 /*---------------------------- SPIx CRCPOLY Configuration ----------------------
399 * Configure SPIx CRCPOLY with parameter:
400 * - CRCPoly : CRCPOLY[31:0] bits
401 */
402 if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
403 {
404 assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
405 LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
406 }
407
408 /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
409 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
410
411 status = SUCCESS;
412 }
413
414 return status;
415 }
416
417 /**
418 * @brief Set each @ref LL_SPI_InitTypeDef field to default value.
419 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
420 * whose fields will be set to default values.
421 * @retval None
422 */
423 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
424 {
425 /* Set SPI_InitStruct fields to default values */
426 SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
427 SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
428 SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
429 SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
430 SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
431 SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
432 SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
433 SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
434 SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
435 SPI_InitStruct->CRCPoly = 7UL;
436 }
437
438 /**
439 * @}
440 */
441
442 /**
443 * @}
444 */
445
446 /**
447 * @}
448 */
449
450 /** @addtogroup I2S_LL
451 * @{
452 */
453
454 /* Private types -------------------------------------------------------------*/
455 /* Private variables ---------------------------------------------------------*/
456 /* Private constants ---------------------------------------------------------*/
457 /** @defgroup I2S_LL_Private_Constants I2S Private Constants
458 * @{
459 */
460 /* I2S registers Masks */
461 #define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
462 SPI_I2SCFGR_DATFMT | SPI_I2SCFGR_CKPOL | \
463 SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_MCKOE | \
464 SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD )
465
466 /**
467 * @}
468 */
469 /* Private macros ------------------------------------------------------------*/
470 /** @defgroup I2S_LL_Private_Macros I2S Private Macros
471 * @{
472 */
473
474 #define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
475 || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
476 || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
477 || ((__VALUE__) == LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED) \
478 || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
479
480 #define IS_LL_I2S_CHANNEL_LENGTH_TYPE (__VALUE__) (((__VALUE__) == LL_I2S_SLAVE_VARIABLE_CH_LENGTH) \
481 || ((__VALUE__) == LL_I2S_SLAVE_FIXED_CH_LENGTH))
482
483 #define IS_LL_I2S_CKPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \
484 || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
485
486 #define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
487 || ((__VALUE__) == LL_I2S_STANDARD_MSB) \
488 || ((__VALUE__) == LL_I2S_STANDARD_LSB) \
489 || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
490 || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
491
492 #define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
493 || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
494 || ((__VALUE__) == LL_I2S_MODE_SLAVE_FULL_DUPLEX) \
495 || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
496 || ((__VALUE__) == LL_I2S_MODE_MASTER_RX) \
497 || ((__VALUE__) == LL_I2S_MODE_MASTER_FULL_DUPLEX))
498
499 #define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
500 || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
501
502 #define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
503 && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
504 || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
505
506 #define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) <= 0xFFUL)
507
508 #define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
509 || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
510
511 #define IS_LL_I2S_FIFO_TH (__VALUE__) (((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_01DATA) \
512 || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_02DATA) \
513 || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_03DATA) \
514 || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_04DATA) \
515 || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_05DATA) \
516 || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_06DATA) \
517 || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_07DATA) \
518 || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_08DATA))
519
520 #define IS_LL_I2S_BIT_ORDER(__VALUE__) (((__VALUE__) == LL_I2S_LSB_FIRST) \
521 || ((__VALUE__) == LL_I2S_MSB_FIRST))
522 /**
523 * @}
524 */
525
526 /* Private function prototypes -----------------------------------------------*/
527
528 /* Exported functions --------------------------------------------------------*/
529 /** @addtogroup I2S_LL_Exported_Functions
530 * @{
531 */
532
533 /** @addtogroup I2S_LL_EF_Init
534 * @{
535 */
536
537 /**
538 * @brief De-initialize the SPI/I2S registers to their default reset values.
539 * @param SPIx SPI Instance
540 * @retval An ErrorStatus enumeration value:
541 * - SUCCESS: SPI registers are de-initialized
542 * - ERROR: SPI registers are not de-initialized
543 */
544 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
545 {
546 return LL_SPI_DeInit(SPIx);
547 }
548
549 /**
550 * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
551 * @note As some bits in I2S configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
552 * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
553 * @note I2S (SPI) source clock must be ready before calling this function. Otherwise will results in wrong programming.
554 * @param SPIx SPI Instance
555 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
556 * @retval An ErrorStatus enumeration value:
557 * - SUCCESS: SPI registers are Initialized
558 * - ERROR: SPI registers are not Initialized
559 */
560 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
561 {
562 uint32_t i2sdiv = 0UL, i2sodd = 0UL, packetlength = 1UL, ispcm = 0UL;
563 uint32_t tmp;
564 uint32_t sourceclock;
565 ErrorStatus status = ERROR;
566
567 /* Check the I2S parameters */
568 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
569 assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
570 assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
571 assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
572 assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
573 assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
574 assert_param(IS_LL_I2S_CKPOL(I2S_InitStruct->ClockPolarity));
575
576 /* Check that SPE bit is set to 0 in order to be sure that SPI/I2S block is disabled.
577 * In this case, it is useless to check if the I2SMOD bit is set to 0 because
578 * this bit I2SMOD only serves to select the desired mode.
579 */
580 if (LL_SPI_IsEnabled(SPIx) == 0x00000000UL)
581 {
582 /*---------------------------- SPIx I2SCFGR Configuration --------------------
583 * Configure SPIx I2SCFGR with parameters:
584 * - Mode : SPI_I2SCFGR_I2SCFG[2:0] bits
585 * - Standard : SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
586 * - DataFormat : SPI_I2SCFGR_CHLEN, SPI_I2SCFGR_DATFMT and SPI_I2SCFGR_DATLEN[1:0] bits
587 * - ClockPolarity : SPI_I2SCFGR_CKPOL bit
588 * - MCLKOutput : SPI_I2SPR_MCKOE bit
589 * - I2S mode : SPI_I2SCFGR_I2SMOD bit
590 */
591
592 /* Write to SPIx I2SCFGR */
593 MODIFY_REG(SPIx->I2SCFGR,
594 I2S_I2SCFGR_CLEAR_MASK,
595 I2S_InitStruct->Mode | I2S_InitStruct->Standard |
596 I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
597 I2S_InitStruct->MCLKOutput | SPI_I2SCFGR_I2SMOD);
598
599 /*---------------------------- SPIx I2SCFGR Configuration ----------------------
600 * Configure SPIx I2SCFGR with parameters:
601 * - AudioFreq : SPI_I2SCFGR_I2SDIV[7:0] and SPI_I2SCFGR_ODD bits
602 */
603
604 /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
605 * else, default values are used: i2sodd = 0U, i2sdiv = 0U.
606 */
607 if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
608 {
609 /* Check the frame length (For the Prescaler computing)
610 * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
611 */
612 if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
613 {
614 /* Packet length is 32 bits */
615 packetlength = 2UL;
616 }
617
618 /* Check if PCM standard is used */
619 if ((I2S_InitStruct->Standard == LL_I2S_STANDARD_PCM_SHORT) ||
620 (I2S_InitStruct->Standard == LL_I2S_STANDARD_PCM_LONG))
621 {
622 ispcm = 1UL;
623 }
624
625 /* Get the I2S (SPI) source clock value */
626 #if defined (SPI_SPI6I2S_SUPPORT)
627 if (SPIx == SPI6)
628 {
629 sourceclock = LL_RCC_GetSPIClockFreq(LL_RCC_SPI6_CLKSOURCE);
630 }
631 else
632 {
633 sourceclock = LL_RCC_GetSPIClockFreq(LL_RCC_SPI123_CLKSOURCE);
634 }
635 #else
636 sourceclock = LL_RCC_GetSPIClockFreq(LL_RCC_SPI123_CLKSOURCE);
637 #endif
638
639 /* Compute the Real divider depending on the MCLK output state with a fixed point */
640 if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
641 {
642 /* MCLK output is enabled */
643 tmp = (((sourceclock / (256UL >> ispcm)) * 16UL) / I2S_InitStruct->AudioFreq) + 8UL;
644 }
645 else
646 {
647 /* MCLK output is disabled */
648 tmp = (((sourceclock / ((32UL >> ispcm) * packetlength)) * 16UL) / I2S_InitStruct->AudioFreq) + 8UL;
649 }
650
651 /* Remove the fixed point */
652 tmp = tmp / 16UL;
653
654 /* Check the parity of the divider */
655 i2sodd = tmp & 0x1UL;
656
657 /* Compute the i2sdiv prescaler */
658 i2sdiv = tmp / 2UL;
659 }
660
661 /* Test if the obtain values are forbiden or out of range */
662 if (((i2sodd == 1UL) && (i2sdiv == 1UL)) || (i2sdiv > 0xFFUL))
663 {
664 /* Set the default values */
665 i2sdiv = 0UL;
666 i2sodd = 0UL;
667 }
668
669 /* Write to SPIx I2SCFGR register the computed value */
670 MODIFY_REG(SPIx->I2SCFGR,
671 SPI_I2SCFGR_ODD | SPI_I2SCFGR_I2SDIV,
672 (i2sodd << SPI_I2SCFGR_ODD_Pos) | (i2sdiv << SPI_I2SCFGR_I2SDIV_Pos));
673
674 status = SUCCESS;
675 }
676
677 return status;
678 }
679
680 /**
681 * @brief Set each @ref LL_I2S_InitTypeDef field to default value.
682 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
683 * whose fields will be set to default values.
684 * @retval None
685 */
686 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
687 {
688 /*--------------- Reset I2S init structure parameters values -----------------*/
689 I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX;
690 I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS;
691 I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B;
692 I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE;
693 I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT;
694 I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW;
695 }
696
697 /**
698 * @brief Set linear and parity prescaler.
699 * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
700 * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
701 * @param SPIx SPI Instance
702 * @param PrescalerLinear Value between Min_Data=0x00 and Max_Data=0xFF
703 * @note PrescalerLinear '1' is not authorized with parity LL_I2S_PRESCALER_PARITY_ODD
704 * @param PrescalerParity This parameter can be one of the following values:
705 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
706 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
707 * @retval None
708 */
709 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
710 {
711 /* Check the I2S parameters */
712 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
713 assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
714 assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
715
716 /* Write to SPIx I2SPR */
717 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SDIV | SPI_I2SCFGR_ODD, (PrescalerLinear << SPI_I2SCFGR_I2SDIV_Pos) |
718 (PrescalerParity << SPI_I2SCFGR_ODD_Pos));
719 }
720
721 /**
722 * @}
723 */
724
725 /**
726 * @}
727 */
728
729 /**
730 * @}
731 */
732
733 #endif /* defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6) */
734
735 /**
736 * @}
737 */
738 #endif /* USE_FULL_LL_DRIVER */
739
740 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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