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kvm: bios: sync tsc on bootup
[kvm-userspace.git] / bios / rombios32.c
blobc83aaf6c0575574cb8b9844d586859c93ad10a59
1 /////////////////////////////////////////////////////////////////////////
2 // $Id: rombios32.c,v 1.11 2007/08/03 13:56:13 vruppert Exp $
3 /////////////////////////////////////////////////////////////////////////
4 //
5 // 32 bit Bochs BIOS init code
6 // Copyright (C) 2006 Fabrice Bellard
7 //
8 // This library is free software; you can redistribute it and/or
9 // modify it under the terms of the GNU Lesser General Public
10 // License as published by the Free Software Foundation; either
11 // version 2 of the License, or (at your option) any later version.
12 //
13 // This library is distributed in the hope that it will be useful,
14 // but WITHOUT ANY WARRANTY; without even the implied warranty of
15 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 // Lesser General Public License for more details.
17 //
18 // You should have received a copy of the GNU Lesser General Public
19 // License along with this library; if not, write to the Free Software
20 // Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <stdarg.h>
22 #include <stddef.h>
23
24 #include "rombios.h"
25
26 typedef signed char int8_t;
27 typedef short int16_t;
28 typedef int int32_t;
29 typedef long long int64_t;
30 typedef unsigned char uint8_t;
31 typedef unsigned short uint16_t;
32 typedef unsigned int uint32_t;
33 typedef unsigned long long uint64_t;
34
35 /* if true, put the MP float table and ACPI RSDT in EBDA and the MP
36 table in RAM. Unfortunately, Linux has bugs with that, so we prefer
37 to modify the BIOS in shadow RAM */
38 //#define BX_USE_EBDA_TABLES
39
40 /* define it if the (emulated) hardware supports SMM mode */
41 #define BX_USE_SMM
42
43 #define cpuid(index, eax, ebx, ecx, edx) \
44 asm volatile ("cpuid" \
45 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) \
46 : "0" (index))
47
48 #define wbinvd() asm volatile("wbinvd")
49
50 #define CPUID_APIC (1 << 9)
51
52 #define APIC_BASE ((uint8_t *)0xfee00000)
53 #define APIC_ICR_LOW 0x300
54 #define APIC_SVR 0x0F0
55 #define APIC_ID 0x020
56 #define APIC_LVT3 0x370
57
58 /* IRQs 5,9,10,11 */
59 #define PCI_ISA_IRQ_MASK 0x0e20U
60
61 #define APIC_ENABLED 0x0100
62
63 #define AP_BOOT_ADDR 0x10000
64
65 #define MPTABLE_MAX_SIZE 0x00002000
66 #define SMI_CMD_IO_ADDR 0xb2
67
68 #define BIOS_TMP_STORAGE 0x00030000 /* 64 KB used to copy the BIOS to shadow RAM */
69
70 static inline void outl(int addr, int val)
71 {
72 asm volatile ("outl %1, %w0" : : "d" (addr), "a" (val));
73 }
74
75 static inline void outw(int addr, int val)
76 {
77 asm volatile ("outw %w1, %w0" : : "d" (addr), "a" (val));
78 }
79
80 static inline void outb(int addr, int val)
81 {
82 asm volatile ("outb %b1, %w0" : : "d" (addr), "a" (val));
83 }
84
85 static inline uint32_t inl(int addr)
86 {
87 uint32_t val;
88 asm volatile ("inl %w1, %0" : "=a" (val) : "d" (addr));
89 return val;
90 }
91
92 static inline uint16_t inw(int addr)
93 {
94 uint16_t val;
95 asm volatile ("inw %w1, %w0" : "=a" (val) : "d" (addr));
96 return val;
97 }
98
99 static inline uint8_t inb(int addr)
100 {
101 uint8_t val;
102 asm volatile ("inb %w1, %b0" : "=a" (val) : "d" (addr));
103 return val;
104 }
105
106 static inline void writel(void *addr, uint32_t val)
107 {
108 *(volatile uint32_t *)addr = val;
109 }
110
111 static inline void writew(void *addr, uint16_t val)
112 {
113 *(volatile uint16_t *)addr = val;
114 }
115
116 static inline void writeb(void *addr, uint8_t val)
117 {
118 *(volatile uint8_t *)addr = val;
119 }
120
121 static inline uint32_t readl(const void *addr)
122 {
123 return *(volatile const uint32_t *)addr;
124 }
125
126 static inline uint16_t readw(const void *addr)
127 {
128 return *(volatile const uint16_t *)addr;
129 }
130
131 static inline uint8_t readb(const void *addr)
132 {
133 return *(volatile const uint8_t *)addr;
134 }
135
136 static inline void putc(int c)
137 {
138 outb(INFO_PORT, c);
139 }
140
141 static inline int isdigit(int c)
142 {
143 return c >= '0' && c <= '9';
144 }
145
146 void *memset(void *d1, int val, size_t len)
147 {
148 uint8_t *d = d1;
149
150 while (len--) {
151 *d++ = val;
152 }
153 return d1;
154 }
155
156 void *memcpy(void *d1, const void *s1, size_t len)
157 {
158 uint8_t *d = d1;
159 const uint8_t *s = s1;
160
161 while (len--) {
162 *d++ = *s++;
163 }
164 return d1;
165 }
166
167 void *memmove(void *d1, const void *s1, size_t len)
168 {
169 uint8_t *d = d1;
170 const uint8_t *s = s1;
171
172 if (d <= s) {
173 while (len--) {
174 *d++ = *s++;
175 }
176 } else {
177 d += len;
178 s += len;
179 while (len--) {
180 *--d = *--s;
181 }
182 }
183 return d1;
184 }
185
186 size_t strlen(const char *s)
187 {
188 const char *s1;
189 for(s1 = s; *s1 != '\0'; s1++);
190 return s1 - s;
191 }
192
193 /* from BSD ppp sources */
194 int vsnprintf(char *buf, int buflen, const char *fmt, va_list args)
195 {
196 int c, i, n;
197 int width, prec, fillch;
198 int base, len, neg;
199 unsigned long val = 0;
200 const char *f;
201 char *str, *buf0;
202 char num[32];
203 static const char hexchars[] = "0123456789abcdef";
204
205 buf0 = buf;
206 --buflen;
207 while (buflen > 0) {
208 for (f = fmt; *f != '%' && *f != 0; ++f)
209 ;
210 if (f > fmt) {
211 len = f - fmt;
212 if (len > buflen)
213 len = buflen;
214 memcpy(buf, fmt, len);
215 buf += len;
216 buflen -= len;
217 fmt = f;
218 }
219 if (*fmt == 0)
220 break;
221 c = *++fmt;
222 width = prec = 0;
223 fillch = ' ';
224 if (c == '0') {
225 fillch = '0';
226 c = *++fmt;
227 }
228 if (c == '*') {
229 width = va_arg(args, int);
230 c = *++fmt;
231 } else {
232 while (isdigit(c)) {
233 width = width * 10 + c - '0';
234 c = *++fmt;
235 }
236 }
237 if (c == '.') {
238 c = *++fmt;
239 if (c == '*') {
240 prec = va_arg(args, int);
241 c = *++fmt;
242 } else {
243 while (isdigit(c)) {
244 prec = prec * 10 + c - '0';
245 c = *++fmt;
246 }
247 }
248 }
249 /* modifiers */
250 switch(c) {
251 case 'l':
252 c = *++fmt;
253 break;
254 default:
255 break;
256 }
257 str = 0;
258 base = 0;
259 neg = 0;
260 ++fmt;
261 switch (c) {
262 case 'd':
263 i = va_arg(args, int);
264 if (i < 0) {
265 neg = 1;
266 val = -i;
267 } else
268 val = i;
269 base = 10;
270 break;
271 case 'o':
272 val = va_arg(args, unsigned int);
273 base = 8;
274 break;
275 case 'x':
276 case 'X':
277 val = va_arg(args, unsigned int);
278 base = 16;
279 break;
280 case 'p':
281 val = (unsigned long) va_arg(args, void *);
282 base = 16;
283 neg = 2;
284 break;
285 case 's':
286 str = va_arg(args, char *);
287 break;
288 case 'c':
289 num[0] = va_arg(args, int);
290 num[1] = 0;
291 str = num;
292 break;
293 default:
294 *buf++ = '%';
295 if (c != '%')
296 --fmt; /* so %z outputs %z etc. */
297 --buflen;
298 continue;
299 }
300 if (base != 0) {
301 str = num + sizeof(num);
302 *--str = 0;
303 while (str > num + neg) {
304 *--str = hexchars[val % base];
305 val = val / base;
306 if (--prec <= 0 && val == 0)
307 break;
308 }
309 switch (neg) {
310 case 1:
311 *--str = '-';
312 break;
313 case 2:
314 *--str = 'x';
315 *--str = '0';
316 break;
317 }
318 len = num + sizeof(num) - 1 - str;
319 } else {
320 len = strlen(str);
321 if (prec > 0 && len > prec)
322 len = prec;
323 }
324 if (width > 0) {
325 if (width > buflen)
326 width = buflen;
327 if ((n = width - len) > 0) {
328 buflen -= n;
329 for (; n > 0; --n)
330 *buf++ = fillch;
331 }
332 }
333 if (len > buflen)
334 len = buflen;
335 memcpy(buf, str, len);
336 buf += len;
337 buflen -= len;
338 }
339 *buf = 0;
340 return buf - buf0;
341 }
342
343 void bios_printf(int flags, const char *fmt, ...)
344 {
345 va_list ap;
346 char buf[1024];
347 const char *s;
348
349 va_start(ap, fmt);
350 vsnprintf(buf, sizeof(buf), fmt, ap);
351 s = buf;
352 while (*s)
353 putc(*s++);
354 va_end(ap);
355 }
356
357 void delay_ms(int n)
358 {
359 int i, j;
360 for(i = 0; i < n; i++) {
361 #ifdef BX_QEMU
362 /* approximative ! */
363 for(j = 0; j < 1000000; j++);
364 #else
365 {
366 int r1, r2;
367 j = 66;
368 r1 = inb(0x61) & 0x10;
369 do {
370 r2 = inb(0x61) & 0x10;
371 if (r1 != r2) {
372 j--;
373 r1 = r2;
374 }
375 } while (j > 0);
376 }
377 #endif
378 }
379 }
380
381 int smp_cpus;
382 uint32_t cpuid_features;
383 uint32_t cpuid_ext_features;
384 unsigned long ram_size;
385 #ifdef BX_USE_EBDA_TABLES
386 unsigned long ebda_cur_addr;
387 #endif
388 int acpi_enabled;
389 uint32_t pm_io_base, smb_io_base;
390 int pm_sci_int;
391 unsigned long bios_table_cur_addr;
392 unsigned long bios_table_end_addr;
393
394 void cpu_probe(void)
395 {
396 uint32_t eax, ebx, ecx, edx;
397 cpuid(1, eax, ebx, ecx, edx);
398 cpuid_features = edx;
399 cpuid_ext_features = ecx;
400 }
401
402 static int cmos_readb(int addr)
403 {
404 outb(0x70, addr);
405 return inb(0x71);
406 }
407
408 void ram_probe(void)
409 {
410 ram_size = (cmos_readb(0x34) | (cmos_readb(0x35) << 8)) * 65536 +
411 16 * 1024 * 1024;
412 #ifdef BX_USE_EBDA_TABLES
413 ebda_cur_addr = ((*(uint16_t *)(0x40e)) << 4) + 0x380;
414 #endif
415 BX_INFO("ram_size=0x%08lx\n");
416 }
417
418 /****************************************************/
419 /* SMP probe */
420
421 extern uint8_t smp_ap_boot_code_start;
422 extern uint8_t smp_ap_boot_code_end;
423
424 /* find the number of CPUs by launching a SIPI to them */
425 void smp_probe(void)
426 {
427 uint32_t val, sipi_vector;
428
429 smp_cpus = 1;
430 if (cpuid_features & CPUID_APIC) {
431
432 /* enable local APIC */
433 val = readl(APIC_BASE + APIC_SVR);
434 val |= APIC_ENABLED;
435 writel(APIC_BASE + APIC_SVR, val);
436
437 writew((void *)CPU_COUNT_ADDR, 1);
438 /* copy AP boot code */
439 memcpy((void *)AP_BOOT_ADDR, &smp_ap_boot_code_start,
440 &smp_ap_boot_code_end - &smp_ap_boot_code_start);
441
442 /* broadcast SIPI */
443 writel(APIC_BASE + APIC_ICR_LOW, 0x000C4500);
444 sipi_vector = AP_BOOT_ADDR >> 12;
445 writel(APIC_BASE + APIC_ICR_LOW, 0x000C4600 | sipi_vector);
446 asm volatile(
447 "xor %%eax, %%eax \n\t"
448 "xor %%edx, %%edx \n\t"
449 "mov $0x10, %%ecx \n\t"
450 "wrmsr"
451 : : : "eax", "ecx", "edx");
452
453 #ifndef BX_QEMU
454 delay_ms(10);
455 #else
456 while (cmos_readb(0x5f) + 1 != readw((void *)CPU_COUNT_ADDR))
457 ;
458 #endif
459
460 smp_cpus = readw((void *)CPU_COUNT_ADDR);
461 }
462 BX_INFO("Found %d cpu(s)\n", smp_cpus);
463 }
464
465 /****************************************************/
466 /* PCI init */
467
468 #define PCI_ADDRESS_SPACE_MEM 0x00
469 #define PCI_ADDRESS_SPACE_IO 0x01
470 #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
471
472 #define PCI_ROM_SLOT 6
473 #define PCI_NUM_REGIONS 7
474
475 #define PCI_DEVICES_MAX 64
476
477 #define PCI_VENDOR_ID 0x00 /* 16 bits */
478 #define PCI_DEVICE_ID 0x02 /* 16 bits */
479 #define PCI_COMMAND 0x04 /* 16 bits */
480 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
481 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
482 #define PCI_CLASS_DEVICE 0x0a /* Device class */
483 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
484 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
485 #define PCI_MIN_GNT 0x3e /* 8 bits */
486 #define PCI_MAX_LAT 0x3f /* 8 bits */
487
488 typedef struct PCIDevice {
489 int bus;
490 int devfn;
491 } PCIDevice;
492
493 static uint32_t pci_bios_io_addr;
494 static uint32_t pci_bios_mem_addr;
495 static uint32_t pci_bios_bigmem_addr;
496 /* host irqs corresponding to PCI irqs A-D */
497 static uint8_t pci_irqs[4] = { 10, 10, 11, 11 };
498 static PCIDevice i440_pcidev;
499
500 static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val)
501 {
502 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
503 outl(0xcfc, val);
504 }
505
506 static void pci_config_writew(PCIDevice *d, uint32_t addr, uint32_t val)
507 {
508 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
509 outw(0xcfc + (addr & 2), val);
510 }
511
512 static void pci_config_writeb(PCIDevice *d, uint32_t addr, uint32_t val)
513 {
514 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
515 outb(0xcfc + (addr & 3), val);
516 }
517
518 static uint32_t pci_config_readl(PCIDevice *d, uint32_t addr)
519 {
520 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
521 return inl(0xcfc);
522 }
523
524 static uint32_t pci_config_readw(PCIDevice *d, uint32_t addr)
525 {
526 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
527 return inw(0xcfc + (addr & 2));
528 }
529
530 static uint32_t pci_config_readb(PCIDevice *d, uint32_t addr)
531 {
532 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
533 return inb(0xcfc + (addr & 3));
534 }
535
536 static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr)
537 {
538 uint16_t cmd;
539 uint32_t ofs, old_addr;
540
541 if ( region_num == PCI_ROM_SLOT ) {
542 ofs = 0x30;
543 }else{
544 ofs = 0x10 + region_num * 4;
545 }
546
547 old_addr = pci_config_readl(d, ofs);
548
549 pci_config_writel(d, ofs, addr);
550 BX_INFO("region %d: 0x%08x\n", region_num, addr);
551
552 /* enable memory mappings */
553 cmd = pci_config_readw(d, PCI_COMMAND);
554 if ( region_num == PCI_ROM_SLOT )
555 cmd |= 2;
556 else if (old_addr & PCI_ADDRESS_SPACE_IO)
557 cmd |= 1;
558 else
559 cmd |= 2;
560 pci_config_writew(d, PCI_COMMAND, cmd);
561 }
562
563 /* return the global irq number corresponding to a given device irq
564 pin. We could also use the bus number to have a more precise
565 mapping. */
566 static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
567 {
568 int slot_addend;
569 slot_addend = (pci_dev->devfn >> 3) - 1;
570 return (irq_num + slot_addend) & 3;
571 }
572
573 static int find_bios_table_area(void)
574 {
575 unsigned long addr;
576 for(addr = 0xf0000; addr < 0x100000; addr += 16) {
577 if (*(uint32_t *)addr == 0xaafb4442) {
578 bios_table_cur_addr = addr + 8;
579 bios_table_end_addr = bios_table_cur_addr + *(uint32_t *)(addr + 4);
580 BX_INFO("bios_table_addr: 0x%08lx end=0x%08lx\n",
581 bios_table_cur_addr, bios_table_end_addr);
582 return 0;
583 }
584 }
585 return -1;
586 }
587
588 static void bios_shadow_init(PCIDevice *d)
589 {
590 int v;
591
592 if (find_bios_table_area() < 0)
593 return;
594
595 /* remap the BIOS to shadow RAM an keep it read/write while we
596 are writing tables */
597 memcpy((void *)BIOS_TMP_STORAGE, (void *)0x000f0000, 0x10000);
598 v = pci_config_readb(d, 0x59);
599 v = (v & 0x0f) | (0x30);
600 pci_config_writeb(d, 0x59, v);
601 memcpy((void *)0x000f0000, (void *)BIOS_TMP_STORAGE, 0x10000);
602
603 i440_pcidev = *d;
604 }
605
606 static void bios_lock_shadow_ram(void)
607 {
608 PCIDevice *d = &i440_pcidev;
609 int v;
610
611 wbinvd();
612 v = pci_config_readb(d, 0x59);
613 v = (v & 0x0f) | (0x10);
614 pci_config_writeb(d, 0x59, v);
615 }
616
617 static void pci_bios_init_bridges(PCIDevice *d)
618 {
619 uint16_t vendor_id, device_id;
620
621 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
622 device_id = pci_config_readw(d, PCI_DEVICE_ID);
623
624 if (vendor_id == 0x8086 && device_id == 0x7000) {
625 int i, irq;
626 uint8_t elcr[2];
627
628 /* PIIX3 bridge */
629
630 elcr[0] = 0x00;
631 elcr[1] = 0x00;
632 for(i = 0; i < 4; i++) {
633 irq = pci_irqs[i];
634 /* set to trigger level */
635 elcr[irq >> 3] |= (1 << (irq & 7));
636 /* activate irq remapping in PIIX */
637 pci_config_writeb(d, 0x60 + i, irq);
638 }
639 outb(0x4d0, elcr[0]);
640 outb(0x4d1, elcr[1]);
641 BX_INFO("PIIX3 init: elcr=%02x %02x\n",
642 elcr[0], elcr[1]);
643 } else if (vendor_id == 0x8086 && device_id == 0x1237) {
644 /* i440 PCI bridge */
645 bios_shadow_init(d);
646 }
647 }
648
649 extern uint8_t smm_relocation_start, smm_relocation_end;
650 extern uint8_t smm_code_start, smm_code_end;
651
652 #ifdef BX_USE_SMM
653 static void smm_init(PCIDevice *d)
654 {
655 /* copy the SMM relocation code */
656 memcpy((void *)0x38000, &smm_relocation_start,
657 &smm_relocation_end - &smm_relocation_start);
658
659 /* enable SMI generation when writing to the APMC register */
660 pci_config_writel(d, 0x58, pci_config_readl(d, 0x58) | (1 << 25));
661
662 /* init APM status port */
663 outb(0xb3, 0x01);
664
665 /* raise an SMI interrupt */
666 outb(0xb2, 0x00);
667
668 /* wait until SMM code executed */
669 while (inb(0xb3) != 0x00);
670
671 /* enable the SMM memory window */
672 pci_config_writeb(&i440_pcidev, 0x72, 0x02 | 0x48);
673
674 /* copy the SMM code */
675 memcpy((void *)0xa8000, &smm_code_start,
676 &smm_code_end - &smm_code_start);
677 wbinvd();
678
679 /* close the SMM memory window and enable normal SMM */
680 pci_config_writeb(&i440_pcidev, 0x72, 0x02 | 0x08);
681 }
682 #endif
683
684 static void pci_bios_init_device(PCIDevice *d)
685 {
686 int class;
687 uint32_t *paddr;
688 int i, pin, pic_irq, vendor_id, device_id;
689
690 class = pci_config_readw(d, PCI_CLASS_DEVICE);
691 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
692 device_id = pci_config_readw(d, PCI_DEVICE_ID);
693 BX_INFO("PCI: bus=%d devfn=0x%02x: vendor_id=0x%04x device_id=0x%04x\n",
694 d->bus, d->devfn, vendor_id, device_id);
695 switch(class) {
696 case 0x0101:
697 if (vendor_id == 0x8086 && device_id == 0x7010) {
698 /* PIIX3 IDE */
699 pci_config_writew(d, 0x40, 0x8000); // enable IDE0
700 pci_config_writew(d, 0x42, 0x8000); // enable IDE1
701 goto default_map;
702 } else {
703 /* IDE: we map it as in ISA mode */
704 pci_set_io_region_addr(d, 0, 0x1f0);
705 pci_set_io_region_addr(d, 1, 0x3f4);
706 pci_set_io_region_addr(d, 2, 0x170);
707 pci_set_io_region_addr(d, 3, 0x374);
708 }
709 break;
710 case 0x0300:
711 if (vendor_id != 0x1234)
712 goto default_map;
713 /* VGA: map frame buffer to default Bochs VBE address */
714 pci_set_io_region_addr(d, 0, 0xE0000000);
715 break;
716 case 0x0800:
717 /* PIC */
718 if (vendor_id == 0x1014) {
719 /* IBM */
720 if (device_id == 0x0046 || device_id == 0xFFFF) {
721 /* MPIC & MPIC2 */
722 pci_set_io_region_addr(d, 0, 0x80800000 + 0x00040000);
723 }
724 }
725 break;
726 case 0xff00:
727 if (vendor_id == 0x0106b &&
728 (device_id == 0x0017 || device_id == 0x0022)) {
729 /* macio bridge */
730 pci_set_io_region_addr(d, 0, 0x80800000);
731 }
732 break;
733 default:
734 default_map:
735 /* default memory mappings */
736 for(i = 0; i < PCI_NUM_REGIONS; i++) {
737 int ofs;
738 uint32_t val, size ;
739
740 if (i == PCI_ROM_SLOT)
741 ofs = 0x30;
742 else
743 ofs = 0x10 + i * 4;
744 pci_config_writel(d, ofs, 0xffffffff);
745 val = pci_config_readl(d, ofs);
746 if (val != 0) {
747 size = (~(val & ~0xf)) + 1;
748 if (val & PCI_ADDRESS_SPACE_IO)
749 paddr = &pci_bios_io_addr;
750 else if (size >= 0x04000000)
751 paddr = &pci_bios_bigmem_addr;
752 else
753 paddr = &pci_bios_mem_addr;
754 *paddr = (*paddr + size - 1) & ~(size - 1);
755 pci_set_io_region_addr(d, i, *paddr);
756 *paddr += size;
757 }
758 }
759 break;
760 }
761
762 /* map the interrupt */
763 pin = pci_config_readb(d, PCI_INTERRUPT_PIN);
764 if (pin != 0) {
765 pin = pci_slot_get_pirq(d, pin - 1);
766 pic_irq = pci_irqs[pin];
767 pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq);
768 }
769
770 if (vendor_id == 0x8086 && device_id == 0x7113) {
771 /* PIIX4 Power Management device (for ACPI) */
772 pm_io_base = PM_IO_BASE;
773 pci_config_writel(d, 0x40, pm_io_base | 1);
774 pci_config_writeb(d, 0x80, 0x01); /* enable PM io space */
775 smb_io_base = SMB_IO_BASE;
776 pci_config_writel(d, 0x90, smb_io_base | 1);
777 pci_config_writeb(d, 0xd2, 0x09); /* enable SMBus io space */
778 pm_sci_int = pci_config_readb(d, PCI_INTERRUPT_LINE);
779 #ifdef BX_USE_SMM
780 smm_init(d);
781 #endif
782 acpi_enabled = 1;
783 }
784 }
785
786 void pci_for_each_device(void (*init_func)(PCIDevice *d))
787 {
788 PCIDevice d1, *d = &d1;
789 int bus, devfn;
790 uint16_t vendor_id, device_id;
791
792 for(bus = 0; bus < 1; bus++) {
793 for(devfn = 0; devfn < 256; devfn++) {
794 d->bus = bus;
795 d->devfn = devfn;
796 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
797 device_id = pci_config_readw(d, PCI_DEVICE_ID);
798 if (vendor_id != 0xffff || device_id != 0xffff) {
799 init_func(d);
800 }
801 }
802 }
803 }
804
805 void pci_bios_init(void)
806 {
807 pci_bios_io_addr = 0xc000;
808 pci_bios_mem_addr = 0xf0000000;
809 pci_bios_bigmem_addr = ram_size;
810 if (pci_bios_bigmem_addr < 0x90000000)
811 pci_bios_bigmem_addr = 0x90000000;
812
813 pci_for_each_device(pci_bios_init_bridges);
814
815 pci_for_each_device(pci_bios_init_device);
816 }
817
818 /****************************************************/
819 /* Multi Processor table init */
820
821 static void putb(uint8_t **pp, int val)
822 {
823 uint8_t *q;
824 q = *pp;
825 *q++ = val;
826 *pp = q;
827 }
828
829 static void putstr(uint8_t **pp, const char *str)
830 {
831 uint8_t *q;
832 q = *pp;
833 while (*str)
834 *q++ = *str++;
835 *pp = q;
836 }
837
838 static void putle16(uint8_t **pp, int val)
839 {
840 uint8_t *q;
841 q = *pp;
842 *q++ = val;
843 *q++ = val >> 8;
844 *pp = q;
845 }
846
847 static void putle32(uint8_t **pp, int val)
848 {
849 uint8_t *q;
850 q = *pp;
851 *q++ = val;
852 *q++ = val >> 8;
853 *q++ = val >> 16;
854 *q++ = val >> 24;
855 *pp = q;
856 }
857
858 static int mpf_checksum(const uint8_t *data, int len)
859 {
860 int sum, i;
861 sum = 0;
862 for(i = 0; i < len; i++)
863 sum += data[i];
864 return sum & 0xff;
865 }
866
867 static unsigned long align(unsigned long addr, unsigned long v)
868 {
869 return (addr + v - 1) & ~(v - 1);
870 }
871
872 static void mptable_init(void)
873 {
874 uint8_t *mp_config_table, *q, *float_pointer_struct;
875 int ioapic_id, i, len;
876 int mp_config_table_size;
877
878 #ifdef BX_QEMU
879 if (smp_cpus <= 1)
880 return;
881 #endif
882
883 #ifdef BX_USE_EBDA_TABLES
884 mp_config_table = (uint8_t *)(ram_size - ACPI_DATA_SIZE - MPTABLE_MAX_SIZE);
885 #else
886 bios_table_cur_addr = align(bios_table_cur_addr, 16);
887 mp_config_table = (uint8_t *)bios_table_cur_addr;
888 #endif
889 q = mp_config_table;
890 putstr(&q, "PCMP"); /* "PCMP signature */
891 putle16(&q, 0); /* table length (patched later) */
892 putb(&q, 4); /* spec rev */
893 putb(&q, 0); /* checksum (patched later) */
894 #ifdef BX_QEMU
895 putstr(&q, "QEMUCPU "); /* OEM id */
896 #else
897 putstr(&q, "BOCHSCPU");
898 #endif
899 putstr(&q, "0.1 "); /* vendor id */
900 putle32(&q, 0); /* OEM table ptr */
901 putle16(&q, 0); /* OEM table size */
902 putle16(&q, smp_cpus + 18); /* entry count */
903 putle32(&q, 0xfee00000); /* local APIC addr */
904 putle16(&q, 0); /* ext table length */
905 putb(&q, 0); /* ext table checksum */
906 putb(&q, 0); /* reserved */
907
908 for(i = 0; i < smp_cpus; i++) {
909 putb(&q, 0); /* entry type = processor */
910 putb(&q, i); /* APIC id */
911 putb(&q, 0x11); /* local APIC version number */
912 if (i == 0)
913 putb(&q, 3); /* cpu flags: enabled, bootstrap cpu */
914 else
915 putb(&q, 1); /* cpu flags: enabled */
916 putb(&q, 0); /* cpu signature */
917 putb(&q, 6);
918 putb(&q, 0);
919 putb(&q, 0);
920 putle16(&q, 0x201); /* feature flags */
921 putle16(&q, 0);
922
923 putle16(&q, 0); /* reserved */
924 putle16(&q, 0);
925 putle16(&q, 0);
926 putle16(&q, 0);
927 }
928
929 /* isa bus */
930 putb(&q, 1); /* entry type = bus */
931 putb(&q, 0); /* bus ID */
932 putstr(&q, "ISA ");
933
934 /* ioapic */
935 ioapic_id = smp_cpus;
936 putb(&q, 2); /* entry type = I/O APIC */
937 putb(&q, ioapic_id); /* apic ID */
938 putb(&q, 0x11); /* I/O APIC version number */
939 putb(&q, 1); /* enable */
940 putle32(&q, 0xfec00000); /* I/O APIC addr */
941
942 /* irqs */
943 for(i = 0; i < 16; i++) {
944 putb(&q, 3); /* entry type = I/O interrupt */
945 putb(&q, 0); /* interrupt type = vectored interrupt */
946 putb(&q, 0); /* flags: po=0, el=0 */
947 putb(&q, 0);
948 putb(&q, 0); /* source bus ID = ISA */
949 putb(&q, i); /* source bus IRQ */
950 putb(&q, ioapic_id); /* dest I/O APIC ID */
951 putb(&q, i); /* dest I/O APIC interrupt in */
952 }
953 /* patch length */
954 len = q - mp_config_table;
955 mp_config_table[4] = len;
956 mp_config_table[5] = len >> 8;
957
958 mp_config_table[7] = -mpf_checksum(mp_config_table, q - mp_config_table);
959
960 mp_config_table_size = q - mp_config_table;
961
962 #ifndef BX_USE_EBDA_TABLES
963 bios_table_cur_addr += mp_config_table_size;
964 #endif
965
966 /* floating pointer structure */
967 #ifdef BX_USE_EBDA_TABLES
968 ebda_cur_addr = align(ebda_cur_addr, 16);
969 float_pointer_struct = (uint8_t *)ebda_cur_addr;
970 #else
971 bios_table_cur_addr = align(bios_table_cur_addr, 16);
972 float_pointer_struct = (uint8_t *)bios_table_cur_addr;
973 #endif
974 q = float_pointer_struct;
975 putstr(&q, "_MP_");
976 /* pointer to MP config table */
977 putle32(&q, (unsigned long)mp_config_table);
978
979 putb(&q, 1); /* length in 16 byte units */
980 putb(&q, 4); /* MP spec revision */
981 putb(&q, 0); /* checksum (patched later) */
982 putb(&q, 0); /* MP feature byte 1 */
983
984 putb(&q, 0);
985 putb(&q, 0);
986 putb(&q, 0);
987 putb(&q, 0);
988 float_pointer_struct[10] =
989 -mpf_checksum(float_pointer_struct, q - float_pointer_struct);
990 #ifdef BX_USE_EBDA_TABLES
991 ebda_cur_addr += (q - float_pointer_struct);
992 #else
993 bios_table_cur_addr += (q - float_pointer_struct);
994 #endif
995 BX_INFO("MP table addr=0x%08lx MPC table addr=0x%08lx size=0x%x\n",
996 (unsigned long)float_pointer_struct,
997 (unsigned long)mp_config_table,
998 mp_config_table_size);
999 }
1000
1001 /****************************************************/
1002 /* ACPI tables init */
1003
1004 /* Table structure from Linux kernel (the ACPI tables are under the
1005 BSD license) */
1006
1007 #define ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \
1008 uint8_t signature [4]; /* ACPI signature (4 ASCII characters) */\
1009 uint32_t length; /* Length of table, in bytes, including header */\
1010 uint8_t revision; /* ACPI Specification minor version # */\
1011 uint8_t checksum; /* To make sum of entire table == 0 */\
1012 uint8_t oem_id [6]; /* OEM identification */\
1013 uint8_t oem_table_id [8]; /* OEM table identification */\
1014 uint32_t oem_revision; /* OEM revision number */\
1015 uint8_t asl_compiler_id [4]; /* ASL compiler vendor ID */\
1016 uint32_t asl_compiler_revision; /* ASL compiler revision number */
1017
1018
1019 struct acpi_table_header /* ACPI common table header */
1020 {
1021 ACPI_TABLE_HEADER_DEF
1022 };
1023
1024 struct rsdp_descriptor /* Root System Descriptor Pointer */
1025 {
1026 uint8_t signature [8]; /* ACPI signature, contains "RSD PTR " */
1027 uint8_t checksum; /* To make sum of struct == 0 */
1028 uint8_t oem_id [6]; /* OEM identification */
1029 uint8_t revision; /* Must be 0 for 1.0, 2 for 2.0 */
1030 uint32_t rsdt_physical_address; /* 32-bit physical address of RSDT */
1031 uint32_t length; /* XSDT Length in bytes including hdr */
1032 uint64_t xsdt_physical_address; /* 64-bit physical address of XSDT */
1033 uint8_t extended_checksum; /* Checksum of entire table */
1034 uint8_t reserved [3]; /* Reserved field must be 0 */
1035 };
1036
1037 /*
1038 * ACPI 1.0 Root System Description Table (RSDT)
1039 */
1040 struct rsdt_descriptor_rev1
1041 {
1042 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
1043 uint32_t table_offset_entry [2]; /* Array of pointers to other */
1044 /* ACPI tables */
1045 };
1046
1047 /*
1048 * ACPI 1.0 Firmware ACPI Control Structure (FACS)
1049 */
1050 struct facs_descriptor_rev1
1051 {
1052 uint8_t signature[4]; /* ACPI Signature */
1053 uint32_t length; /* Length of structure, in bytes */
1054 uint32_t hardware_signature; /* Hardware configuration signature */
1055 uint32_t firmware_waking_vector; /* ACPI OS waking vector */
1056 uint32_t global_lock; /* Global Lock */
1057 uint32_t S4bios_f : 1; /* Indicates if S4BIOS support is present */
1058 uint32_t reserved1 : 31; /* Must be 0 */
1059 uint8_t resverved3 [40]; /* Reserved - must be zero */
1060 };
1061
1062
1063 /*
1064 * ACPI 1.0 Fixed ACPI Description Table (FADT)
1065 */
1066 struct fadt_descriptor_rev1
1067 {
1068 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
1069 uint32_t firmware_ctrl; /* Physical address of FACS */
1070 uint32_t dsdt; /* Physical address of DSDT */
1071 uint8_t model; /* System Interrupt Model */
1072 uint8_t reserved1; /* Reserved */
1073 uint16_t sci_int; /* System vector of SCI interrupt */
1074 uint32_t smi_cmd; /* Port address of SMI command port */
1075 uint8_t acpi_enable; /* Value to write to smi_cmd to enable ACPI */
1076 uint8_t acpi_disable; /* Value to write to smi_cmd to disable ACPI */
1077 uint8_t S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */
1078 uint8_t reserved2; /* Reserved - must be zero */
1079 uint32_t pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */
1080 uint32_t pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */
1081 uint32_t pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */
1082 uint32_t pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */
1083 uint32_t pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */
1084 uint32_t pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
1085 uint32_t gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */
1086 uint32_t gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */
1087 uint8_t pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */
1088 uint8_t pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */
1089 uint8_t pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */
1090 uint8_t pm_tmr_len; /* Byte Length of ports at pm_tm_blk */
1091 uint8_t gpe0_blk_len; /* Byte Length of ports at gpe0_blk */
1092 uint8_t gpe1_blk_len; /* Byte Length of ports at gpe1_blk */
1093 uint8_t gpe1_base; /* Offset in gpe model where gpe1 events start */
1094 uint8_t reserved3; /* Reserved */
1095 uint16_t plvl2_lat; /* Worst case HW latency to enter/exit C2 state */
1096 uint16_t plvl3_lat; /* Worst case HW latency to enter/exit C3 state */
1097 uint16_t flush_size; /* Size of area read to flush caches */
1098 uint16_t flush_stride; /* Stride used in flushing caches */
1099 uint8_t duty_offset; /* Bit location of duty cycle field in p_cnt reg */
1100 uint8_t duty_width; /* Bit width of duty cycle field in p_cnt reg */
1101 uint8_t day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */
1102 uint8_t mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */
1103 uint8_t century; /* Index to century in RTC CMOS RAM */
1104 uint8_t reserved4; /* Reserved */
1105 uint8_t reserved4a; /* Reserved */
1106 uint8_t reserved4b; /* Reserved */
1107 #if 0
1108 uint32_t wb_invd : 1; /* The wbinvd instruction works properly */
1109 uint32_t wb_invd_flush : 1; /* The wbinvd flushes but does not invalidate */
1110 uint32_t proc_c1 : 1; /* All processors support C1 state */
1111 uint32_t plvl2_up : 1; /* C2 state works on MP system */
1112 uint32_t pwr_button : 1; /* Power button is handled as a generic feature */
1113 uint32_t sleep_button : 1; /* Sleep button is handled as a generic feature, or not present */
1114 uint32_t fixed_rTC : 1; /* RTC wakeup stat not in fixed register space */
1115 uint32_t rtcs4 : 1; /* RTC wakeup stat not possible from S4 */
1116 uint32_t tmr_val_ext : 1; /* The tmr_val width is 32 bits (0 = 24 bits) */
1117 uint32_t reserved5 : 23; /* Reserved - must be zero */
1118 #else
1119 uint32_t flags;
1120 #endif
1121 };
1122
1123 /*
1124 * MADT values and structures
1125 */
1126
1127 /* Values for MADT PCATCompat */
1128
1129 #define DUAL_PIC 0
1130 #define MULTIPLE_APIC 1
1131
1132
1133 /* Master MADT */
1134
1135 struct multiple_apic_table
1136 {
1137 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
1138 uint32_t local_apic_address; /* Physical address of local APIC */
1139 #if 0
1140 uint32_t PCATcompat : 1; /* A one indicates system also has dual 8259s */
1141 uint32_t reserved1 : 31;
1142 #else
1143 uint32_t flags;
1144 #endif
1145 };
1146
1147
1148 /* Values for Type in APIC_HEADER_DEF */
1149
1150 #define APIC_PROCESSOR 0
1151 #define APIC_IO 1
1152 #define APIC_XRUPT_OVERRIDE 2
1153 #define APIC_NMI 3
1154 #define APIC_LOCAL_NMI 4
1155 #define APIC_ADDRESS_OVERRIDE 5
1156 #define APIC_IO_SAPIC 6
1157 #define APIC_LOCAL_SAPIC 7
1158 #define APIC_XRUPT_SOURCE 8
1159 #define APIC_RESERVED 9 /* 9 and greater are reserved */
1160
1161 /*
1162 * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
1163 */
1164 #define APIC_HEADER_DEF /* Common APIC sub-structure header */\
1165 uint8_t type; \
1166 uint8_t length;
1167
1168 /* Sub-structures for MADT */
1169
1170 struct madt_processor_apic
1171 {
1172 APIC_HEADER_DEF
1173 uint8_t processor_id; /* ACPI processor id */
1174 uint8_t local_apic_id; /* Processor's local APIC id */
1175 #if 0
1176 uint32_t processor_enabled: 1; /* Processor is usable if set */
1177 uint32_t reserved2 : 31; /* Reserved, must be zero */
1178 #else
1179 uint32_t flags;
1180 #endif
1181 };
1182
1183 struct madt_io_apic
1184 {
1185 APIC_HEADER_DEF
1186 uint8_t io_apic_id; /* I/O APIC ID */
1187 uint8_t reserved; /* Reserved - must be zero */
1188 uint32_t address; /* APIC physical address */
1189 uint32_t interrupt; /* Global system interrupt where INTI
1190 * lines start */
1191 };
1192
1193 struct madt_intsrcovr {
1194 APIC_HEADER_DEF
1195 uint8_t bus;
1196 uint8_t source;
1197 uint32_t gsi;
1198 uint16_t flags;
1199 };
1200
1201 #include "acpi-dsdt.hex"
1202
1203 static inline uint16_t cpu_to_le16(uint16_t x)
1204 {
1205 return x;
1206 }
1207
1208 static inline uint32_t cpu_to_le32(uint32_t x)
1209 {
1210 return x;
1211 }
1212
1213 static int acpi_checksum(const uint8_t *data, int len)
1214 {
1215 int sum, i;
1216 sum = 0;
1217 for(i = 0; i < len; i++)
1218 sum += data[i];
1219 return (-sum) & 0xff;
1220 }
1221
1222 static void acpi_build_table_header(struct acpi_table_header *h,
1223 char *sig, int len)
1224 {
1225 memcpy(h->signature, sig, 4);
1226 h->length = cpu_to_le32(len);
1227 h->revision = 1;
1228 #ifdef BX_QEMU
1229 memcpy(h->oem_id, "QEMU ", 6);
1230 memcpy(h->oem_table_id, "QEMU", 4);
1231 #else
1232 memcpy(h->oem_id, "BOCHS ", 6);
1233 memcpy(h->oem_table_id, "BXPC", 4);
1234 #endif
1235 memcpy(h->oem_table_id + 4, sig, 4);
1236 h->oem_revision = cpu_to_le32(1);
1237 #ifdef BX_QEMU
1238 memcpy(h->asl_compiler_id, "QEMU", 4);
1239 #else
1240 memcpy(h->asl_compiler_id, "BXPC", 4);
1241 #endif
1242 h->asl_compiler_revision = cpu_to_le32(1);
1243 h->checksum = acpi_checksum((void *)h, len);
1244 }
1245
1246 /* base_addr must be a multiple of 4KB */
1247 void acpi_bios_init(void)
1248 {
1249 struct rsdp_descriptor *rsdp;
1250 struct rsdt_descriptor_rev1 *rsdt;
1251 struct fadt_descriptor_rev1 *fadt;
1252 struct facs_descriptor_rev1 *facs;
1253 struct multiple_apic_table *madt;
1254 uint8_t *dsdt;
1255 uint32_t base_addr, rsdt_addr, fadt_addr, addr, facs_addr, dsdt_addr;
1256 uint32_t acpi_tables_size, madt_addr, madt_size;
1257 int i;
1258
1259 /* reserve memory space for tables */
1260 #ifdef BX_USE_EBDA_TABLES
1261 ebda_cur_addr = align(ebda_cur_addr, 16);
1262 rsdp = (void *)(ebda_cur_addr);
1263 ebda_cur_addr += sizeof(*rsdp);
1264 #else
1265 bios_table_cur_addr = align(bios_table_cur_addr, 16);
1266 rsdp = (void *)(bios_table_cur_addr);
1267 bios_table_cur_addr += sizeof(*rsdp);
1268 #endif
1269
1270 addr = base_addr = ram_size - ACPI_DATA_SIZE;
1271 rsdt_addr = addr;
1272 rsdt = (void *)(addr);
1273 addr += sizeof(*rsdt);
1274
1275 fadt_addr = addr;
1276 fadt = (void *)(addr);
1277 addr += sizeof(*fadt);
1278
1279 /* XXX: FACS should be in RAM */
1280 addr = (addr + 63) & ~63; /* 64 byte alignment for FACS */
1281 facs_addr = addr;
1282 facs = (void *)(addr);
1283 addr += sizeof(*facs);
1284
1285 dsdt_addr = addr;
1286 dsdt = (void *)(addr);
1287 addr += sizeof(AmlCode);
1288
1289 addr = (addr + 7) & ~7;
1290 madt_addr = addr;
1291 madt_size = sizeof(*madt) +
1292 sizeof(struct madt_processor_apic) * smp_cpus +
1293 sizeof(struct madt_io_apic);
1294 madt = (void *)(addr);
1295 addr += madt_size;
1296
1297 acpi_tables_size = addr - base_addr;
1298
1299 BX_INFO("ACPI tables: RSDP addr=0x%08lx ACPI DATA addr=0x%08lx size=0x%x\n",
1300 (unsigned long)rsdp,
1301 (unsigned long)rsdt, acpi_tables_size);
1302
1303 /* RSDP */
1304 memset(rsdp, 0, sizeof(*rsdp));
1305 memcpy(rsdp->signature, "RSD PTR ", 8);
1306 #ifdef BX_QEMU
1307 memcpy(rsdp->oem_id, "QEMU ", 6);
1308 #else
1309 memcpy(rsdp->oem_id, "BOCHS ", 6);
1310 #endif
1311 rsdp->rsdt_physical_address = cpu_to_le32(rsdt_addr);
1312 rsdp->checksum = acpi_checksum((void *)rsdp, 20);
1313
1314 /* RSDT */
1315 rsdt->table_offset_entry[0] = cpu_to_le32(fadt_addr);
1316 rsdt->table_offset_entry[1] = cpu_to_le32(madt_addr);
1317 acpi_build_table_header((struct acpi_table_header *)rsdt,
1318 "RSDT", sizeof(*rsdt));
1319
1320 /* FADT */
1321 memset(fadt, 0, sizeof(*fadt));
1322 fadt->firmware_ctrl = cpu_to_le32(facs_addr);
1323 fadt->dsdt = cpu_to_le32(dsdt_addr);
1324 fadt->model = 1;
1325 fadt->reserved1 = 0;
1326 fadt->sci_int = cpu_to_le16(pm_sci_int);
1327 fadt->smi_cmd = cpu_to_le32(SMI_CMD_IO_ADDR);
1328 fadt->acpi_enable = 0xf1;
1329 fadt->acpi_disable = 0xf0;
1330 fadt->pm1a_evt_blk = cpu_to_le32(pm_io_base);
1331 fadt->pm1a_cnt_blk = cpu_to_le32(pm_io_base + 0x04);
1332 fadt->pm_tmr_blk = cpu_to_le32(pm_io_base + 0x08);
1333 fadt->pm1_evt_len = 4;
1334 fadt->pm1_cnt_len = 2;
1335 fadt->pm_tmr_len = 4;
1336 fadt->plvl2_lat = cpu_to_le16(0x0fff); // C2 state not supported
1337 fadt->plvl3_lat = cpu_to_le16(0x0fff); // C3 state not supported
1338 /* WBINVD + PROC_C1 + SLP_BUTTON + FIX_RTC */
1339 fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 5) | (1 << 6));
1340 acpi_build_table_header((struct acpi_table_header *)fadt, "FACP",
1341 sizeof(*fadt));
1342
1343 /* FACS */
1344 memset(facs, 0, sizeof(*facs));
1345 memcpy(facs->signature, "FACS", 4);
1346 facs->length = cpu_to_le32(sizeof(*facs));
1347
1348 /* DSDT */
1349 memcpy(dsdt, AmlCode, sizeof(AmlCode));
1350
1351 /* MADT */
1352 {
1353 struct madt_processor_apic *apic;
1354 struct madt_io_apic *io_apic;
1355 struct madt_intsrcovr *intsrcovr;
1356
1357 memset(madt, 0, madt_size);
1358 madt->local_apic_address = cpu_to_le32(0xfee00000);
1359 madt->flags = cpu_to_le32(1);
1360 apic = (void *)(madt + 1);
1361 for(i=0;i<smp_cpus;i++) {
1362 apic->type = APIC_PROCESSOR;
1363 apic->length = sizeof(*apic);
1364 apic->processor_id = i;
1365 apic->local_apic_id = i;
1366 apic->flags = cpu_to_le32(1);
1367 apic++;
1368 }
1369 io_apic = (void *)apic;
1370 io_apic->type = APIC_IO;
1371 io_apic->length = sizeof(*io_apic);
1372 io_apic->io_apic_id = smp_cpus;
1373 io_apic->address = cpu_to_le32(0xfec00000);
1374 io_apic->interrupt = cpu_to_le32(0);
1375
1376 intsrcovr = (struct madt_intsrcovr*)(io_apic + 1);
1377 for ( i = 0; i < 16; i++ ) {
1378 if ( PCI_ISA_IRQ_MASK & (1U << i) ) {
1379 memset(intsrcovr, 0, sizeof(*intsrcovr));
1380 intsrcovr->type = APIC_XRUPT_OVERRIDE;
1381 intsrcovr->length = sizeof(*intsrcovr);
1382 intsrcovr->source = i;
1383 intsrcovr->gsi = i;
1384 intsrcovr->flags = 0xd; /* active high, level triggered */
1385 } else {
1386 /* No need for a INT source override structure. */
1387 continue;
1388 }
1389 intsrcovr++;
1390 madt_size += sizeof(struct madt_intsrcovr);
1391 }
1392 acpi_build_table_header((struct acpi_table_header *)madt,
1393 "APIC", madt_size);
1394 }
1395 }
1396
1397 void rombios32_init(void)
1398 {
1399 BX_INFO("Starting rombios32\n");
1400
1401 ram_probe();
1402
1403 cpu_probe();
1404
1405 smp_probe();
1406
1407 pci_bios_init();
1408
1409 if (bios_table_cur_addr != 0) {
1410
1411 mptable_init();
1412
1413 if (acpi_enabled)
1414 acpi_bios_init();
1415
1416 bios_lock_shadow_ram();
1417 }
1418 }
kvm userspace components