2 * QLogic iSCSI HBA Driver
3 * Copyright (c) 2003-2010 QLogic Corporation
5 * See LICENSE.qla4xxx for copyright and licensing details.
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/types.h>
14 #include <linux/module.h>
15 #include <linux/list.h>
16 #include <linux/pci.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/sched.h>
19 #include <linux/slab.h>
20 #include <linux/dmapool.h>
21 #include <linux/mempool.h>
22 #include <linux/spinlock.h>
23 #include <linux/workqueue.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/mutex.h>
27 #include <linux/aer.h>
30 #include <scsi/scsi.h>
31 #include <scsi/scsi_host.h>
32 #include <scsi/scsi_device.h>
33 #include <scsi/scsi_cmnd.h>
34 #include <scsi/scsi_transport.h>
35 #include <scsi/scsi_transport_iscsi.h>
40 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4010
41 #define PCI_DEVICE_ID_QLOGIC_ISP4010 0x4010
44 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4022
45 #define PCI_DEVICE_ID_QLOGIC_ISP4022 0x4022
48 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4032
49 #define PCI_DEVICE_ID_QLOGIC_ISP4032 0x4032
52 #ifndef PCI_DEVICE_ID_QLOGIC_ISP8022
53 #define PCI_DEVICE_ID_QLOGIC_ISP8022 0x8022
56 #define ISP4XXX_PCI_FN_1 0x1
57 #define ISP4XXX_PCI_FN_2 0x3
63 * Data bit definitions
81 #define BIT_16 0x10000
82 #define BIT_17 0x20000
83 #define BIT_18 0x40000
84 #define BIT_19 0x80000
85 #define BIT_20 0x100000
86 #define BIT_21 0x200000
87 #define BIT_22 0x400000
88 #define BIT_23 0x800000
89 #define BIT_24 0x1000000
90 #define BIT_25 0x2000000
91 #define BIT_26 0x4000000
92 #define BIT_27 0x8000000
93 #define BIT_28 0x10000000
94 #define BIT_29 0x20000000
95 #define BIT_30 0x40000000
96 #define BIT_31 0x80000000
99 * Macros to help code, maintain, etc.
101 #define ql4_printk(level, ha, format, arg...) \
102 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
106 * Host adapter default definitions
107 ***********************************/
110 #define MAX_TARGETS MAX_DEV_DB_ENTRIES
111 #define MAX_LUNS 0xffff
112 #define MAX_AEN_ENTRIES 256 /* should be > EXT_DEF_MAX_AEN_QUEUE */
113 #define MAX_DDB_ENTRIES MAX_DEV_DB_ENTRIES
114 #define MAX_PDU_ENTRIES 32
115 #define INVALID_ENTRY 0xFFFF
116 #define MAX_CMDS_TO_RISC 1024
117 #define MAX_SRBS MAX_CMDS_TO_RISC
118 #define MBOX_AEN_REG_COUNT 5
119 #define MAX_INIT_RETRIES 5
124 #define REQUEST_QUEUE_DEPTH MAX_CMDS_TO_RISC
125 #define RESPONSE_QUEUE_DEPTH 64
126 #define QUEUE_SIZE 64
127 #define DMA_BUFFER_SIZE 512
132 #define MAC_ADDR_LEN 6 /* in bytes */
133 #define IP_ADDR_LEN 4 /* in bytes */
134 #define IPv6_ADDR_LEN 16 /* IPv6 address size */
135 #define DRIVER_NAME "qla4xxx"
137 #define MAX_LINKED_CMDS_PER_LUN 3
138 #define MAX_REQS_SERVICED_PER_INTR 1
140 #define ISCSI_IPADDR_SIZE 4 /* IP address size */
141 #define ISCSI_ALIAS_SIZE 32 /* ISCSI Alias name size */
142 #define ISCSI_NAME_SIZE 0xE0 /* ISCSI Name size */
144 #define QL4_SESS_RECOVERY_TMO 30 /* iSCSI session */
145 /* recovery timeout */
147 #define LSDW(x) ((u32)((u64)(x)))
148 #define MSDW(x) ((u32)((((u64)(x)) >> 16) >> 16))
151 * Retry & Timeout Values
154 #define SOFT_RESET_TOV 30
155 #define RESET_INTR_TOV 3
156 #define SEMAPHORE_TOV 10
157 #define ADAPTER_INIT_TOV 30
158 #define ADAPTER_RESET_TOV 180
159 #define EXTEND_CMD_TOV 60
160 #define WAIT_CMD_TOV 30
161 #define EH_WAIT_CMD_TOV 120
162 #define FIRMWARE_UP_TOV 60
163 #define RESET_FIRMWARE_TOV 30
164 #define LOGOUT_TOV 10
165 #define IOCB_TOV_MARGIN 10
166 #define RELOGIN_TOV 18
167 #define ISNS_DEREG_TOV 5
168 #define HBA_ONLINE_TOV 30
170 #define MAX_RESET_HA_RETRIES 2
172 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
175 * SCSI Request Block structure (srb) that is placed
176 * on cmd->SCp location of every I/O [We have 22 bytes available]
179 struct list_head list
; /* (8) */
180 struct scsi_qla_host
*ha
; /* HA the SP is queued on */
181 struct ddb_entry
*ddb
;
182 uint16_t flags
; /* (1) Status flags. */
184 #define SRB_DMA_VALID BIT_3 /* DMA Buffer mapped. */
185 #define SRB_GOT_SENSE BIT_4 /* sense data received. */
186 uint8_t state
; /* (1) Status flags. */
188 #define SRB_NO_QUEUE_STATE 0 /* Request is in between states */
189 #define SRB_FREE_STATE 1
190 #define SRB_ACTIVE_STATE 3
191 #define SRB_ACTIVE_TIMEOUT_STATE 4
192 #define SRB_SUSPENDED_STATE 7 /* Request in suspended state */
194 struct scsi_cmnd
*cmd
; /* (4) SCSI command block */
195 dma_addr_t dma_handle
; /* (4) for unmap of single transfers */
196 struct kref srb_ref
; /* reference count for this srb */
197 uint8_t err_id
; /* error id */
198 #define SRB_ERR_PORT 1 /* Request failed because "port down" */
199 #define SRB_ERR_LOOP 2 /* Request failed because "loop down" */
200 #define SRB_ERR_DEVICE 3 /* Request failed because "device error" */
201 #define SRB_ERR_OTHER 4
205 uint16_t iocb_cnt
; /* Number of used iocbs */
208 /* Used for extended sense / status continuation */
209 uint8_t *req_sense_ptr
;
210 uint16_t req_sense_len
;
215 * Asynchronous Event Queue structure
218 uint32_t mbox_sts
[MBOX_AEN_REG_COUNT
];
223 struct aen entry
[MAX_AEN_ENTRIES
];
227 * Device Database (DDB) structure
230 struct list_head list
; /* ddb list */
231 struct scsi_qla_host
*ha
;
232 struct iscsi_cls_session
*sess
;
233 struct iscsi_cls_conn
*conn
;
235 atomic_t state
; /* DDB State */
237 unsigned long flags
; /* DDB Flags */
239 uint16_t fw_ddb_index
; /* DDB firmware index */
241 uint32_t fw_ddb_device_state
; /* F/W Device State -- see ql4_fw.h */
244 uint16_t target_session_id
;
245 uint16_t connection_id
;
246 uint16_t exe_throttle
; /* Max mumber of cmds outstanding
248 uint16_t task_mgmt_timeout
; /* Min time for task mgmt cmds to
250 uint16_t default_relogin_timeout
; /* Max time to wait for
251 * relogin to complete */
252 uint16_t tcp_source_port_num
;
253 uint32_t default_time2wait
; /* Default Min time between
254 * relogins (+aens) */
256 atomic_t retry_relogin_timer
; /* Min Time between relogins
258 atomic_t relogin_timer
; /* Max Time to wait for relogin to complete */
259 atomic_t relogin_retry_count
; /* Num of times relogin has been
264 uint8_t ip_addr
[IP_ADDR_LEN
];
265 uint8_t iscsi_name
[ISCSI_NAME_SIZE
]; /* 72 x48 */
266 uint8_t iscsi_alias
[0x20];
268 uint16_t iscsi_max_burst_len
;
269 uint16_t iscsi_max_outsnd_r2t
;
270 uint16_t iscsi_first_burst_len
;
271 uint16_t iscsi_max_rcv_data_seg_len
;
272 uint16_t iscsi_max_snd_data_seg_len
;
274 struct in6_addr remote_ipv6_addr
;
275 struct in6_addr link_local_ipv6_addr
;
281 #define DDB_STATE_DEAD 0 /* We can no longer talk to
283 #define DDB_STATE_ONLINE 1 /* Device ready to accept
285 #define DDB_STATE_MISSING 2 /* Device logged off, trying
291 #define DF_RELOGIN 0 /* Relogin to device */
292 #define DF_ISNS_DISCOVERED 2 /* Device was discovered via iSNS */
293 #define DF_FO_MASKED 3
297 #include "ql4_nvram.h"
299 struct ql82xx_hw_data
{
300 /* Offsets for flash/nvram access (set to ~0 if not used). */
301 uint32_t flash_conf_off
;
302 uint32_t flash_data_off
;
304 uint32_t fdt_wrt_disable
;
305 uint32_t fdt_erase_cmd
;
306 uint32_t fdt_block_size
;
307 uint32_t fdt_unprotect_sec_cmd
;
308 uint32_t fdt_protect_sec_cmd
;
310 uint32_t flt_region_flt
;
311 uint32_t flt_region_fdt
;
312 uint32_t flt_region_boot
;
313 uint32_t flt_region_bootload
;
314 uint32_t flt_region_fw
;
318 struct qla4_8xxx_legacy_intr_set
{
319 uint32_t int_vec_bit
;
320 uint32_t tgt_status_reg
;
321 uint32_t tgt_mask_reg
;
322 uint32_t pci_int_reg
;
327 #define QLA_MSIX_DEFAULT 0x00
328 #define QLA_MSIX_RSP_Q 0x01
330 #define QLA_MSIX_ENTRIES 2
331 #define QLA_MIDX_DEFAULT 0
332 #define QLA_MIDX_RSP_Q 1
334 struct ql4_msix_entry
{
336 uint16_t msix_vector
;
343 struct isp_operations
{
344 int (*iospace_config
) (struct scsi_qla_host
*ha
);
345 void (*pci_config
) (struct scsi_qla_host
*);
346 void (*disable_intrs
) (struct scsi_qla_host
*);
347 void (*enable_intrs
) (struct scsi_qla_host
*);
348 int (*start_firmware
) (struct scsi_qla_host
*);
349 irqreturn_t (*intr_handler
) (int , void *);
350 void (*interrupt_service_routine
) (struct scsi_qla_host
*, uint32_t);
351 int (*reset_chip
) (struct scsi_qla_host
*);
352 int (*reset_firmware
) (struct scsi_qla_host
*);
353 void (*queue_iocb
) (struct scsi_qla_host
*);
354 void (*complete_iocb
) (struct scsi_qla_host
*);
355 uint16_t (*rd_shdw_req_q_out
) (struct scsi_qla_host
*);
356 uint16_t (*rd_shdw_rsp_q_in
) (struct scsi_qla_host
*);
357 int (*get_sys_info
) (struct scsi_qla_host
*);
361 * Linux Host Adapter structure
363 struct scsi_qla_host
{
364 /* Linux adapter configuration data */
367 #define AF_ONLINE 0 /* 0x00000001 */
368 #define AF_INIT_DONE 1 /* 0x00000002 */
369 #define AF_MBOX_COMMAND 2 /* 0x00000004 */
370 #define AF_MBOX_COMMAND_DONE 3 /* 0x00000008 */
371 #define AF_DPC_SCHEDULED 5 /* 0x00000020 */
372 #define AF_INTERRUPTS_ON 6 /* 0x00000040 */
373 #define AF_GET_CRASH_RECORD 7 /* 0x00000080 */
374 #define AF_LINK_UP 8 /* 0x00000100 */
375 #define AF_IRQ_ATTACHED 10 /* 0x00000400 */
376 #define AF_DISABLE_ACB_COMPLETE 11 /* 0x00000800 */
377 #define AF_HA_REMOVAL 12 /* 0x00001000 */
378 #define AF_INTx_ENABLED 15 /* 0x00008000 */
379 #define AF_MSI_ENABLED 16 /* 0x00010000 */
380 #define AF_MSIX_ENABLED 17 /* 0x00020000 */
381 #define AF_MBOX_COMMAND_NOPOLL 18 /* 0x00040000 */
382 #define AF_FW_RECOVERY 19 /* 0x00080000 */
383 #define AF_EEH_BUSY 20 /* 0x00100000 */
384 #define AF_PCI_CHANNEL_IO_PERM_FAILURE 21 /* 0x00200000 */
386 unsigned long dpc_flags
;
388 #define DPC_RESET_HA 1 /* 0x00000002 */
389 #define DPC_RETRY_RESET_HA 2 /* 0x00000004 */
390 #define DPC_RELOGIN_DEVICE 3 /* 0x00000008 */
391 #define DPC_RESET_HA_FW_CONTEXT 4 /* 0x00000010 */
392 #define DPC_RESET_HA_INTR 5 /* 0x00000020 */
393 #define DPC_ISNS_RESTART 7 /* 0x00000080 */
394 #define DPC_AEN 9 /* 0x00000200 */
395 #define DPC_GET_DHCP_IP_ADDR 15 /* 0x00008000 */
396 #define DPC_LINK_CHANGED 18 /* 0x00040000 */
397 #define DPC_RESET_ACTIVE 20 /* 0x00040000 */
398 #define DPC_HA_UNRECOVERABLE 21 /* 0x00080000 ISP-82xx only*/
399 #define DPC_HA_NEED_QUIESCENT 22 /* 0x00100000 ISP-82xx only*/
402 struct Scsi_Host
*host
; /* pointer to host data */
408 #define SRB_MIN_REQ 128
409 mempool_t
*srb_mempool
;
411 /* pci information */
412 struct pci_dev
*pdev
;
414 struct isp_reg __iomem
*reg
; /* Base I/O address */
415 unsigned long pio_address
;
416 unsigned long pio_length
;
417 #define MIN_IOBASE_LEN 0x100
419 uint16_t req_q_count
;
421 unsigned long host_no
;
423 /* NVRAM registers */
424 struct eeprom_data
*nvram
;
425 spinlock_t hardware_lock ____cacheline_aligned
;
426 uint32_t eeprom_cmd_data
;
428 /* Counters for general statistics */
430 uint64_t adapter_error_count
;
431 uint64_t device_error_count
;
432 uint64_t total_io_count
;
433 uint64_t total_mbytes_xferred
;
434 uint64_t link_failure_count
;
435 uint64_t invalid_crc_count
;
436 uint32_t bytes_xfered
;
437 uint32_t spurious_int_count
;
438 uint32_t aborted_io_count
;
439 uint32_t io_timeout_count
;
440 uint32_t mailbox_timeout_count
;
441 uint32_t seconds_since_last_intr
;
442 uint32_t seconds_since_last_heartbeat
;
445 /* Info Needed for Management App */
446 /* --- From GetFwVersion --- */
447 uint32_t firmware_version
[2];
448 uint32_t patch_number
;
449 uint32_t build_number
;
452 /* --- From Init_FW --- */
453 /* init_cb_t *init_cb; */
454 uint16_t firmware_options
;
455 uint16_t tcp_options
;
456 uint8_t ip_address
[IP_ADDR_LEN
];
457 uint8_t subnet_mask
[IP_ADDR_LEN
];
458 uint8_t gateway
[IP_ADDR_LEN
];
460 uint8_t name_string
[256];
461 uint8_t heartbeat_interval
;
463 /* --- From FlashSysInfo --- */
464 uint8_t my_mac
[MAC_ADDR_LEN
];
465 uint8_t serial_number
[16];
467 /* --- From GetFwState --- */
468 uint32_t firmware_state
;
469 uint32_t addl_fw_state
;
471 /* Linux kernel thread */
472 struct workqueue_struct
*dpc_thread
;
473 struct work_struct dpc_work
;
475 /* Linux timer thread */
476 struct timer_list timer
;
477 uint32_t timer_active
;
479 /* Recovery Timers */
480 atomic_t check_relogin_timeouts
;
481 uint32_t retry_reset_ha_cnt
;
482 uint32_t isp_reset_timer
; /* reset test timer */
483 uint32_t nic_reset_timer
; /* simulated nic reset test timer */
485 struct list_head free_srb_q
;
486 uint16_t free_srb_q_count
;
487 uint16_t num_srbs_allocated
;
489 /* DMA Memory Block */
491 dma_addr_t queues_dma
;
492 unsigned long queues_len
;
494 #define MEM_ALIGN_VALUE \
495 ((max(REQUEST_QUEUE_DEPTH, RESPONSE_QUEUE_DEPTH)) * \
496 sizeof(struct queue_entry))
497 /* request and response queue variables */
498 dma_addr_t request_dma
;
499 struct queue_entry
*request_ring
;
500 struct queue_entry
*request_ptr
;
501 dma_addr_t response_dma
;
502 struct queue_entry
*response_ring
;
503 struct queue_entry
*response_ptr
;
504 dma_addr_t shadow_regs_dma
;
505 struct shadow_regs
*shadow_regs
;
506 uint16_t request_in
; /* Current indexes. */
507 uint16_t request_out
;
508 uint16_t response_in
;
509 uint16_t response_out
;
511 /* aen queue variables */
512 uint16_t aen_q_count
; /* Number of available aen_q entries */
513 uint16_t aen_in
; /* Current indexes */
515 struct aen aen_q
[MAX_AEN_ENTRIES
];
517 struct ql4_aen_log aen_log
;/* tracks all aens */
519 /* This mutex protects several threads to do mailbox commands
522 struct mutex mbox_sem
;
524 /* temporary mailbox status registers */
525 volatile uint8_t mbox_status_count
;
526 volatile uint32_t mbox_status
[MBOX_REG_COUNT
];
528 /* local device database list (contains internal ddb entries) */
529 struct list_head ddb_list
;
531 /* Map ddb_list entry by FW ddb index */
532 struct ddb_entry
*fw_ddb_index_map
[MAX_DDB_ENTRIES
];
534 /* Saved srb for status continuation entry processing */
535 struct srb
*status_srb
;
537 /* IPv6 support info from InitFW */
539 uint8_t ipv4_addr_state
;
540 uint16_t ipv4_options
;
543 uint32_t ipv6_options
;
544 uint32_t ipv6_addl_options
;
545 uint8_t ipv6_link_local_state
;
546 uint8_t ipv6_addr0_state
;
547 uint8_t ipv6_addr1_state
;
548 uint8_t ipv6_default_router_state
;
549 struct in6_addr ipv6_link_local_addr
;
550 struct in6_addr ipv6_addr0
;
551 struct in6_addr ipv6_addr1
;
552 struct in6_addr ipv6_default_router_addr
;
554 /* qla82xx specific fields */
555 struct device_reg_82xx __iomem
*qla4_8xxx_reg
; /* Base I/O address */
556 unsigned long nx_pcibase
; /* Base I/O address */
557 uint8_t *nx_db_rd_ptr
; /* Doorbell read pointer */
558 unsigned long nx_db_wr_ptr
; /* Door bell write pointer */
559 unsigned long first_page_group_start
;
560 unsigned long first_page_group_end
;
563 uint32_t curr_window
;
564 uint32_t ddr_mn_window
;
565 unsigned long mn_win_crb
;
566 unsigned long ms_win_crb
;
572 struct qla4_8xxx_legacy_intr_set nx_legacy_intr
;
576 uint32_t fw_heartbeat_counter
;
578 struct isp_operations
*isp_ops
;
579 struct ql82xx_hw_data hw
;
581 struct ql4_msix_entry msix_entries
[QLA_MSIX_ENTRIES
];
583 uint32_t nx_dev_init_timeout
;
584 uint32_t nx_reset_timeout
;
586 struct completion mbx_intr_comp
;
589 static inline int is_ipv4_enabled(struct scsi_qla_host
*ha
)
591 return ((ha
->ipv4_options
& IPOPT_IPv4_PROTOCOL_ENABLE
) != 0);
594 static inline int is_ipv6_enabled(struct scsi_qla_host
*ha
)
596 return ((ha
->ipv6_options
& IPV6_OPT_IPV6_PROTOCOL_ENABLE
) != 0);
599 static inline int is_qla4010(struct scsi_qla_host
*ha
)
601 return ha
->pdev
->device
== PCI_DEVICE_ID_QLOGIC_ISP4010
;
604 static inline int is_qla4022(struct scsi_qla_host
*ha
)
606 return ha
->pdev
->device
== PCI_DEVICE_ID_QLOGIC_ISP4022
;
609 static inline int is_qla4032(struct scsi_qla_host
*ha
)
611 return ha
->pdev
->device
== PCI_DEVICE_ID_QLOGIC_ISP4032
;
614 static inline int is_qla8022(struct scsi_qla_host
*ha
)
616 return ha
->pdev
->device
== PCI_DEVICE_ID_QLOGIC_ISP8022
;
619 /* Note: Currently AER/EEH is now supported only for 8022 cards
620 * This function needs to be updated when AER/EEH is enabled
623 static inline int is_aer_supported(struct scsi_qla_host
*ha
)
625 return ha
->pdev
->device
== PCI_DEVICE_ID_QLOGIC_ISP8022
;
628 static inline int adapter_up(struct scsi_qla_host
*ha
)
630 return (test_bit(AF_ONLINE
, &ha
->flags
) != 0) &&
631 (test_bit(AF_LINK_UP
, &ha
->flags
) != 0);
634 static inline struct scsi_qla_host
* to_qla_host(struct Scsi_Host
*shost
)
636 return (struct scsi_qla_host
*)shost
->hostdata
;
639 static inline void __iomem
* isp_semaphore(struct scsi_qla_host
*ha
)
641 return (is_qla4010(ha
) ?
642 &ha
->reg
->u1
.isp4010
.nvram
:
643 &ha
->reg
->u1
.isp4022
.semaphore
);
646 static inline void __iomem
* isp_nvram(struct scsi_qla_host
*ha
)
648 return (is_qla4010(ha
) ?
649 &ha
->reg
->u1
.isp4010
.nvram
:
650 &ha
->reg
->u1
.isp4022
.nvram
);
653 static inline void __iomem
* isp_ext_hw_conf(struct scsi_qla_host
*ha
)
655 return (is_qla4010(ha
) ?
656 &ha
->reg
->u2
.isp4010
.ext_hw_conf
:
657 &ha
->reg
->u2
.isp4022
.p0
.ext_hw_conf
);
660 static inline void __iomem
* isp_port_status(struct scsi_qla_host
*ha
)
662 return (is_qla4010(ha
) ?
663 &ha
->reg
->u2
.isp4010
.port_status
:
664 &ha
->reg
->u2
.isp4022
.p0
.port_status
);
667 static inline void __iomem
* isp_port_ctrl(struct scsi_qla_host
*ha
)
669 return (is_qla4010(ha
) ?
670 &ha
->reg
->u2
.isp4010
.port_ctrl
:
671 &ha
->reg
->u2
.isp4022
.p0
.port_ctrl
);
674 static inline void __iomem
* isp_port_error_status(struct scsi_qla_host
*ha
)
676 return (is_qla4010(ha
) ?
677 &ha
->reg
->u2
.isp4010
.port_err_status
:
678 &ha
->reg
->u2
.isp4022
.p0
.port_err_status
);
681 static inline void __iomem
* isp_gp_out(struct scsi_qla_host
*ha
)
683 return (is_qla4010(ha
) ?
684 &ha
->reg
->u2
.isp4010
.gp_out
:
685 &ha
->reg
->u2
.isp4022
.p0
.gp_out
);
688 static inline int eeprom_ext_hw_conf_offset(struct scsi_qla_host
*ha
)
690 return (is_qla4010(ha
) ?
691 offsetof(struct eeprom_data
, isp4010
.ext_hw_conf
) / 2 :
692 offsetof(struct eeprom_data
, isp4022
.ext_hw_conf
) / 2);
695 int ql4xxx_sem_spinlock(struct scsi_qla_host
* ha
, u32 sem_mask
, u32 sem_bits
);
696 void ql4xxx_sem_unlock(struct scsi_qla_host
* ha
, u32 sem_mask
);
697 int ql4xxx_sem_lock(struct scsi_qla_host
* ha
, u32 sem_mask
, u32 sem_bits
);
699 static inline int ql4xxx_lock_flash(struct scsi_qla_host
*a
)
702 return ql4xxx_sem_spinlock(a
, QL4010_FLASH_SEM_MASK
,
703 QL4010_FLASH_SEM_BITS
);
705 return ql4xxx_sem_spinlock(a
, QL4022_FLASH_SEM_MASK
,
706 (QL4022_RESOURCE_BITS_BASE_CODE
|
707 (a
->mac_index
)) << 13);
710 static inline void ql4xxx_unlock_flash(struct scsi_qla_host
*a
)
713 ql4xxx_sem_unlock(a
, QL4010_FLASH_SEM_MASK
);
715 ql4xxx_sem_unlock(a
, QL4022_FLASH_SEM_MASK
);
718 static inline int ql4xxx_lock_nvram(struct scsi_qla_host
*a
)
721 return ql4xxx_sem_spinlock(a
, QL4010_NVRAM_SEM_MASK
,
722 QL4010_NVRAM_SEM_BITS
);
724 return ql4xxx_sem_spinlock(a
, QL4022_NVRAM_SEM_MASK
,
725 (QL4022_RESOURCE_BITS_BASE_CODE
|
726 (a
->mac_index
)) << 10);
729 static inline void ql4xxx_unlock_nvram(struct scsi_qla_host
*a
)
732 ql4xxx_sem_unlock(a
, QL4010_NVRAM_SEM_MASK
);
734 ql4xxx_sem_unlock(a
, QL4022_NVRAM_SEM_MASK
);
737 static inline int ql4xxx_lock_drvr(struct scsi_qla_host
*a
)
740 return ql4xxx_sem_lock(a
, QL4010_DRVR_SEM_MASK
,
741 QL4010_DRVR_SEM_BITS
);
743 return ql4xxx_sem_lock(a
, QL4022_DRVR_SEM_MASK
,
744 (QL4022_RESOURCE_BITS_BASE_CODE
|
745 (a
->mac_index
)) << 1);
748 static inline void ql4xxx_unlock_drvr(struct scsi_qla_host
*a
)
751 ql4xxx_sem_unlock(a
, QL4010_DRVR_SEM_MASK
);
753 ql4xxx_sem_unlock(a
, QL4022_DRVR_SEM_MASK
);
756 /*---------------------------------------------------------------------------*/
758 /* Defines for qla4xxx_initialize_adapter() and qla4xxx_recover_adapter() */
759 #define PRESERVE_DDB_LIST 0
760 #define REBUILD_DDB_LIST 1
762 /* Defines for process_aen() */
763 #define PROCESS_ALL_AENS 0
764 #define FLUSH_DDB_CHANGED_AENS 1
766 #endif /*_QLA4XXX_H */