drivers/usb/host/ehci.h

   1 /*
   2  * Copyright (c) 2001-2002 by David Brownell
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the
   6  * Free Software Foundation; either version 2 of the License, or (at your
   7  * option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  11  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software Foundation,
  16  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17  */
  18
  19 #ifndef __LINUX_EHCI_HCD_H
  20 #define __LINUX_EHCI_HCD_H
  21
  22 /* definitions used for the EHCI driver */
  23
  24 /*
  25  * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
  26  * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on
  27  * the host controller implementation.
  28  *
  29  * To facilitate the strongest possible byte-order checking from "sparse"
  30  * and so on, we use __leXX unless that's not practical.
  31  */
  32 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
  33 typedef __u32 __bitwise __hc32;
  34 typedef __u16 __bitwise __hc16;
  35 #else
  36 #define __hc32  __le32
  37 #define __hc16  __le16
  38 #endif
  39
  40 /* statistics can be kept for tuning/monitoring */
  41 struct ehci_stats {
  42         /* irq usage */
  43         unsigned long           normal;
  44         unsigned long           error;
  45         unsigned long           reclaim;
  46         unsigned long           lost_iaa;
  47
  48         /* termination of urbs from core */
  49         unsigned long           complete;
  50         unsigned long           unlink;
  51 };
  52
  53 /* ehci_hcd->lock guards shared data against other CPUs:
  54  *   ehci_hcd:  async, reclaim, periodic (and shadow), ...
  55  *   usb_host_endpoint: hcpriv
  56  *   ehci_qh:   qh_next, qtd_list
  57  *   ehci_qtd:  qtd_list
  58  *
  59  * Also, hold this lock when talking to HC registers or
  60  * when updating hw_* fields in shared qh/qtd/... structures.
  61  */
  62
  63 #define EHCI_MAX_ROOT_PORTS     15              /* see HCS_N_PORTS */
  64
  65 struct ehci_hcd {                       /* one per controller */
  66         /* glue to PCI and HCD framework */
  67         struct ehci_caps __iomem *caps;
  68         struct ehci_regs __iomem *regs;
  69         struct ehci_dbg_port __iomem *debug;
  70
  71         __u32                   hcs_params;     /* cached register copy */
  72         spinlock_t              lock;
  73
  74         /* async schedule support */
  75         struct ehci_qh          *async;
  76         struct ehci_qh          *dummy;         /* For AMD quirk use */
  77         struct ehci_qh          *reclaim;
  78         unsigned                scanning : 1;
  79
  80         /* periodic schedule support */
  81 #define DEFAULT_I_TDPS          1024            /* some HCs can do less */
  82         unsigned                periodic_size;
  83         __hc32                  *periodic;      /* hw periodic table */
  84         dma_addr_t              periodic_dma;
  85         unsigned                i_thresh;       /* uframes HC might cache */
  86
  87         union ehci_shadow       *pshadow;       /* mirror hw periodic table */
  88         int                     next_uframe;    /* scan periodic, start here */
  89         unsigned                periodic_sched; /* periodic activity count */
  90
  91         /* list of itds & sitds completed while clock_frame was still active */
  92         struct list_head        cached_itd_list;
  93         struct list_head        cached_sitd_list;
  94         unsigned                clock_frame;
  95
  96         /* per root hub port */
  97         unsigned long           reset_done [EHCI_MAX_ROOT_PORTS];
  98
  99         /* bit vectors (one bit per port) */
 100         unsigned long           bus_suspended;          /* which ports were
 101                         already suspended at the start of a bus suspend */
 102         unsigned long           companion_ports;        /* which ports are
 103                         dedicated to the companion controller */
 104         unsigned long           owned_ports;            /* which ports are
 105                         owned by the companion during a bus suspend */
 106         unsigned long           port_c_suspend;         /* which ports have
 107                         the change-suspend feature turned on */
 108         unsigned long           suspended_ports;        /* which ports are
 109                         suspended */
 110
 111         /* per-HC memory pools (could be per-bus, but ...) */
 112         struct dma_pool         *qh_pool;       /* qh per active urb */
 113         struct dma_pool         *qtd_pool;      /* one or more per qh */
 114         struct dma_pool         *itd_pool;      /* itd per iso urb */
 115         struct dma_pool         *sitd_pool;     /* sitd per split iso urb */
 116
 117         struct timer_list       iaa_watchdog;
 118         struct timer_list       watchdog;
 119         unsigned long           actions;
 120         unsigned                stamp;
 121         unsigned                random_frame;
 122         unsigned long           next_statechange;
 123         ktime_t                 last_periodic_enable;
 124         u32                     command;
 125
 126         /* SILICON QUIRKS */
 127         unsigned                no_selective_suspend:1;
 128         unsigned                has_fsl_port_bug:1; /* FreeScale */
 129         unsigned                big_endian_mmio:1;
 130         unsigned                big_endian_desc:1;
 131         unsigned                has_amcc_usb23:1;
 132         unsigned                need_io_watchdog:1;
 133         unsigned                broken_periodic:1;
 134         unsigned                amd_pll_fix:1;
 135         unsigned                fs_i_thresh:1;  /* Intel iso scheduling */
 136         unsigned                use_dummy_qh:1; /* AMD Frame List table quirk*/
 137         unsigned                has_synopsys_hc_bug:1; /* Synopsys HC */
 138
 139         /* required for usb32 quirk */
 140         #define OHCI_CTRL_HCFS          (3 << 6)
 141         #define OHCI_USB_OPER           (2 << 6)
 142         #define OHCI_USB_SUSPEND        (3 << 6)
 143
 144         #define OHCI_HCCTRL_OFFSET      0x4
 145         #define OHCI_HCCTRL_LEN         0x4
 146         __hc32                  *ohci_hcctrl_reg;
 147         unsigned                has_hostpc:1;
 148         unsigned                has_lpm:1;  /* support link power management */
 149         unsigned                has_ppcd:1; /* support per-port change bits */
 150         u8                      sbrn;           /* packed release number */
 151
 152         /* irq statistics */
 153 #ifdef EHCI_STATS
 154         struct ehci_stats       stats;
 155 #       define COUNT(x) do { (x)++; } while (0)
 156 #else
 157 #       define COUNT(x) do {} while (0)
 158 #endif
 159
 160         /* debug files */
 161 #ifdef DEBUG
 162         struct dentry           *debug_dir;
 163 #endif
 164 };
 165
 166 /* convert between an HCD pointer and the corresponding EHCI_HCD */
 167 static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd)
 168 {
 169         return (struct ehci_hcd *) (hcd->hcd_priv);
 170 }
 171 static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci)
 172 {
 173         return container_of ((void *) ehci, struct usb_hcd, hcd_priv);
 174 }
 175
 176
 177 static inline void
 178 iaa_watchdog_start(struct ehci_hcd *ehci)
 179 {
 180         WARN_ON(timer_pending(&ehci->iaa_watchdog));
 181         mod_timer(&ehci->iaa_watchdog,
 182                         jiffies + msecs_to_jiffies(EHCI_IAA_MSECS));
 183 }
 184
 185 static inline void iaa_watchdog_done(struct ehci_hcd *ehci)
 186 {
 187         del_timer(&ehci->iaa_watchdog);
 188 }
 189
 190 enum ehci_timer_action {
 191         TIMER_IO_WATCHDOG,
 192         TIMER_ASYNC_SHRINK,
 193         TIMER_ASYNC_OFF,
 194 };
 195
 196 static inline void
 197 timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action)
 198 {
 199         clear_bit (action, &ehci->actions);
 200 }
 201
 202 static void free_cached_lists(struct ehci_hcd *ehci);
 203
 204 /*-------------------------------------------------------------------------*/
 205
 206 #include <linux/usb/ehci_def.h>
 207
 208 /*-------------------------------------------------------------------------*/
 209
 210 #define QTD_NEXT(ehci, dma)     cpu_to_hc32(ehci, (u32)dma)
 211
 212 /*
 213  * EHCI Specification 0.95 Section 3.5
 214  * QTD: describe data transfer components (buffer, direction, ...)
 215  * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
 216  *
 217  * These are associated only with "QH" (Queue Head) structures,
 218  * used with control, bulk, and interrupt transfers.
 219  */
 220 struct ehci_qtd {
 221         /* first part defined by EHCI spec */
 222         __hc32                  hw_next;        /* see EHCI 3.5.1 */
 223         __hc32                  hw_alt_next;    /* see EHCI 3.5.2 */
 224         __hc32                  hw_token;       /* see EHCI 3.5.3 */
 225 #define QTD_TOGGLE      (1 << 31)       /* data toggle */
 226 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
 227 #define QTD_IOC         (1 << 15)       /* interrupt on complete */
 228 #define QTD_CERR(tok)   (((tok)>>10) & 0x3)
 229 #define QTD_PID(tok)    (((tok)>>8) & 0x3)
 230 #define QTD_STS_ACTIVE  (1 << 7)        /* HC may execute this */
 231 #define QTD_STS_HALT    (1 << 6)        /* halted on error */
 232 #define QTD_STS_DBE     (1 << 5)        /* data buffer error (in HC) */
 233 #define QTD_STS_BABBLE  (1 << 4)        /* device was babbling (qtd halted) */
 234 #define QTD_STS_XACT    (1 << 3)        /* device gave illegal response */
 235 #define QTD_STS_MMF     (1 << 2)        /* incomplete split transaction */
 236 #define QTD_STS_STS     (1 << 1)        /* split transaction state */
 237 #define QTD_STS_PING    (1 << 0)        /* issue PING? */
 238
 239 #define ACTIVE_BIT(ehci)        cpu_to_hc32(ehci, QTD_STS_ACTIVE)
 240 #define HALT_BIT(ehci)          cpu_to_hc32(ehci, QTD_STS_HALT)
 241 #define STATUS_BIT(ehci)        cpu_to_hc32(ehci, QTD_STS_STS)
 242
 243         __hc32                  hw_buf [5];        /* see EHCI 3.5.4 */
 244         __hc32                  hw_buf_hi [5];        /* Appendix B */
 245
 246         /* the rest is HCD-private */
 247         dma_addr_t              qtd_dma;                /* qtd address */
 248         struct list_head        qtd_list;               /* sw qtd list */
 249         struct urb              *urb;                   /* qtd's urb */
 250         size_t                  length;                 /* length of buffer */
 251 } __attribute__ ((aligned (32)));
 252
 253 /* mask NakCnt+T in qh->hw_alt_next */
 254 #define QTD_MASK(ehci)  cpu_to_hc32 (ehci, ~0x1f)
 255
 256 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
 257
 258 /*-------------------------------------------------------------------------*/
 259
 260 /* type tag from {qh,itd,sitd,fstn}->hw_next */
 261 #define Q_NEXT_TYPE(ehci,dma)   ((dma) & cpu_to_hc32(ehci, 3 << 1))
 262
 263 /*
 264  * Now the following defines are not converted using the
 265  * cpu_to_le32() macro anymore, since we have to support
 266  * "dynamic" switching between be and le support, so that the driver
 267  * can be used on one system with SoC EHCI controller using big-endian
 268  * descriptors as well as a normal little-endian PCI EHCI controller.
 269  */
 270 /* values for that type tag */
 271 #define Q_TYPE_ITD      (0 << 1)
 272 #define Q_TYPE_QH       (1 << 1)
 273 #define Q_TYPE_SITD     (2 << 1)
 274 #define Q_TYPE_FSTN     (3 << 1)
 275
 276 /* next async queue entry, or pointer to interrupt/periodic QH */
 277 #define QH_NEXT(ehci,dma)       (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH))
 278
 279 /* for periodic/async schedules and qtd lists, mark end of list */
 280 #define EHCI_LIST_END(ehci)     cpu_to_hc32(ehci, 1) /* "null pointer" to hw */
 281
 282 /*
 283  * Entries in periodic shadow table are pointers to one of four kinds
 284  * of data structure.  That's dictated by the hardware; a type tag is
 285  * encoded in the low bits of the hardware's periodic schedule.  Use
 286  * Q_NEXT_TYPE to get the tag.
 287  *
 288  * For entries in the async schedule, the type tag always says "qh".
 289  */
 290 union ehci_shadow {
 291         struct ehci_qh          *qh;            /* Q_TYPE_QH */
 292         struct ehci_itd         *itd;           /* Q_TYPE_ITD */
 293         struct ehci_sitd        *sitd;          /* Q_TYPE_SITD */
 294         struct ehci_fstn        *fstn;          /* Q_TYPE_FSTN */
 295         __hc32                  *hw_next;       /* (all types) */
 296         void                    *ptr;
 297 };
 298
 299 /*-------------------------------------------------------------------------*/
 300
 301 /*
 302  * EHCI Specification 0.95 Section 3.6
 303  * QH: describes control/bulk/interrupt endpoints
 304  * See Fig 3-7 "Queue Head Structure Layout".
 305  *
 306  * These appear in both the async and (for interrupt) periodic schedules.
 307  */
 308
 309 /* first part defined by EHCI spec */
 310 struct ehci_qh_hw {
 311         __hc32                  hw_next;        /* see EHCI 3.6.1 */
 312         __hc32                  hw_info1;       /* see EHCI 3.6.2 */
 313 #define QH_HEAD         0x00008000
 314         __hc32                  hw_info2;        /* see EHCI 3.6.2 */
 315 #define QH_SMASK        0x000000ff
 316 #define QH_CMASK        0x0000ff00
 317 #define QH_HUBADDR      0x007f0000
 318 #define QH_HUBPORT      0x3f800000
 319 #define QH_MULT         0xc0000000
 320         __hc32                  hw_current;     /* qtd list - see EHCI 3.6.4 */
 321
 322         /* qtd overlay (hardware parts of a struct ehci_qtd) */
 323         __hc32                  hw_qtd_next;
 324         __hc32                  hw_alt_next;
 325         __hc32                  hw_token;
 326         __hc32                  hw_buf [5];
 327         __hc32                  hw_buf_hi [5];
 328 } __attribute__ ((aligned(32)));
 329
 330 struct ehci_qh {
 331         struct ehci_qh_hw       *hw;
 332         /* the rest is HCD-private */
 333         dma_addr_t              qh_dma;         /* address of qh */
 334         union ehci_shadow       qh_next;        /* ptr to qh; or periodic */
 335         struct list_head        qtd_list;       /* sw qtd list */
 336         struct ehci_qtd         *dummy;
 337         struct ehci_qh          *reclaim;       /* next to reclaim */
 338
 339         struct ehci_hcd         *ehci;
 340
 341         /*
 342          * Do NOT use atomic operations for QH refcounting. On some CPUs
 343          * (PPC7448 for example), atomic operations cannot be performed on
 344          * memory that is cache-inhibited (i.e. being used for DMA).
 345          * Spinlocks are used to protect all QH fields.
 346          */
 347         u32                     refcount;
 348         unsigned                stamp;
 349
 350         u8                      needs_rescan;   /* Dequeue during giveback */
 351         u8                      qh_state;
 352 #define QH_STATE_LINKED         1               /* HC sees this */
 353 #define QH_STATE_UNLINK         2               /* HC may still see this */
 354 #define QH_STATE_IDLE           3               /* HC doesn't see this */
 355 #define QH_STATE_UNLINK_WAIT    4               /* LINKED and on reclaim q */
 356 #define QH_STATE_COMPLETING     5               /* don't touch token.HALT */
 357
 358         u8                      xacterrs;       /* XactErr retry counter */
 359 #define QH_XACTERR_MAX          32              /* XactErr retry limit */
 360
 361         /* periodic schedule info */
 362         u8                      usecs;          /* intr bandwidth */
 363         u8                      gap_uf;         /* uframes split/csplit gap */
 364         u8                      c_usecs;        /* ... split completion bw */
 365         u16                     tt_usecs;       /* tt downstream bandwidth */
 366         unsigned short          period;         /* polling interval */
 367         unsigned short          start;          /* where polling starts */
 368 #define NO_FRAME ((unsigned short)~0)                   /* pick new start */
 369
 370         struct usb_device       *dev;           /* access to TT */
 371         unsigned                clearing_tt:1;  /* Clear-TT-Buf in progress */
 372 };
 373
 374 /*-------------------------------------------------------------------------*/
 375
 376 /* description of one iso transaction (up to 3 KB data if highspeed) */
 377 struct ehci_iso_packet {
 378         /* These will be copied to iTD when scheduling */
 379         u64                     bufp;           /* itd->hw_bufp{,_hi}[pg] |= */
 380         __hc32                  transaction;    /* itd->hw_transaction[i] |= */
 381         u8                      cross;          /* buf crosses pages */
 382         /* for full speed OUT splits */
 383         u32                     buf1;
 384 };
 385
 386 /* temporary schedule data for packets from iso urbs (both speeds)
 387  * each packet is one logical usb transaction to the device (not TT),
 388  * beginning at stream->next_uframe
 389  */
 390 struct ehci_iso_sched {
 391         struct list_head        td_list;
 392         unsigned                span;
 393         struct ehci_iso_packet  packet [0];
 394 };
 395
 396 /*
 397  * ehci_iso_stream - groups all (s)itds for this endpoint.
 398  * acts like a qh would, if EHCI had them for ISO.
 399  */
 400 struct ehci_iso_stream {
 401         /* first field matches ehci_hq, but is NULL */
 402         struct ehci_qh_hw       *hw;
 403
 404         u32                     refcount;
 405         u8                      bEndpointAddress;
 406         u8                      highspeed;
 407         struct list_head        td_list;        /* queued itds/sitds */
 408         struct list_head        free_list;      /* list of unused itds/sitds */
 409         struct usb_device       *udev;
 410         struct usb_host_endpoint *ep;
 411
 412         /* output of (re)scheduling */
 413         int                     next_uframe;
 414         __hc32                  splits;
 415
 416         /* the rest is derived from the endpoint descriptor,
 417          * trusting urb->interval == f(epdesc->bInterval) and
 418          * including the extra info for hw_bufp[0..2]
 419          */
 420         u8                      usecs, c_usecs;
 421         u16                     interval;
 422         u16                     tt_usecs;
 423         u16                     maxp;
 424         u16                     raw_mask;
 425         unsigned                bandwidth;
 426
 427         /* This is used to initialize iTD's hw_bufp fields */
 428         __hc32                  buf0;
 429         __hc32                  buf1;
 430         __hc32                  buf2;
 431
 432         /* this is used to initialize sITD's tt info */
 433         __hc32                  address;
 434 };
 435
 436 /*-------------------------------------------------------------------------*/
 437
 438 /*
 439  * EHCI Specification 0.95 Section 3.3
 440  * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
 441  *
 442  * Schedule records for high speed iso xfers
 443  */
 444 struct ehci_itd {
 445         /* first part defined by EHCI spec */
 446         __hc32                  hw_next;           /* see EHCI 3.3.1 */
 447         __hc32                  hw_transaction [8]; /* see EHCI 3.3.2 */
 448 #define EHCI_ISOC_ACTIVE        (1<<31)        /* activate transfer this slot */
 449 #define EHCI_ISOC_BUF_ERR       (1<<30)        /* Data buffer error */
 450 #define EHCI_ISOC_BABBLE        (1<<29)        /* babble detected */
 451 #define EHCI_ISOC_XACTERR       (1<<28)        /* XactErr - transaction error */
 452 #define EHCI_ITD_LENGTH(tok)    (((tok)>>16) & 0x0fff)
 453 #define EHCI_ITD_IOC            (1 << 15)       /* interrupt on complete */
 454
 455 #define ITD_ACTIVE(ehci)        cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
 456
 457         __hc32                  hw_bufp [7];    /* see EHCI 3.3.3 */
 458         __hc32                  hw_bufp_hi [7]; /* Appendix B */
 459
 460         /* the rest is HCD-private */
 461         dma_addr_t              itd_dma;        /* for this itd */
 462         union ehci_shadow       itd_next;       /* ptr to periodic q entry */
 463
 464         struct urb              *urb;
 465         struct ehci_iso_stream  *stream;        /* endpoint's queue */
 466         struct list_head        itd_list;       /* list of stream's itds */
 467
 468         /* any/all hw_transactions here may be used by that urb */
 469         unsigned                frame;          /* where scheduled */
 470         unsigned                pg;
 471         unsigned                index[8];       /* in urb->iso_frame_desc */
 472 } __attribute__ ((aligned (32)));
 473
 474 /*-------------------------------------------------------------------------*/
 475
 476 /*
 477  * EHCI Specification 0.95 Section 3.4
 478  * siTD, aka split-transaction isochronous Transfer Descriptor
 479  *       ... describe full speed iso xfers through TT in hubs
 480  * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
 481  */
 482 struct ehci_sitd {
 483         /* first part defined by EHCI spec */
 484         __hc32                  hw_next;
 485 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
 486         __hc32                  hw_fullspeed_ep;        /* EHCI table 3-9 */
 487         __hc32                  hw_uframe;              /* EHCI table 3-10 */
 488         __hc32                  hw_results;             /* EHCI table 3-11 */
 489 #define SITD_IOC        (1 << 31)       /* interrupt on completion */
 490 #define SITD_PAGE       (1 << 30)       /* buffer 0/1 */
 491 #define SITD_LENGTH(x)  (0x3ff & ((x)>>16))
 492 #define SITD_STS_ACTIVE (1 << 7)        /* HC may execute this */
 493 #define SITD_STS_ERR    (1 << 6)        /* error from TT */
 494 #define SITD_STS_DBE    (1 << 5)        /* data buffer error (in HC) */
 495 #define SITD_STS_BABBLE (1 << 4)        /* device was babbling */
 496 #define SITD_STS_XACT   (1 << 3)        /* illegal IN response */
 497 #define SITD_STS_MMF    (1 << 2)        /* incomplete split transaction */
 498 #define SITD_STS_STS    (1 << 1)        /* split transaction state */
 499
 500 #define SITD_ACTIVE(ehci)       cpu_to_hc32(ehci, SITD_STS_ACTIVE)
 501
 502         __hc32                  hw_buf [2];             /* EHCI table 3-12 */
 503         __hc32                  hw_backpointer;         /* EHCI table 3-13 */
 504         __hc32                  hw_buf_hi [2];          /* Appendix B */
 505
 506         /* the rest is HCD-private */
 507         dma_addr_t              sitd_dma;
 508         union ehci_shadow       sitd_next;      /* ptr to periodic q entry */
 509
 510         struct urb              *urb;
 511         struct ehci_iso_stream  *stream;        /* endpoint's queue */
 512         struct list_head        sitd_list;      /* list of stream's sitds */
 513         unsigned                frame;
 514         unsigned                index;
 515 } __attribute__ ((aligned (32)));
 516
 517 /*-------------------------------------------------------------------------*/
 518
 519 /*
 520  * EHCI Specification 0.96 Section 3.7
 521  * Periodic Frame Span Traversal Node (FSTN)
 522  *
 523  * Manages split interrupt transactions (using TT) that span frame boundaries
 524  * into uframes 0/1; see 4.12.2.2.  In those uframes, a "save place" FSTN
 525  * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
 526  * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
 527  */
 528 struct ehci_fstn {
 529         __hc32                  hw_next;        /* any periodic q entry */
 530         __hc32                  hw_prev;        /* qh or EHCI_LIST_END */
 531
 532         /* the rest is HCD-private */
 533         dma_addr_t              fstn_dma;
 534         union ehci_shadow       fstn_next;      /* ptr to periodic q entry */
 535 } __attribute__ ((aligned (32)));
 536
 537 /*-------------------------------------------------------------------------*/
 538
 539 /* Prepare the PORTSC wakeup flags during controller suspend/resume */
 540
 541 #define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup)      \
 542                 ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup);
 543
 544 #define ehci_prepare_ports_for_controller_resume(ehci)                  \
 545                 ehci_adjust_port_wakeup_flags(ehci, false, false);
 546
 547 /*-------------------------------------------------------------------------*/
 548
 549 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
 550
 551 /*
 552  * Some EHCI controllers have a Transaction Translator built into the
 553  * root hub. This is a non-standard feature.  Each controller will need
 554  * to add code to the following inline functions, and call them as
 555  * needed (mostly in root hub code).
 556  */
 557
 558 #define ehci_is_TDI(e)                  (ehci_to_hcd(e)->has_tt)
 559
 560 /* Returns the speed of a device attached to a port on the root hub. */
 561 static inline unsigned int
 562 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
 563 {
 564         if (ehci_is_TDI(ehci)) {
 565                 switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {
 566                 case 0:
 567                         return 0;
 568                 case 1:
 569                         return USB_PORT_STAT_LOW_SPEED;
 570                 case 2:
 571                 default:
 572                         return USB_PORT_STAT_HIGH_SPEED;
 573                 }
 574         }
 575         return USB_PORT_STAT_HIGH_SPEED;
 576 }
 577
 578 #else
 579
 580 #define ehci_is_TDI(e)                  (0)
 581
 582 #define ehci_port_speed(ehci, portsc)   USB_PORT_STAT_HIGH_SPEED
 583 #endif
 584
 585 /*-------------------------------------------------------------------------*/
 586
 587 #ifdef CONFIG_PPC_83xx
 588 /* Some Freescale processors have an erratum in which the TT
 589  * port number in the queue head was 0..N-1 instead of 1..N.
 590  */
 591 #define ehci_has_fsl_portno_bug(e)              ((e)->has_fsl_port_bug)
 592 #else
 593 #define ehci_has_fsl_portno_bug(e)              (0)
 594 #endif
 595
 596 /*
 597  * While most USB host controllers implement their registers in
 598  * little-endian format, a minority (celleb companion chip) implement
 599  * them in big endian format.
 600  *
 601  * This attempts to support either format at compile time without a
 602  * runtime penalty, or both formats with the additional overhead
 603  * of checking a flag bit.
 604  */
 605
 606 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 607 #define ehci_big_endian_mmio(e)         ((e)->big_endian_mmio)
 608 #else
 609 #define ehci_big_endian_mmio(e)         0
 610 #endif
 611
 612 /*
 613  * Big-endian read/write functions are arch-specific.
 614  * Other arches can be added if/when they're needed.
 615  */
 616 #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX)
 617 #define readl_be(addr)          __raw_readl((__force unsigned *)addr)
 618 #define writel_be(val, addr)    __raw_writel(val, (__force unsigned *)addr)
 619 #endif
 620
 621 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
 622                 __u32 __iomem * regs)
 623 {
 624 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 625         return ehci_big_endian_mmio(ehci) ?
 626                 readl_be(regs) :
 627                 readl(regs);
 628 #else
 629         return readl(regs);
 630 #endif
 631 }
 632
 633 static inline void ehci_writel(const struct ehci_hcd *ehci,
 634                 const unsigned int val, __u32 __iomem *regs)
 635 {
 636 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 637         ehci_big_endian_mmio(ehci) ?
 638                 writel_be(val, regs) :
 639                 writel(val, regs);
 640 #else
 641         writel(val, regs);
 642 #endif
 643 }
 644
 645 /*
 646  * On certain ppc-44x SoC there is a HW issue, that could only worked around with
 647  * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch.
 648  * Other common bits are dependent on has_amcc_usb23 quirk flag.
 649  */
 650 #ifdef CONFIG_44x
 651 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
 652 {
 653         u32 hc_control;
 654
 655         hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS);
 656         if (operational)
 657                 hc_control |= OHCI_USB_OPER;
 658         else
 659                 hc_control |= OHCI_USB_SUSPEND;
 660
 661         writel_be(hc_control, ehci->ohci_hcctrl_reg);
 662         (void) readl_be(ehci->ohci_hcctrl_reg);
 663 }
 664 #else
 665 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
 666 { }
 667 #endif
 668
 669 /*-------------------------------------------------------------------------*/
 670
 671 /*
 672  * The AMCC 440EPx not only implements its EHCI registers in big-endian
 673  * format, but also its DMA data structures (descriptors).
 674  *
 675  * EHCI controllers accessed through PCI work normally (little-endian
 676  * everywhere), so we won't bother supporting a BE-only mode for now.
 677  */
 678 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
 679 #define ehci_big_endian_desc(e)         ((e)->big_endian_desc)
 680
 681 /* cpu to ehci */
 682 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
 683 {
 684         return ehci_big_endian_desc(ehci)
 685                 ? (__force __hc32)cpu_to_be32(x)
 686                 : (__force __hc32)cpu_to_le32(x);
 687 }
 688
 689 /* ehci to cpu */
 690 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
 691 {
 692         return ehci_big_endian_desc(ehci)
 693                 ? be32_to_cpu((__force __be32)x)
 694                 : le32_to_cpu((__force __le32)x);
 695 }
 696
 697 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
 698 {
 699         return ehci_big_endian_desc(ehci)
 700                 ? be32_to_cpup((__force __be32 *)x)
 701                 : le32_to_cpup((__force __le32 *)x);
 702 }
 703
 704 #else
 705
 706 /* cpu to ehci */
 707 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
 708 {
 709         return cpu_to_le32(x);
 710 }
 711
 712 /* ehci to cpu */
 713 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
 714 {
 715         return le32_to_cpu(x);
 716 }
 717
 718 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
 719 {
 720         return le32_to_cpup(x);
 721 }
 722
 723 #endif
 724
 725 /*-------------------------------------------------------------------------*/
 726
 727 #ifndef DEBUG
 728 #define STUB_DEBUG_FILES
 729 #endif  /* DEBUG */
 730
 731 /*-------------------------------------------------------------------------*/
 732
 733 #endif /* __LINUX_EHCI_HCD_H */