arch/powerpc/platforms/86xx/mpc8610_hpcd.c

   1 /*
   2  * MPC8610 HPCD board specific routines
   3  *
   4  * Initial author: Xianghua Xiao <x.xiao@freescale.com>
   5  * Recode: Jason Jin <jason.jin@freescale.com>
   6  *         York Sun <yorksun@freescale.com>
   7  *
   8  * Rewrite the interrupt routing. remove the 8259PIC support,
   9  * All the integrated device in ULI use sideband interrupt.
  10  *
  11  * Copyright 2008 Freescale Semiconductor Inc.
  12  *
  13  * This program is free software; you can redistribute  it and/or modify it
  14  * under  the terms of  the GNU General  Public License as published by the
  15  * Free Software Foundation;  either version 2 of the  License, or (at your
  16  * option) any later version.
  17  */
  18
  19 #include <linux/stddef.h>
  20 #include <linux/kernel.h>
  21 #include <linux/pci.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/kdev_t.h>
  24 #include <linux/delay.h>
  25 #include <linux/seq_file.h>
  26 #include <linux/of.h>
  27
  28 #include <asm/system.h>
  29 #include <asm/time.h>
  30 #include <asm/machdep.h>
  31 #include <asm/pci-bridge.h>
  32 #include <asm/prom.h>
  33 #include <mm/mmu_decl.h>
  34 #include <asm/udbg.h>
  35
  36 #include <asm/mpic.h>
  37
  38 #include <linux/of_platform.h>
  39 #include <sysdev/fsl_pci.h>
  40 #include <sysdev/fsl_soc.h>
  41 #include <sysdev/simple_gpio.h>
  42
  43 #include "mpc86xx.h"
  44
  45 static struct device_node *pixis_node;
  46 static unsigned char *pixis_bdcfg0, *pixis_arch;
  47
  48 #ifdef CONFIG_SUSPEND
  49 static irqreturn_t mpc8610_sw9_irq(int irq, void *data)
  50 {
  51         pr_debug("%s: PIXIS' event (sw9/wakeup) IRQ handled\n", __func__);
  52         return IRQ_HANDLED;
  53 }
  54
  55 static void __init mpc8610_suspend_init(void)
  56 {
  57         int irq;
  58         int ret;
  59
  60         if (!pixis_node)
  61                 return;
  62
  63         irq = irq_of_parse_and_map(pixis_node, 0);
  64         if (!irq) {
  65                 pr_err("%s: can't map pixis event IRQ.\n", __func__);
  66                 return;
  67         }
  68
  69         ret = request_irq(irq, mpc8610_sw9_irq, 0, "sw9/wakeup", NULL);
  70         if (ret) {
  71                 pr_err("%s: can't request pixis event IRQ: %d\n",
  72                        __func__, ret);
  73                 irq_dispose_mapping(irq);
  74         }
  75
  76         enable_irq_wake(irq);
  77 }
  78 #else
  79 static inline void mpc8610_suspend_init(void) { }
  80 #endif /* CONFIG_SUSPEND */
  81
  82 static struct of_device_id __initdata mpc8610_ids[] = {
  83         { .compatible = "fsl,mpc8610-immr", },
  84         { .compatible = "fsl,mpc8610-guts", },
  85         { .compatible = "simple-bus", },
  86         /* So that the DMA channel nodes can be probed individually: */
  87         { .compatible = "fsl,eloplus-dma", },
  88         {}
  89 };
  90
  91 static int __init mpc8610_declare_of_platform_devices(void)
  92 {
  93         /* Firstly, register PIXIS GPIOs. */
  94         simple_gpiochip_init("fsl,fpga-pixis-gpio-bank");
  95
  96         /* Enable wakeup on PIXIS' event IRQ. */
  97         mpc8610_suspend_init();
  98
  99         /* Without this call, the SSI device driver won't get probed. */
 100         of_platform_bus_probe(NULL, mpc8610_ids, NULL);
 101
 102         return 0;
 103 }
 104 machine_device_initcall(mpc86xx_hpcd, mpc8610_declare_of_platform_devices);
 105
 106 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
 107
 108 static u32 get_busfreq(void)
 109 {
 110         struct device_node *node;
 111
 112         u32 fs_busfreq = 0;
 113         node = of_find_node_by_type(NULL, "cpu");
 114         if (node) {
 115                 unsigned int size;
 116                 const unsigned int *prop =
 117                         of_get_property(node, "bus-frequency", &size);
 118                 if (prop)
 119                         fs_busfreq = *prop;
 120                 of_node_put(node);
 121         };
 122         return fs_busfreq;
 123 }
 124
 125 unsigned int mpc8610hpcd_get_pixel_format(unsigned int bits_per_pixel,
 126                                                 int monitor_port)
 127 {
 128         static const unsigned long pixelformat[][3] = {
 129                 {0x88882317, 0x88083218, 0x65052119},
 130                 {0x88883316, 0x88082219, 0x65053118},
 131         };
 132         unsigned int pix_fmt, arch_monitor;
 133
 134         arch_monitor = ((*pixis_arch == 0x01) && (monitor_port == 0))? 0 : 1;
 135                 /* DVI port for board version 0x01 */
 136
 137         if (bits_per_pixel == 32)
 138                 pix_fmt = pixelformat[arch_monitor][0];
 139         else if (bits_per_pixel == 24)
 140                 pix_fmt = pixelformat[arch_monitor][1];
 141         else if (bits_per_pixel == 16)
 142                 pix_fmt = pixelformat[arch_monitor][2];
 143         else
 144                 pix_fmt = pixelformat[1][0];
 145
 146         return pix_fmt;
 147 }
 148
 149 void mpc8610hpcd_set_gamma_table(int monitor_port, char *gamma_table_base)
 150 {
 151         int i;
 152         if (monitor_port == 2) {                /* dual link LVDS */
 153                 for (i = 0; i < 256*3; i++)
 154                         gamma_table_base[i] = (gamma_table_base[i] << 2) |
 155                                          ((gamma_table_base[i] >> 6) & 0x03);
 156         }
 157 }
 158
 159 #define PX_BRDCFG0_DVISEL       (1 << 3)
 160 #define PX_BRDCFG0_DLINK        (1 << 4)
 161 #define PX_BRDCFG0_DIU_MASK     (PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK)
 162
 163 void mpc8610hpcd_set_monitor_port(int monitor_port)
 164 {
 165         static const u8 bdcfg[] = {
 166                 PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK,
 167                 PX_BRDCFG0_DLINK,
 168                 0,
 169         };
 170
 171         if (monitor_port < 3)
 172                 clrsetbits_8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK,
 173                              bdcfg[monitor_port]);
 174 }
 175
 176 void mpc8610hpcd_set_pixel_clock(unsigned int pixclock)
 177 {
 178         u32 __iomem *clkdvdr;
 179         u32 temp;
 180         /* variables for pixel clock calcs */
 181         ulong  bestval, bestfreq, speed_ccb, minpixclock, maxpixclock;
 182         ulong pixval;
 183         long err;
 184         int i;
 185
 186         clkdvdr = ioremap(get_immrbase() + 0xe0800, sizeof(u32));
 187         if (!clkdvdr) {
 188                 printk(KERN_ERR "Err: can't map clock divider register!\n");
 189                 return;
 190         }
 191
 192         /* Pixel Clock configuration */
 193         pr_debug("DIU: Bus Frequency = %d\n", get_busfreq());
 194         speed_ccb = get_busfreq();
 195
 196         /* Calculate the pixel clock with the smallest error */
 197         /* calculate the following in steps to avoid overflow */
 198         pr_debug("DIU pixclock in ps - %d\n", pixclock);
 199         temp = 1000000000/pixclock;
 200         temp *= 1000;
 201         pixclock = temp;
 202         pr_debug("DIU pixclock freq - %u\n", pixclock);
 203
 204         temp = pixclock * 5 / 100;
 205         pr_debug("deviation = %d\n", temp);
 206         minpixclock = pixclock - temp;
 207         maxpixclock = pixclock + temp;
 208         pr_debug("DIU minpixclock - %lu\n", minpixclock);
 209         pr_debug("DIU maxpixclock - %lu\n", maxpixclock);
 210         pixval = speed_ccb/pixclock;
 211         pr_debug("DIU pixval = %lu\n", pixval);
 212
 213         err = 100000000;
 214         bestval = pixval;
 215         pr_debug("DIU bestval = %lu\n", bestval);
 216
 217         bestfreq = 0;
 218         for (i = -1; i <= 1; i++) {
 219                 temp = speed_ccb / ((pixval+i) + 1);
 220                 pr_debug("DIU test pixval i= %d, pixval=%lu, temp freq. = %u\n",
 221                                                         i, pixval, temp);
 222                 if ((temp < minpixclock) || (temp > maxpixclock))
 223                         pr_debug("DIU exceeds monitor range (%lu to %lu)\n",
 224                                 minpixclock, maxpixclock);
 225                 else if (abs(temp - pixclock) < err) {
 226                   pr_debug("Entered the else if block %d\n", i);
 227                         err = abs(temp - pixclock);
 228                         bestval = pixval+i;
 229                         bestfreq = temp;
 230                 }
 231         }
 232
 233         pr_debug("DIU chose = %lx\n", bestval);
 234         pr_debug("DIU error = %ld\n NomPixClk ", err);
 235         pr_debug("DIU: Best Freq = %lx\n", bestfreq);
 236         /* Modify PXCLK in GUTS CLKDVDR */
 237         pr_debug("DIU: Current value of CLKDVDR = 0x%08x\n", (*clkdvdr));
 238         temp = (*clkdvdr) & 0x2000FFFF;
 239         *clkdvdr = temp;                /* turn off clock */
 240         *clkdvdr = temp | 0x80000000 | (((bestval) & 0x1F) << 16);
 241         pr_debug("DIU: Modified value of CLKDVDR = 0x%08x\n", (*clkdvdr));
 242         iounmap(clkdvdr);
 243 }
 244
 245 ssize_t mpc8610hpcd_show_monitor_port(int monitor_port, char *buf)
 246 {
 247         return snprintf(buf, PAGE_SIZE,
 248                         "%c0 - DVI\n"
 249                         "%c1 - Single link LVDS\n"
 250                         "%c2 - Dual link LVDS\n",
 251                         monitor_port == 0 ? '*' : ' ',
 252                         monitor_port == 1 ? '*' : ' ',
 253                         monitor_port == 2 ? '*' : ' ');
 254 }
 255
 256 int mpc8610hpcd_set_sysfs_monitor_port(int val)
 257 {
 258         return val < 3 ? val : 0;
 259 }
 260
 261 #endif
 262
 263 static void __init mpc86xx_hpcd_setup_arch(void)
 264 {
 265         struct resource r;
 266         struct device_node *np;
 267         unsigned char *pixis;
 268
 269         if (ppc_md.progress)
 270                 ppc_md.progress("mpc86xx_hpcd_setup_arch()", 0);
 271
 272 #ifdef CONFIG_PCI
 273         for_each_node_by_type(np, "pci") {
 274                 if (of_device_is_compatible(np, "fsl,mpc8610-pci")
 275                     || of_device_is_compatible(np, "fsl,mpc8641-pcie")) {
 276                         struct resource rsrc;
 277                         of_address_to_resource(np, 0, &rsrc);
 278                         if ((rsrc.start & 0xfffff) == 0xa000)
 279                                 fsl_add_bridge(np, 1);
 280                         else
 281                                 fsl_add_bridge(np, 0);
 282                 }
 283         }
 284 #endif
 285 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
 286         diu_ops.get_pixel_format        = mpc8610hpcd_get_pixel_format;
 287         diu_ops.set_gamma_table         = mpc8610hpcd_set_gamma_table;
 288         diu_ops.set_monitor_port        = mpc8610hpcd_set_monitor_port;
 289         diu_ops.set_pixel_clock         = mpc8610hpcd_set_pixel_clock;
 290         diu_ops.show_monitor_port       = mpc8610hpcd_show_monitor_port;
 291         diu_ops.set_sysfs_monitor_port  = mpc8610hpcd_set_sysfs_monitor_port;
 292 #endif
 293
 294         pixis_node = of_find_compatible_node(NULL, NULL, "fsl,fpga-pixis");
 295         if (pixis_node) {
 296                 of_address_to_resource(pixis_node, 0, &r);
 297                 of_node_put(pixis_node);
 298                 pixis = ioremap(r.start, 32);
 299                 if (!pixis) {
 300                         printk(KERN_ERR "Err: can't map FPGA cfg register!\n");
 301                         return;
 302                 }
 303                 pixis_bdcfg0 = pixis + 8;
 304                 pixis_arch = pixis + 1;
 305         } else
 306                 printk(KERN_ERR "Err: "
 307                                 "can't find device node 'fsl,fpga-pixis'\n");
 308
 309         printk("MPC86xx HPCD board from Freescale Semiconductor\n");
 310 }
 311
 312 /*
 313  * Called very early, device-tree isn't unflattened
 314  */
 315 static int __init mpc86xx_hpcd_probe(void)
 316 {
 317         unsigned long root = of_get_flat_dt_root();
 318
 319         if (of_flat_dt_is_compatible(root, "fsl,MPC8610HPCD"))
 320                 return 1;       /* Looks good */
 321
 322         return 0;
 323 }
 324
 325 static long __init mpc86xx_time_init(void)
 326 {
 327         unsigned int temp;
 328
 329         /* Set the time base to zero */
 330         mtspr(SPRN_TBWL, 0);
 331         mtspr(SPRN_TBWU, 0);
 332
 333         temp = mfspr(SPRN_HID0);
 334         temp |= HID0_TBEN;
 335         mtspr(SPRN_HID0, temp);
 336         asm volatile("isync");
 337
 338         return 0;
 339 }
 340
 341 define_machine(mpc86xx_hpcd) {
 342         .name                   = "MPC86xx HPCD",
 343         .probe                  = mpc86xx_hpcd_probe,
 344         .setup_arch             = mpc86xx_hpcd_setup_arch,
 345         .init_IRQ               = mpc86xx_init_irq,
 346         .get_irq                = mpic_get_irq,
 347         .restart                = fsl_rstcr_restart,
 348         .time_init              = mpc86xx_time_init,
 349         .calibrate_decr         = generic_calibrate_decr,
 350         .progress               = udbg_progress,
 351         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 352 };