1 menu "Platform support"
3 source "arch/powerpc/platforms/pseries/Kconfig"
4 source "arch/powerpc/platforms/iseries/Kconfig"
5 source "arch/powerpc/platforms/chrp/Kconfig"
6 source "arch/powerpc/platforms/512x/Kconfig"
7 source "arch/powerpc/platforms/52xx/Kconfig"
8 source "arch/powerpc/platforms/powermac/Kconfig"
9 source "arch/powerpc/platforms/prep/Kconfig"
10 source "arch/powerpc/platforms/maple/Kconfig"
11 source "arch/powerpc/platforms/pasemi/Kconfig"
12 source "arch/powerpc/platforms/ps3/Kconfig"
13 source "arch/powerpc/platforms/cell/Kconfig"
14 source "arch/powerpc/platforms/8xx/Kconfig"
15 source "arch/powerpc/platforms/82xx/Kconfig"
16 source "arch/powerpc/platforms/83xx/Kconfig"
17 source "arch/powerpc/platforms/85xx/Kconfig"
18 source "arch/powerpc/platforms/86xx/Kconfig"
19 source "arch/powerpc/platforms/embedded6xx/Kconfig"
20 source "arch/powerpc/platforms/44x/Kconfig"
21 source "arch/powerpc/platforms/40x/Kconfig"
22 source "arch/powerpc/platforms/amigaone/Kconfig"
23 source "arch/powerpc/platforms/wsp/Kconfig"
26 bool "KVM Guest support"
29 This option enables various optimizations for running under the KVM
30 hypervisor. Overhead for the kernel when not running inside KVM should
33 In case of doubt, say Y
37 depends on 6xx || PPC64
39 Support for running natively on the hardware, i.e. without
40 a hypervisor. This option is not user-selectable but should
41 be selected by all platforms that need it.
43 config PPC_OF_BOOT_TRAMPOLINE
44 bool "Support booting from Open Firmware or yaboot"
45 depends on 6xx || PPC64
48 Support from booting from Open Firmware or yaboot using an
49 Open Firmware client interface. This enables the kernel to
50 communicate with open firmware to retrieve system information
51 such as the device tree.
53 In case of doubt, say Y
55 config UDBG_RTAS_CONSOLE
56 bool "RTAS based debug console"
60 config PPC_SMP_MUXED_IPI
63 Select this opton if your platform supports SMP and your
64 interrupt controller provides less than 4 interrupts to each
65 cpu. This will enable the generic code to multiplex the 4
66 messages on to one ipi.
69 bool "BEAT based debug console"
98 config RTAS_ERROR_LOGGING
103 config PPC_RTAS_DAEMON
109 bool "Proc interface to RTAS"
114 tristate "Firmware flash interface"
115 depends on PPC64 && RTAS_PROC
121 config MPIC_U3_HT_IRQS
125 config MPIC_BROKEN_REGREAD
129 This option enables a MPIC driver workaround for some chips
130 that have a bug that causes some interrupt source information
131 to not read back properly. It is safe to use on other chips as
132 well, but enabling it uses about 8KB of memory to keep copies
133 of the register contents in software.
136 depends on PPC_PSERIES || PPC_ISERIES
141 depends on PPC_PSERIES
142 bool "Support for GX bus based adapters"
144 Bus device driver for GX bus based adapters.
158 config PPC_INDIRECT_IO
162 config PPC_INDIRECT_PIO
164 select PPC_INDIRECT_IO
166 config PPC_INDIRECT_MMIO
168 select PPC_INDIRECT_IO
170 config PPC_IO_WORKAROUNDS
176 source "drivers/cpufreq/Kconfig"
178 menu "CPU Frequency drivers"
182 bool "Support for Apple PowerBooks"
183 depends on ADB_PMU && PPC32
184 select CPU_FREQ_TABLE
186 This adds support for frequency switching on Apple PowerBooks,
187 this currently includes some models of iBook & Titanium
190 config CPU_FREQ_PMAC64
191 bool "Support for some Apple G5s"
192 depends on PPC_PMAC && PPC64
193 select CPU_FREQ_TABLE
195 This adds support for frequency switching on Apple iMac G5,
196 and some of the more recent desktop G5 machines as well.
198 config PPC_PASEMI_CPUFREQ
199 bool "Support for PA Semi PWRficient"
200 depends on PPC_PASEMI
202 select CPU_FREQ_TABLE
204 This adds the support for frequency switching on PA Semi
205 PWRficient processors.
209 config PPC601_SYNC_FIX
210 bool "Workarounds for PPC601 bugs"
211 depends on 6xx && (PPC_PREP || PPC_PMAC)
213 Some versions of the PPC601 (the first PowerPC chip) have bugs which
214 mean that extra synchronization instructions are required near
215 certain instructions, typically those that make major changes to the
216 CPU state. These extra instructions reduce performance slightly.
217 If you say N here, these extra instructions will not be included,
218 resulting in a kernel which will run faster but may not run at all
219 on some systems with the PPC601 chip.
221 If in doubt, say Y here.
224 bool "On-chip CPU temperature sensor support"
227 G3 and G4 processors have an on-chip temperature sensor called the
228 'Thermal Assist Unit (TAU)', which, in theory, can measure the on-die
229 temperature within 2-4 degrees Celsius. This option shows the current
230 on-die temperature in /proc/cpuinfo if the cpu supports it.
232 Unfortunately, on some chip revisions, this sensor is very inaccurate
233 and in many cases, does not work at all, so don't assume the cpu
234 temp is actually what /proc/cpuinfo says it is.
237 bool "Interrupt driven TAU driver (DANGEROUS)"
240 The TAU supports an interrupt driven mode which causes an interrupt
241 whenever the temperature goes out of range. This is the fastest way
242 to get notified the temp has exceeded a range. With this option off,
243 a timer is used to re-check the temperature periodically.
245 However, on some cpus it appears that the TAU interrupt hardware
246 is buggy and can cause a situation which would lead unexplained hard
249 Unless you are extending the TAU driver, or enjoy kernel/hardware
250 debugging, leave this option off.
253 bool "Average high and low temp"
256 The TAU hardware can compare the temperature to an upper and lower
257 bound. The default behavior is to show both the upper and lower
258 bound in /proc/cpuinfo. If the range is large, the temperature is
259 either changing a lot, or the TAU hardware is broken (likely on some
260 G4's). If the range is small (around 4 degrees), the temperature is
261 relatively stable. If you say Y here, a single temperature value,
262 halfway between the upper and lower bounds, will be reported in
265 If in doubt, say N here.
268 bool "Freescale QUICC Engine (QE) Support"
273 The QUICC Engine (QE) is a new generation of communications
274 coprocessors on Freescale embedded CPUs (akin to CPM in older chips).
275 Selecting this option means that you wish to build a kernel
276 for a machine with a QE coprocessor.
279 bool "QE GPIO support"
280 depends on QUICC_ENGINE
282 select ARCH_REQUIRE_GPIOLIB
284 Say Y here if you're going to use hardware that connects to the
288 bool "Enable support for the CPM2 (Communications Processor Module)"
289 depends on (FSL_SOC_BOOKE && PPC32) || 8260
292 select PPC_PCI_CHOICE
293 select ARCH_REQUIRE_GPIOLIB
296 The CPM2 (Communications Processor Module) is a coprocessor on
297 embedded CPUs made by Freescale. Selecting this option means that
298 you wish to build a kernel for a machine with a CPM2 coprocessor
299 on it (826x, 827x, 8560).
302 tristate "Axon DDR2 memory device driver"
303 depends on PPC_IBM_CELL_BLADE && BLOCK
306 It registers one block device per Axon's DDR2 memory bank found
307 on a system. Block devices are called axonram?, their major and
308 minor numbers are available in /proc/devices, /proc/partitions or
309 in /sys/block/axonram?/dev.
314 select GENERIC_ISA_DMA
316 Supports for the ULI1575 PCIe south bridge that exists on some
317 Freescale reference boards. The boards all use the ULI in pretty
327 Uses information from the OF or flattened device tree to instantiate
328 platform devices for direct mapped RTC chips like the DS1742 or DS1743.
330 source "arch/powerpc/sysdev/bestcomm/Kconfig"
333 bool "MPC512x/MPC8xxx GPIO support"
334 depends on PPC_MPC512x || PPC_MPC831x || PPC_MPC834x || PPC_MPC837x || \
335 FSL_SOC_BOOKE || PPC_86xx
337 select ARCH_REQUIRE_GPIOLIB
339 Say Y here if you're going to use hardware that connects to the
340 MPC512x/831x/834x/837x/8572/8610 GPIOs.
343 bool "Support for simple, memory-mapped GPIO controllers"
346 select ARCH_REQUIRE_GPIOLIB
348 Say Y here to support simple, memory-mapped GPIO controllers.
349 These are usually BCSRs used to control board's switches, LEDs,
350 chip-selects, Ethernet/USB PHY's power and various other small
351 on-board peripherals.
353 config MCU_MPC8349EMITX
354 tristate "MPC8349E-mITX MCU driver"
355 depends on I2C && PPC_83xx
357 select ARCH_REQUIRE_GPIOLIB
359 Say Y here to enable soft power-off functionality on the Freescale
360 boards with the MPC8349E-mITX-compatible MCU chips. This driver will
361 also register MCU GPIOs with the generic GPIO API, so you'll able
362 to use MCU pins as GPIOs.
365 bool "Xilinx PCI host bridge support"
366 depends on PCI && XILINX_VIRTEX