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[linux-2.6/next.git] / arch / s390 / include / asm / pgtable.h
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1 /*
2 * include/asm-s390/pgtable.h
4 * S390 version
5 * Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 * Author(s): Hartmut Penner (hp@de.ibm.com)
7 * Ulrich Weigand (weigand@de.ibm.com)
8 * Martin Schwidefsky (schwidefsky@de.ibm.com)
10 * Derived from "include/asm-i386/pgtable.h"
13 #ifndef _ASM_S390_PGTABLE_H
14 #define _ASM_S390_PGTABLE_H
17 * The Linux memory management assumes a three-level page table setup. For
18 * s390 31 bit we "fold" the mid level into the top-level page table, so
19 * that we physically have the same two-level page table as the s390 mmu
20 * expects in 31 bit mode. For s390 64 bit we use three of the five levels
21 * the hardware provides (region first and region second tables are not
22 * used).
24 * The "pgd_xxx()" functions are trivial for a folded two-level
25 * setup: the pgd is never bad, and a pmd always exists (as it's folded
26 * into the pgd entry)
28 * This file contains the functions and defines necessary to modify and use
29 * the S390 page table tree.
31 #ifndef __ASSEMBLY__
32 #include <linux/sched.h>
33 #include <linux/mm_types.h>
34 #include <asm/bug.h>
35 #include <asm/page.h>
37 extern pgd_t swapper_pg_dir[] __attribute__ ((aligned (4096)));
38 extern void paging_init(void);
39 extern void vmem_map_init(void);
40 extern void fault_init(void);
43 * The S390 doesn't have any external MMU info: the kernel page
44 * tables contain all the necessary information.
46 #define update_mmu_cache(vma, address, ptep) do { } while (0)
49 * ZERO_PAGE is a global shared page that is always zero; used
50 * for zero-mapped memory areas etc..
53 extern unsigned long empty_zero_page;
54 extern unsigned long zero_page_mask;
56 #define ZERO_PAGE(vaddr) \
57 (virt_to_page((void *)(empty_zero_page + \
58 (((unsigned long)(vaddr)) &zero_page_mask))))
60 #define is_zero_pfn is_zero_pfn
61 static inline int is_zero_pfn(unsigned long pfn)
63 extern unsigned long zero_pfn;
64 unsigned long offset_from_zero_pfn = pfn - zero_pfn;
65 return offset_from_zero_pfn <= (zero_page_mask >> PAGE_SHIFT);
68 #define my_zero_pfn(addr) page_to_pfn(ZERO_PAGE(addr))
70 #endif /* !__ASSEMBLY__ */
73 * PMD_SHIFT determines the size of the area a second-level page
74 * table can map
75 * PGDIR_SHIFT determines what a third-level page table entry can map
77 #ifndef __s390x__
78 # define PMD_SHIFT 20
79 # define PUD_SHIFT 20
80 # define PGDIR_SHIFT 20
81 #else /* __s390x__ */
82 # define PMD_SHIFT 20
83 # define PUD_SHIFT 31
84 # define PGDIR_SHIFT 42
85 #endif /* __s390x__ */
87 #define PMD_SIZE (1UL << PMD_SHIFT)
88 #define PMD_MASK (~(PMD_SIZE-1))
89 #define PUD_SIZE (1UL << PUD_SHIFT)
90 #define PUD_MASK (~(PUD_SIZE-1))
91 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
92 #define PGDIR_MASK (~(PGDIR_SIZE-1))
95 * entries per page directory level: the S390 is two-level, so
96 * we don't really have any PMD directory physically.
97 * for S390 segment-table entries are combined to one PGD
98 * that leads to 1024 pte per pgd
100 #define PTRS_PER_PTE 256
101 #ifndef __s390x__
102 #define PTRS_PER_PMD 1
103 #define PTRS_PER_PUD 1
104 #else /* __s390x__ */
105 #define PTRS_PER_PMD 2048
106 #define PTRS_PER_PUD 2048
107 #endif /* __s390x__ */
108 #define PTRS_PER_PGD 2048
110 #define FIRST_USER_ADDRESS 0
112 #define pte_ERROR(e) \
113 printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e))
114 #define pmd_ERROR(e) \
115 printk("%s:%d: bad pmd %p.\n", __FILE__, __LINE__, (void *) pmd_val(e))
116 #define pud_ERROR(e) \
117 printk("%s:%d: bad pud %p.\n", __FILE__, __LINE__, (void *) pud_val(e))
118 #define pgd_ERROR(e) \
119 printk("%s:%d: bad pgd %p.\n", __FILE__, __LINE__, (void *) pgd_val(e))
121 #ifndef __ASSEMBLY__
123 * The vmalloc area will always be on the topmost area of the kernel
124 * mapping. We reserve 96MB (31bit) / 128GB (64bit) for vmalloc,
125 * which should be enough for any sane case.
126 * By putting vmalloc at the top, we maximise the gap between physical
127 * memory and vmalloc to catch misplaced memory accesses. As a side
128 * effect, this also makes sure that 64 bit module code cannot be used
129 * as system call address.
132 extern unsigned long VMALLOC_START;
134 #ifndef __s390x__
135 #define VMALLOC_SIZE (96UL << 20)
136 #define VMALLOC_END 0x7e000000UL
137 #define VMEM_MAP_END 0x80000000UL
138 #else /* __s390x__ */
139 #define VMALLOC_SIZE (128UL << 30)
140 #define VMALLOC_END 0x3e000000000UL
141 #define VMEM_MAP_END 0x40000000000UL
142 #endif /* __s390x__ */
145 * VMEM_MAX_PHYS is the highest physical address that can be added to the 1:1
146 * mapping. This needs to be calculated at compile time since the size of the
147 * VMEM_MAP is static but the size of struct page can change.
149 #define VMEM_MAX_PAGES ((VMEM_MAP_END - VMALLOC_END) / sizeof(struct page))
150 #define VMEM_MAX_PFN min(VMALLOC_START >> PAGE_SHIFT, VMEM_MAX_PAGES)
151 #define VMEM_MAX_PHYS ((VMEM_MAX_PFN << PAGE_SHIFT) & ~((16 << 20) - 1))
152 #define vmemmap ((struct page *) VMALLOC_END)
155 * A 31 bit pagetable entry of S390 has following format:
156 * | PFRA | | OS |
157 * 0 0IP0
158 * 00000000001111111111222222222233
159 * 01234567890123456789012345678901
161 * I Page-Invalid Bit: Page is not available for address-translation
162 * P Page-Protection Bit: Store access not possible for page
164 * A 31 bit segmenttable entry of S390 has following format:
165 * | P-table origin | |PTL
166 * 0 IC
167 * 00000000001111111111222222222233
168 * 01234567890123456789012345678901
170 * I Segment-Invalid Bit: Segment is not available for address-translation
171 * C Common-Segment Bit: Segment is not private (PoP 3-30)
172 * PTL Page-Table-Length: Page-table length (PTL+1*16 entries -> up to 256)
174 * The 31 bit segmenttable origin of S390 has following format:
176 * |S-table origin | | STL |
177 * X **GPS
178 * 00000000001111111111222222222233
179 * 01234567890123456789012345678901
181 * X Space-Switch event:
182 * G Segment-Invalid Bit: *
183 * P Private-Space Bit: Segment is not private (PoP 3-30)
184 * S Storage-Alteration:
185 * STL Segment-Table-Length: Segment-table length (STL+1*16 entries -> up to 2048)
187 * A 64 bit pagetable entry of S390 has following format:
188 * | PFRA |0IPC| OS |
189 * 0000000000111111111122222222223333333333444444444455555555556666
190 * 0123456789012345678901234567890123456789012345678901234567890123
192 * I Page-Invalid Bit: Page is not available for address-translation
193 * P Page-Protection Bit: Store access not possible for page
194 * C Change-bit override: HW is not required to set change bit
196 * A 64 bit segmenttable entry of S390 has following format:
197 * | P-table origin | TT
198 * 0000000000111111111122222222223333333333444444444455555555556666
199 * 0123456789012345678901234567890123456789012345678901234567890123
201 * I Segment-Invalid Bit: Segment is not available for address-translation
202 * C Common-Segment Bit: Segment is not private (PoP 3-30)
203 * P Page-Protection Bit: Store access not possible for page
204 * TT Type 00
206 * A 64 bit region table entry of S390 has following format:
207 * | S-table origin | TF TTTL
208 * 0000000000111111111122222222223333333333444444444455555555556666
209 * 0123456789012345678901234567890123456789012345678901234567890123
211 * I Segment-Invalid Bit: Segment is not available for address-translation
212 * TT Type 01
213 * TF
214 * TL Table length
216 * The 64 bit regiontable origin of S390 has following format:
217 * | region table origon | DTTL
218 * 0000000000111111111122222222223333333333444444444455555555556666
219 * 0123456789012345678901234567890123456789012345678901234567890123
221 * X Space-Switch event:
222 * G Segment-Invalid Bit:
223 * P Private-Space Bit:
224 * S Storage-Alteration:
225 * R Real space
226 * TL Table-Length:
228 * A storage key has the following format:
229 * | ACC |F|R|C|0|
230 * 0 3 4 5 6 7
231 * ACC: access key
232 * F : fetch protection bit
233 * R : referenced bit
234 * C : changed bit
237 /* Hardware bits in the page table entry */
238 #define _PAGE_CO 0x100 /* HW Change-bit override */
239 #define _PAGE_RO 0x200 /* HW read-only bit */
240 #define _PAGE_INVALID 0x400 /* HW invalid bit */
242 /* Software bits in the page table entry */
243 #define _PAGE_SWT 0x001 /* SW pte type bit t */
244 #define _PAGE_SWX 0x002 /* SW pte type bit x */
245 #define _PAGE_SWC 0x004 /* SW pte changed bit (for KVM) */
246 #define _PAGE_SWR 0x008 /* SW pte referenced bit (for KVM) */
247 #define _PAGE_SPECIAL 0x010 /* SW associated with special page */
248 #define __HAVE_ARCH_PTE_SPECIAL
250 /* Set of bits not changed in pte_modify */
251 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_SWC | _PAGE_SWR)
253 /* Six different types of pages. */
254 #define _PAGE_TYPE_EMPTY 0x400
255 #define _PAGE_TYPE_NONE 0x401
256 #define _PAGE_TYPE_SWAP 0x403
257 #define _PAGE_TYPE_FILE 0x601 /* bit 0x002 is used for offset !! */
258 #define _PAGE_TYPE_RO 0x200
259 #define _PAGE_TYPE_RW 0x000
262 * Only four types for huge pages, using the invalid bit and protection bit
263 * of a segment table entry.
265 #define _HPAGE_TYPE_EMPTY 0x020 /* _SEGMENT_ENTRY_INV */
266 #define _HPAGE_TYPE_NONE 0x220
267 #define _HPAGE_TYPE_RO 0x200 /* _SEGMENT_ENTRY_RO */
268 #define _HPAGE_TYPE_RW 0x000
271 * PTE type bits are rather complicated. handle_pte_fault uses pte_present,
272 * pte_none and pte_file to find out the pte type WITHOUT holding the page
273 * table lock. ptep_clear_flush on the other hand uses ptep_clear_flush to
274 * invalidate a given pte. ipte sets the hw invalid bit and clears all tlbs
275 * for the page. The page table entry is set to _PAGE_TYPE_EMPTY afterwards.
276 * This change is done while holding the lock, but the intermediate step
277 * of a previously valid pte with the hw invalid bit set can be observed by
278 * handle_pte_fault. That makes it necessary that all valid pte types with
279 * the hw invalid bit set must be distinguishable from the four pte types
280 * empty, none, swap and file.
282 * irxt ipte irxt
283 * _PAGE_TYPE_EMPTY 1000 -> 1000
284 * _PAGE_TYPE_NONE 1001 -> 1001
285 * _PAGE_TYPE_SWAP 1011 -> 1011
286 * _PAGE_TYPE_FILE 11?1 -> 11?1
287 * _PAGE_TYPE_RO 0100 -> 1100
288 * _PAGE_TYPE_RW 0000 -> 1000
290 * pte_none is true for bits combinations 1000, 1010, 1100, 1110
291 * pte_present is true for bits combinations 0000, 0010, 0100, 0110, 1001
292 * pte_file is true for bits combinations 1101, 1111
293 * swap pte is 1011 and 0001, 0011, 0101, 0111 are invalid.
296 #ifndef __s390x__
298 /* Bits in the segment table address-space-control-element */
299 #define _ASCE_SPACE_SWITCH 0x80000000UL /* space switch event */
300 #define _ASCE_ORIGIN_MASK 0x7ffff000UL /* segment table origin */
301 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
302 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
303 #define _ASCE_TABLE_LENGTH 0x7f /* 128 x 64 entries = 8k */
305 /* Bits in the segment table entry */
306 #define _SEGMENT_ENTRY_ORIGIN 0x7fffffc0UL /* page table origin */
307 #define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */
308 #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
309 #define _SEGMENT_ENTRY_COMMON 0x10 /* common segment bit */
310 #define _SEGMENT_ENTRY_PTL 0x0f /* page table length */
312 #define _SEGMENT_ENTRY (_SEGMENT_ENTRY_PTL)
313 #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INV)
315 /* Page status table bits for virtualization */
316 #define RCP_ACC_BITS 0xf0000000UL
317 #define RCP_FP_BIT 0x08000000UL
318 #define RCP_PCL_BIT 0x00800000UL
319 #define RCP_HR_BIT 0x00400000UL
320 #define RCP_HC_BIT 0x00200000UL
321 #define RCP_GR_BIT 0x00040000UL
322 #define RCP_GC_BIT 0x00020000UL
324 /* User dirty / referenced bit for KVM's migration feature */
325 #define KVM_UR_BIT 0x00008000UL
326 #define KVM_UC_BIT 0x00004000UL
328 #else /* __s390x__ */
330 /* Bits in the segment/region table address-space-control-element */
331 #define _ASCE_ORIGIN ~0xfffUL/* segment table origin */
332 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
333 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
334 #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
335 #define _ASCE_REAL_SPACE 0x20 /* real space control */
336 #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
337 #define _ASCE_TYPE_REGION1 0x0c /* region first table type */
338 #define _ASCE_TYPE_REGION2 0x08 /* region second table type */
339 #define _ASCE_TYPE_REGION3 0x04 /* region third table type */
340 #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
341 #define _ASCE_TABLE_LENGTH 0x03 /* region table length */
343 /* Bits in the region table entry */
344 #define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */
345 #define _REGION_ENTRY_INV 0x20 /* invalid region table entry */
346 #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
347 #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
348 #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
349 #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
350 #define _REGION_ENTRY_LENGTH 0x03 /* region third length */
352 #define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH)
353 #define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INV)
354 #define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH)
355 #define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INV)
356 #define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH)
357 #define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INV)
359 /* Bits in the segment table entry */
360 #define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* segment table origin */
361 #define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */
362 #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
364 #define _SEGMENT_ENTRY (0)
365 #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INV)
367 #define _SEGMENT_ENTRY_LARGE 0x400 /* STE-format control, large page */
368 #define _SEGMENT_ENTRY_CO 0x100 /* change-recording override */
370 /* Page status table bits for virtualization */
371 #define RCP_ACC_BITS 0xf000000000000000UL
372 #define RCP_FP_BIT 0x0800000000000000UL
373 #define RCP_PCL_BIT 0x0080000000000000UL
374 #define RCP_HR_BIT 0x0040000000000000UL
375 #define RCP_HC_BIT 0x0020000000000000UL
376 #define RCP_GR_BIT 0x0004000000000000UL
377 #define RCP_GC_BIT 0x0002000000000000UL
379 /* User dirty / referenced bit for KVM's migration feature */
380 #define KVM_UR_BIT 0x0000800000000000UL
381 #define KVM_UC_BIT 0x0000400000000000UL
383 #endif /* __s390x__ */
386 * A user page table pointer has the space-switch-event bit, the
387 * private-space-control bit and the storage-alteration-event-control
388 * bit set. A kernel page table pointer doesn't need them.
390 #define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \
391 _ASCE_ALT_EVENT)
394 * Page protection definitions.
396 #define PAGE_NONE __pgprot(_PAGE_TYPE_NONE)
397 #define PAGE_RO __pgprot(_PAGE_TYPE_RO)
398 #define PAGE_RW __pgprot(_PAGE_TYPE_RW)
400 #define PAGE_KERNEL PAGE_RW
401 #define PAGE_COPY PAGE_RO
404 * On s390 the page table entry has an invalid bit and a read-only bit.
405 * Read permission implies execute permission and write permission
406 * implies read permission.
408 /*xwr*/
409 #define __P000 PAGE_NONE
410 #define __P001 PAGE_RO
411 #define __P010 PAGE_RO
412 #define __P011 PAGE_RO
413 #define __P100 PAGE_RO
414 #define __P101 PAGE_RO
415 #define __P110 PAGE_RO
416 #define __P111 PAGE_RO
418 #define __S000 PAGE_NONE
419 #define __S001 PAGE_RO
420 #define __S010 PAGE_RW
421 #define __S011 PAGE_RW
422 #define __S100 PAGE_RO
423 #define __S101 PAGE_RO
424 #define __S110 PAGE_RW
425 #define __S111 PAGE_RW
427 static inline int mm_exclusive(struct mm_struct *mm)
429 return likely(mm == current->active_mm &&
430 atomic_read(&mm->context.attach_count) <= 1);
433 static inline int mm_has_pgste(struct mm_struct *mm)
435 #ifdef CONFIG_PGSTE
436 if (unlikely(mm->context.has_pgste))
437 return 1;
438 #endif
439 return 0;
442 * pgd/pmd/pte query functions
444 #ifndef __s390x__
446 static inline int pgd_present(pgd_t pgd) { return 1; }
447 static inline int pgd_none(pgd_t pgd) { return 0; }
448 static inline int pgd_bad(pgd_t pgd) { return 0; }
450 static inline int pud_present(pud_t pud) { return 1; }
451 static inline int pud_none(pud_t pud) { return 0; }
452 static inline int pud_bad(pud_t pud) { return 0; }
454 #else /* __s390x__ */
456 static inline int pgd_present(pgd_t pgd)
458 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2)
459 return 1;
460 return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL;
463 static inline int pgd_none(pgd_t pgd)
465 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2)
466 return 0;
467 return (pgd_val(pgd) & _REGION_ENTRY_INV) != 0UL;
470 static inline int pgd_bad(pgd_t pgd)
473 * With dynamic page table levels the pgd can be a region table
474 * entry or a segment table entry. Check for the bit that are
475 * invalid for either table entry.
477 unsigned long mask =
478 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INV &
479 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH;
480 return (pgd_val(pgd) & mask) != 0;
483 static inline int pud_present(pud_t pud)
485 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3)
486 return 1;
487 return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL;
490 static inline int pud_none(pud_t pud)
492 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3)
493 return 0;
494 return (pud_val(pud) & _REGION_ENTRY_INV) != 0UL;
497 static inline int pud_bad(pud_t pud)
500 * With dynamic page table levels the pud can be a region table
501 * entry or a segment table entry. Check for the bit that are
502 * invalid for either table entry.
504 unsigned long mask =
505 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INV &
506 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH;
507 return (pud_val(pud) & mask) != 0;
510 #endif /* __s390x__ */
512 static inline int pmd_present(pmd_t pmd)
514 return (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) != 0UL;
517 static inline int pmd_none(pmd_t pmd)
519 return (pmd_val(pmd) & _SEGMENT_ENTRY_INV) != 0UL;
522 static inline int pmd_bad(pmd_t pmd)
524 unsigned long mask = ~_SEGMENT_ENTRY_ORIGIN & ~_SEGMENT_ENTRY_INV;
525 return (pmd_val(pmd) & mask) != _SEGMENT_ENTRY;
528 static inline int pte_none(pte_t pte)
530 return (pte_val(pte) & _PAGE_INVALID) && !(pte_val(pte) & _PAGE_SWT);
533 static inline int pte_present(pte_t pte)
535 unsigned long mask = _PAGE_RO | _PAGE_INVALID | _PAGE_SWT | _PAGE_SWX;
536 return (pte_val(pte) & mask) == _PAGE_TYPE_NONE ||
537 (!(pte_val(pte) & _PAGE_INVALID) &&
538 !(pte_val(pte) & _PAGE_SWT));
541 static inline int pte_file(pte_t pte)
543 unsigned long mask = _PAGE_RO | _PAGE_INVALID | _PAGE_SWT;
544 return (pte_val(pte) & mask) == _PAGE_TYPE_FILE;
547 static inline int pte_special(pte_t pte)
549 return (pte_val(pte) & _PAGE_SPECIAL);
552 #define __HAVE_ARCH_PTE_SAME
553 static inline int pte_same(pte_t a, pte_t b)
555 return pte_val(a) == pte_val(b);
558 static inline pgste_t pgste_get_lock(pte_t *ptep)
560 unsigned long new = 0;
561 #ifdef CONFIG_PGSTE
562 unsigned long old;
564 preempt_disable();
565 asm(
566 " lg %0,%2\n"
567 "0: lgr %1,%0\n"
568 " nihh %0,0xff7f\n" /* clear RCP_PCL_BIT in old */
569 " oihh %1,0x0080\n" /* set RCP_PCL_BIT in new */
570 " csg %0,%1,%2\n"
571 " jl 0b\n"
572 : "=&d" (old), "=&d" (new), "=Q" (ptep[PTRS_PER_PTE])
573 : "Q" (ptep[PTRS_PER_PTE]) : "cc");
574 #endif
575 return __pgste(new);
578 static inline void pgste_set_unlock(pte_t *ptep, pgste_t pgste)
580 #ifdef CONFIG_PGSTE
581 asm(
582 " nihh %1,0xff7f\n" /* clear RCP_PCL_BIT */
583 " stg %1,%0\n"
584 : "=Q" (ptep[PTRS_PER_PTE])
585 : "d" (pgste_val(pgste)), "Q" (ptep[PTRS_PER_PTE]) : "cc");
586 preempt_enable();
587 #endif
590 static inline pgste_t pgste_update_all(pte_t *ptep, pgste_t pgste)
592 #ifdef CONFIG_PGSTE
593 unsigned long address, bits;
594 unsigned char skey;
596 address = pte_val(*ptep) & PAGE_MASK;
597 skey = page_get_storage_key(address);
598 bits = skey & (_PAGE_CHANGED | _PAGE_REFERENCED);
599 /* Clear page changed & referenced bit in the storage key */
600 if (bits) {
601 skey ^= bits;
602 page_set_storage_key(address, skey, 1);
604 /* Transfer page changed & referenced bit to guest bits in pgste */
605 pgste_val(pgste) |= bits << 48; /* RCP_GR_BIT & RCP_GC_BIT */
606 /* Get host changed & referenced bits from pgste */
607 bits |= (pgste_val(pgste) & (RCP_HR_BIT | RCP_HC_BIT)) >> 52;
608 /* Clear host bits in pgste. */
609 pgste_val(pgste) &= ~(RCP_HR_BIT | RCP_HC_BIT);
610 pgste_val(pgste) &= ~(RCP_ACC_BITS | RCP_FP_BIT);
611 /* Copy page access key and fetch protection bit to pgste */
612 pgste_val(pgste) |=
613 (unsigned long) (skey & (_PAGE_ACC_BITS | _PAGE_FP_BIT)) << 56;
614 /* Transfer changed and referenced to kvm user bits */
615 pgste_val(pgste) |= bits << 45; /* KVM_UR_BIT & KVM_UC_BIT */
616 /* Transfer changed & referenced to pte sofware bits */
617 pte_val(*ptep) |= bits << 1; /* _PAGE_SWR & _PAGE_SWC */
618 #endif
619 return pgste;
623 static inline pgste_t pgste_update_young(pte_t *ptep, pgste_t pgste)
625 #ifdef CONFIG_PGSTE
626 int young;
628 young = page_reset_referenced(pte_val(*ptep) & PAGE_MASK);
629 /* Transfer page referenced bit to pte software bit (host view) */
630 if (young || (pgste_val(pgste) & RCP_HR_BIT))
631 pte_val(*ptep) |= _PAGE_SWR;
632 /* Clear host referenced bit in pgste. */
633 pgste_val(pgste) &= ~RCP_HR_BIT;
634 /* Transfer page referenced bit to guest bit in pgste */
635 pgste_val(pgste) |= (unsigned long) young << 50; /* set RCP_GR_BIT */
636 #endif
637 return pgste;
641 static inline void pgste_set_pte(pte_t *ptep, pgste_t pgste)
643 #ifdef CONFIG_PGSTE
644 unsigned long address;
645 unsigned long okey, nkey;
647 address = pte_val(*ptep) & PAGE_MASK;
648 okey = nkey = page_get_storage_key(address);
649 nkey &= ~(_PAGE_ACC_BITS | _PAGE_FP_BIT);
650 /* Set page access key and fetch protection bit from pgste */
651 nkey |= (pgste_val(pgste) & (RCP_ACC_BITS | RCP_FP_BIT)) >> 56;
652 if (okey != nkey)
653 page_set_storage_key(address, nkey, 1);
654 #endif
658 * Certain architectures need to do special things when PTEs
659 * within a page table are directly modified. Thus, the following
660 * hook is made available.
662 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
663 pte_t *ptep, pte_t entry)
665 pgste_t pgste;
667 if (mm_has_pgste(mm)) {
668 pgste = pgste_get_lock(ptep);
669 pgste_set_pte(ptep, pgste);
670 *ptep = entry;
671 pgste_set_unlock(ptep, pgste);
672 } else
673 *ptep = entry;
677 * query functions pte_write/pte_dirty/pte_young only work if
678 * pte_present() is true. Undefined behaviour if not..
680 static inline int pte_write(pte_t pte)
682 return (pte_val(pte) & _PAGE_RO) == 0;
685 static inline int pte_dirty(pte_t pte)
687 #ifdef CONFIG_PGSTE
688 if (pte_val(pte) & _PAGE_SWC)
689 return 1;
690 #endif
691 return 0;
694 static inline int pte_young(pte_t pte)
696 #ifdef CONFIG_PGSTE
697 if (pte_val(pte) & _PAGE_SWR)
698 return 1;
699 #endif
700 return 0;
704 * pgd/pmd/pte modification functions
707 static inline void pgd_clear(pgd_t *pgd)
709 #ifdef __s390x__
710 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2)
711 pgd_val(*pgd) = _REGION2_ENTRY_EMPTY;
712 #endif
715 static inline void pud_clear(pud_t *pud)
717 #ifdef __s390x__
718 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3)
719 pud_val(*pud) = _REGION3_ENTRY_EMPTY;
720 #endif
723 static inline void pmd_clear(pmd_t *pmdp)
725 pmd_val(*pmdp) = _SEGMENT_ENTRY_EMPTY;
728 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
730 pte_val(*ptep) = _PAGE_TYPE_EMPTY;
734 * The following pte modification functions only work if
735 * pte_present() is true. Undefined behaviour if not..
737 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
739 pte_val(pte) &= _PAGE_CHG_MASK;
740 pte_val(pte) |= pgprot_val(newprot);
741 return pte;
744 static inline pte_t pte_wrprotect(pte_t pte)
746 /* Do not clobber _PAGE_TYPE_NONE pages! */
747 if (!(pte_val(pte) & _PAGE_INVALID))
748 pte_val(pte) |= _PAGE_RO;
749 return pte;
752 static inline pte_t pte_mkwrite(pte_t pte)
754 pte_val(pte) &= ~_PAGE_RO;
755 return pte;
758 static inline pte_t pte_mkclean(pte_t pte)
760 #ifdef CONFIG_PGSTE
761 pte_val(pte) &= ~_PAGE_SWC;
762 #endif
763 return pte;
766 static inline pte_t pte_mkdirty(pte_t pte)
768 return pte;
771 static inline pte_t pte_mkold(pte_t pte)
773 #ifdef CONFIG_PGSTE
774 pte_val(pte) &= ~_PAGE_SWR;
775 #endif
776 return pte;
779 static inline pte_t pte_mkyoung(pte_t pte)
781 return pte;
784 static inline pte_t pte_mkspecial(pte_t pte)
786 pte_val(pte) |= _PAGE_SPECIAL;
787 return pte;
790 #ifdef CONFIG_HUGETLB_PAGE
791 static inline pte_t pte_mkhuge(pte_t pte)
794 * PROT_NONE needs to be remapped from the pte type to the ste type.
795 * The HW invalid bit is also different for pte and ste. The pte
796 * invalid bit happens to be the same as the ste _SEGMENT_ENTRY_LARGE
797 * bit, so we don't have to clear it.
799 if (pte_val(pte) & _PAGE_INVALID) {
800 if (pte_val(pte) & _PAGE_SWT)
801 pte_val(pte) |= _HPAGE_TYPE_NONE;
802 pte_val(pte) |= _SEGMENT_ENTRY_INV;
805 * Clear SW pte bits SWT and SWX, there are no SW bits in a segment
806 * table entry.
808 pte_val(pte) &= ~(_PAGE_SWT | _PAGE_SWX);
810 * Also set the change-override bit because we don't need dirty bit
811 * tracking for hugetlbfs pages.
813 pte_val(pte) |= (_SEGMENT_ENTRY_LARGE | _SEGMENT_ENTRY_CO);
814 return pte;
816 #endif
819 * Get (and clear) the user dirty bit for a pte.
821 static inline int ptep_test_and_clear_user_dirty(struct mm_struct *mm,
822 pte_t *ptep)
824 pgste_t pgste;
825 int dirty = 0;
827 if (mm_has_pgste(mm)) {
828 pgste = pgste_get_lock(ptep);
829 pgste = pgste_update_all(ptep, pgste);
830 dirty = !!(pgste_val(pgste) & KVM_UC_BIT);
831 pgste_val(pgste) &= ~KVM_UC_BIT;
832 pgste_set_unlock(ptep, pgste);
833 return dirty;
835 return dirty;
839 * Get (and clear) the user referenced bit for a pte.
841 static inline int ptep_test_and_clear_user_young(struct mm_struct *mm,
842 pte_t *ptep)
844 pgste_t pgste;
845 int young = 0;
847 if (mm_has_pgste(mm)) {
848 pgste = pgste_get_lock(ptep);
849 pgste = pgste_update_young(ptep, pgste);
850 young = !!(pgste_val(pgste) & KVM_UR_BIT);
851 pgste_val(pgste) &= ~KVM_UR_BIT;
852 pgste_set_unlock(ptep, pgste);
854 return young;
857 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
858 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
859 unsigned long addr, pte_t *ptep)
861 pgste_t pgste;
862 pte_t pte;
864 if (mm_has_pgste(vma->vm_mm)) {
865 pgste = pgste_get_lock(ptep);
866 pgste = pgste_update_young(ptep, pgste);
867 pte = *ptep;
868 *ptep = pte_mkold(pte);
869 pgste_set_unlock(ptep, pgste);
870 return pte_young(pte);
872 return 0;
875 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
876 static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
877 unsigned long address, pte_t *ptep)
879 /* No need to flush TLB
880 * On s390 reference bits are in storage key and never in TLB
881 * With virtualization we handle the reference bit, without we
882 * we can simply return */
883 return ptep_test_and_clear_young(vma, address, ptep);
886 static inline void __ptep_ipte(unsigned long address, pte_t *ptep)
888 if (!(pte_val(*ptep) & _PAGE_INVALID)) {
889 #ifndef __s390x__
890 /* pto must point to the start of the segment table */
891 pte_t *pto = (pte_t *) (((unsigned long) ptep) & 0x7ffffc00);
892 #else
893 /* ipte in zarch mode can do the math */
894 pte_t *pto = ptep;
895 #endif
896 asm volatile(
897 " ipte %2,%3"
898 : "=m" (*ptep) : "m" (*ptep),
899 "a" (pto), "a" (address));
904 * This is hard to understand. ptep_get_and_clear and ptep_clear_flush
905 * both clear the TLB for the unmapped pte. The reason is that
906 * ptep_get_and_clear is used in common code (e.g. change_pte_range)
907 * to modify an active pte. The sequence is
908 * 1) ptep_get_and_clear
909 * 2) set_pte_at
910 * 3) flush_tlb_range
911 * On s390 the tlb needs to get flushed with the modification of the pte
912 * if the pte is active. The only way how this can be implemented is to
913 * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range
914 * is a nop.
916 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
917 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
918 unsigned long address, pte_t *ptep)
920 pgste_t pgste;
921 pte_t pte;
923 mm->context.flush_mm = 1;
924 if (mm_has_pgste(mm))
925 pgste = pgste_get_lock(ptep);
927 pte = *ptep;
928 if (!mm_exclusive(mm))
929 __ptep_ipte(address, ptep);
930 pte_val(*ptep) = _PAGE_TYPE_EMPTY;
932 if (mm_has_pgste(mm)) {
933 pgste = pgste_update_all(&pte, pgste);
934 pgste_set_unlock(ptep, pgste);
936 return pte;
939 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
940 static inline pte_t ptep_modify_prot_start(struct mm_struct *mm,
941 unsigned long address,
942 pte_t *ptep)
944 pte_t pte;
946 mm->context.flush_mm = 1;
947 if (mm_has_pgste(mm))
948 pgste_get_lock(ptep);
950 pte = *ptep;
951 if (!mm_exclusive(mm))
952 __ptep_ipte(address, ptep);
953 return pte;
956 static inline void ptep_modify_prot_commit(struct mm_struct *mm,
957 unsigned long address,
958 pte_t *ptep, pte_t pte)
960 *ptep = pte;
961 if (mm_has_pgste(mm))
962 pgste_set_unlock(ptep, *(pgste_t *)(ptep + PTRS_PER_PTE));
965 #define __HAVE_ARCH_PTEP_CLEAR_FLUSH
966 static inline pte_t ptep_clear_flush(struct vm_area_struct *vma,
967 unsigned long address, pte_t *ptep)
969 pgste_t pgste;
970 pte_t pte;
972 if (mm_has_pgste(vma->vm_mm))
973 pgste = pgste_get_lock(ptep);
975 pte = *ptep;
976 __ptep_ipte(address, ptep);
977 pte_val(*ptep) = _PAGE_TYPE_EMPTY;
979 if (mm_has_pgste(vma->vm_mm)) {
980 pgste = pgste_update_all(&pte, pgste);
981 pgste_set_unlock(ptep, pgste);
983 return pte;
987 * The batched pte unmap code uses ptep_get_and_clear_full to clear the
988 * ptes. Here an optimization is possible. tlb_gather_mmu flushes all
989 * tlbs of an mm if it can guarantee that the ptes of the mm_struct
990 * cannot be accessed while the batched unmap is running. In this case
991 * full==1 and a simple pte_clear is enough. See tlb.h.
993 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
994 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
995 unsigned long address,
996 pte_t *ptep, int full)
998 pgste_t pgste;
999 pte_t pte;
1001 if (mm_has_pgste(mm))
1002 pgste = pgste_get_lock(ptep);
1004 pte = *ptep;
1005 if (!full)
1006 __ptep_ipte(address, ptep);
1007 pte_val(*ptep) = _PAGE_TYPE_EMPTY;
1009 if (mm_has_pgste(mm)) {
1010 pgste = pgste_update_all(&pte, pgste);
1011 pgste_set_unlock(ptep, pgste);
1013 return pte;
1016 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
1017 static inline pte_t ptep_set_wrprotect(struct mm_struct *mm,
1018 unsigned long address, pte_t *ptep)
1020 pgste_t pgste;
1021 pte_t pte = *ptep;
1023 if (pte_write(pte)) {
1024 mm->context.flush_mm = 1;
1025 if (mm_has_pgste(mm))
1026 pgste = pgste_get_lock(ptep);
1028 if (!mm_exclusive(mm))
1029 __ptep_ipte(address, ptep);
1030 *ptep = pte_wrprotect(pte);
1032 if (mm_has_pgste(mm))
1033 pgste_set_unlock(ptep, pgste);
1035 return pte;
1038 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
1039 static inline int ptep_set_access_flags(struct vm_area_struct *vma,
1040 unsigned long address, pte_t *ptep,
1041 pte_t entry, int dirty)
1043 pgste_t pgste;
1045 if (pte_same(*ptep, entry))
1046 return 0;
1047 if (mm_has_pgste(vma->vm_mm))
1048 pgste = pgste_get_lock(ptep);
1050 __ptep_ipte(address, ptep);
1051 *ptep = entry;
1053 if (mm_has_pgste(vma->vm_mm))
1054 pgste_set_unlock(ptep, pgste);
1055 return 1;
1059 * Conversion functions: convert a page and protection to a page entry,
1060 * and a page entry and page directory to the page they refer to.
1062 static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot)
1064 pte_t __pte;
1065 pte_val(__pte) = physpage + pgprot_val(pgprot);
1066 return __pte;
1069 static inline pte_t mk_pte(struct page *page, pgprot_t pgprot)
1071 unsigned long physpage = page_to_phys(page);
1073 return mk_pte_phys(physpage, pgprot);
1076 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
1077 #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
1078 #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
1079 #define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1))
1081 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
1082 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
1084 #ifndef __s390x__
1086 #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN)
1087 #define pud_deref(pmd) ({ BUG(); 0UL; })
1088 #define pgd_deref(pmd) ({ BUG(); 0UL; })
1090 #define pud_offset(pgd, address) ((pud_t *) pgd)
1091 #define pmd_offset(pud, address) ((pmd_t *) pud + pmd_index(address))
1093 #else /* __s390x__ */
1095 #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN)
1096 #define pud_deref(pud) (pud_val(pud) & _REGION_ENTRY_ORIGIN)
1097 #define pgd_deref(pgd) (pgd_val(pgd) & _REGION_ENTRY_ORIGIN)
1099 static inline pud_t *pud_offset(pgd_t *pgd, unsigned long address)
1101 pud_t *pud = (pud_t *) pgd;
1102 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2)
1103 pud = (pud_t *) pgd_deref(*pgd);
1104 return pud + pud_index(address);
1107 static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address)
1109 pmd_t *pmd = (pmd_t *) pud;
1110 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3)
1111 pmd = (pmd_t *) pud_deref(*pud);
1112 return pmd + pmd_index(address);
1115 #endif /* __s390x__ */
1117 #define pfn_pte(pfn,pgprot) mk_pte_phys(__pa((pfn) << PAGE_SHIFT),(pgprot))
1118 #define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT)
1119 #define pte_page(x) pfn_to_page(pte_pfn(x))
1121 #define pmd_page(pmd) pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)
1123 /* Find an entry in the lowest level page table.. */
1124 #define pte_offset(pmd, addr) ((pte_t *) pmd_deref(*(pmd)) + pte_index(addr))
1125 #define pte_offset_kernel(pmd, address) pte_offset(pmd,address)
1126 #define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address)
1127 #define pte_unmap(pte) do { } while (0)
1130 * 31 bit swap entry format:
1131 * A page-table entry has some bits we have to treat in a special way.
1132 * Bits 0, 20 and bit 23 have to be zero, otherwise an specification
1133 * exception will occur instead of a page translation exception. The
1134 * specifiation exception has the bad habit not to store necessary
1135 * information in the lowcore.
1136 * Bit 21 and bit 22 are the page invalid bit and the page protection
1137 * bit. We set both to indicate a swapped page.
1138 * Bit 30 and 31 are used to distinguish the different page types. For
1139 * a swapped page these bits need to be zero.
1140 * This leaves the bits 1-19 and bits 24-29 to store type and offset.
1141 * We use the 5 bits from 25-29 for the type and the 20 bits from 1-19
1142 * plus 24 for the offset.
1143 * 0| offset |0110|o|type |00|
1144 * 0 0000000001111111111 2222 2 22222 33
1145 * 0 1234567890123456789 0123 4 56789 01
1147 * 64 bit swap entry format:
1148 * A page-table entry has some bits we have to treat in a special way.
1149 * Bits 52 and bit 55 have to be zero, otherwise an specification
1150 * exception will occur instead of a page translation exception. The
1151 * specifiation exception has the bad habit not to store necessary
1152 * information in the lowcore.
1153 * Bit 53 and bit 54 are the page invalid bit and the page protection
1154 * bit. We set both to indicate a swapped page.
1155 * Bit 62 and 63 are used to distinguish the different page types. For
1156 * a swapped page these bits need to be zero.
1157 * This leaves the bits 0-51 and bits 56-61 to store type and offset.
1158 * We use the 5 bits from 57-61 for the type and the 53 bits from 0-51
1159 * plus 56 for the offset.
1160 * | offset |0110|o|type |00|
1161 * 0000000000111111111122222222223333333333444444444455 5555 5 55566 66
1162 * 0123456789012345678901234567890123456789012345678901 2345 6 78901 23
1164 #ifndef __s390x__
1165 #define __SWP_OFFSET_MASK (~0UL >> 12)
1166 #else
1167 #define __SWP_OFFSET_MASK (~0UL >> 11)
1168 #endif
1169 static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
1171 pte_t pte;
1172 offset &= __SWP_OFFSET_MASK;
1173 pte_val(pte) = _PAGE_TYPE_SWAP | ((type & 0x1f) << 2) |
1174 ((offset & 1UL) << 7) | ((offset & ~1UL) << 11);
1175 return pte;
1178 #define __swp_type(entry) (((entry).val >> 2) & 0x1f)
1179 #define __swp_offset(entry) (((entry).val >> 11) | (((entry).val >> 7) & 1))
1180 #define __swp_entry(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) })
1182 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
1183 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
1185 #ifndef __s390x__
1186 # define PTE_FILE_MAX_BITS 26
1187 #else /* __s390x__ */
1188 # define PTE_FILE_MAX_BITS 59
1189 #endif /* __s390x__ */
1191 #define pte_to_pgoff(__pte) \
1192 ((((__pte).pte >> 12) << 7) + (((__pte).pte >> 1) & 0x7f))
1194 #define pgoff_to_pte(__off) \
1195 ((pte_t) { ((((__off) & 0x7f) << 1) + (((__off) >> 7) << 12)) \
1196 | _PAGE_TYPE_FILE })
1198 #endif /* !__ASSEMBLY__ */
1200 #define kern_addr_valid(addr) (1)
1202 extern int vmem_add_mapping(unsigned long start, unsigned long size);
1203 extern int vmem_remove_mapping(unsigned long start, unsigned long size);
1204 extern int s390_enable_sie(void);
1207 * No page table caches to initialise
1209 #define pgtable_cache_init() do { } while (0)
1211 #include <asm-generic/pgtable.h>
1213 #endif /* _S390_PAGE_H */