arch/powerpc/platforms/86xx/mpc8610_hpcd.c

   1 /*
   2  * MPC8610 HPCD board specific routines
   3  *
   4  * Initial author: Xianghua Xiao <x.xiao@freescale.com>
   5  * Recode: Jason Jin <jason.jin@freescale.com>
   6  *         York Sun <yorksun@freescale.com>
   7  *
   8  * Rewrite the interrupt routing. remove the 8259PIC support,
   9  * All the integrated device in ULI use sideband interrupt.
  10  *
  11  * Copyright 2008 Freescale Semiconductor Inc.
  12  *
  13  * This program is free software; you can redistribute  it and/or modify it
  14  * under  the terms of  the GNU General  Public License as published by the
  15  * Free Software Foundation;  either version 2 of the  License, or (at your
  16  * option) any later version.
  17  */
  18
  19 #include <linux/stddef.h>
  20 #include <linux/kernel.h>
  21 #include <linux/pci.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/kdev_t.h>
  24 #include <linux/delay.h>
  25 #include <linux/seq_file.h>
  26 #include <linux/of.h>
  27
  28 #include <asm/system.h>
  29 #include <asm/time.h>
  30 #include <asm/machdep.h>
  31 #include <asm/pci-bridge.h>
  32 #include <asm/prom.h>
  33 #include <mm/mmu_decl.h>
  34 #include <asm/udbg.h>
  35
  36 #include <asm/mpic.h>
  37
  38 #include <linux/of_platform.h>
  39 #include <sysdev/fsl_pci.h>
  40 #include <sysdev/fsl_soc.h>
  41 #include <sysdev/simple_gpio.h>
  42
  43 #include "mpc86xx.h"
  44
  45 static struct device_node *pixis_node;
  46 static unsigned char *pixis_bdcfg0, *pixis_arch;
  47
  48 #ifdef CONFIG_SUSPEND
  49 static irqreturn_t mpc8610_sw9_irq(int irq, void *data)
  50 {
  51         pr_debug("%s: PIXIS' event (sw9/wakeup) IRQ handled\n", __func__);
  52         return IRQ_HANDLED;
  53 }
  54
  55 static void __init mpc8610_suspend_init(void)
  56 {
  57         int irq;
  58         int ret;
  59
  60         if (!pixis_node)
  61                 return;
  62
  63         irq = irq_of_parse_and_map(pixis_node, 0);
  64         if (!irq) {
  65                 pr_err("%s: can't map pixis event IRQ.\n", __func__);
  66                 return;
  67         }
  68
  69         ret = request_irq(irq, mpc8610_sw9_irq, 0, "sw9/wakeup", NULL);
  70         if (ret) {
  71                 pr_err("%s: can't request pixis event IRQ: %d\n",
  72                        __func__, ret);
  73                 irq_dispose_mapping(irq);
  74         }
  75
  76         enable_irq_wake(irq);
  77 }
  78 #else
  79 static inline void mpc8610_suspend_init(void) { }
  80 #endif /* CONFIG_SUSPEND */
  81
  82 static struct of_device_id __initdata mpc8610_ids[] = {
  83         { .compatible = "fsl,mpc8610-immr", },
  84         { .compatible = "fsl,mpc8610-guts", },
  85         { .compatible = "simple-bus", },
  86         { .compatible = "gianfar", },
  87         {}
  88 };
  89
  90 static int __init mpc8610_declare_of_platform_devices(void)
  91 {
  92         /* Firstly, register PIXIS GPIOs. */
  93         simple_gpiochip_init("fsl,fpga-pixis-gpio-bank");
  94
  95         /* Enable wakeup on PIXIS' event IRQ. */
  96         mpc8610_suspend_init();
  97
  98         /* Without this call, the SSI device driver won't get probed. */
  99         of_platform_bus_probe(NULL, mpc8610_ids, NULL);
 100
 101         return 0;
 102 }
 103 machine_device_initcall(mpc86xx_hpcd, mpc8610_declare_of_platform_devices);
 104
 105 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
 106
 107 static u32 get_busfreq(void)
 108 {
 109         struct device_node *node;
 110
 111         u32 fs_busfreq = 0;
 112         node = of_find_node_by_type(NULL, "cpu");
 113         if (node) {
 114                 unsigned int size;
 115                 const unsigned int *prop =
 116                         of_get_property(node, "bus-frequency", &size);
 117                 if (prop)
 118                         fs_busfreq = *prop;
 119                 of_node_put(node);
 120         };
 121         return fs_busfreq;
 122 }
 123
 124 unsigned int mpc8610hpcd_get_pixel_format(unsigned int bits_per_pixel,
 125                                                 int monitor_port)
 126 {
 127         static const unsigned long pixelformat[][3] = {
 128                 {0x88882317, 0x88083218, 0x65052119},
 129                 {0x88883316, 0x88082219, 0x65053118},
 130         };
 131         unsigned int pix_fmt, arch_monitor;
 132
 133         arch_monitor = ((*pixis_arch == 0x01) && (monitor_port == 0))? 0 : 1;
 134                 /* DVI port for board version 0x01 */
 135
 136         if (bits_per_pixel == 32)
 137                 pix_fmt = pixelformat[arch_monitor][0];
 138         else if (bits_per_pixel == 24)
 139                 pix_fmt = pixelformat[arch_monitor][1];
 140         else if (bits_per_pixel == 16)
 141                 pix_fmt = pixelformat[arch_monitor][2];
 142         else
 143                 pix_fmt = pixelformat[1][0];
 144
 145         return pix_fmt;
 146 }
 147
 148 void mpc8610hpcd_set_gamma_table(int monitor_port, char *gamma_table_base)
 149 {
 150         int i;
 151         if (monitor_port == 2) {                /* dual link LVDS */
 152                 for (i = 0; i < 256*3; i++)
 153                         gamma_table_base[i] = (gamma_table_base[i] << 2) |
 154                                          ((gamma_table_base[i] >> 6) & 0x03);
 155         }
 156 }
 157
 158 #define PX_BRDCFG0_DVISEL       (1 << 3)
 159 #define PX_BRDCFG0_DLINK        (1 << 4)
 160 #define PX_BRDCFG0_DIU_MASK     (PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK)
 161
 162 void mpc8610hpcd_set_monitor_port(int monitor_port)
 163 {
 164         static const u8 bdcfg[] = {
 165                 PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK,
 166                 PX_BRDCFG0_DLINK,
 167                 0,
 168         };
 169
 170         if (monitor_port < 3)
 171                 clrsetbits_8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK,
 172                              bdcfg[monitor_port]);
 173 }
 174
 175 void mpc8610hpcd_set_pixel_clock(unsigned int pixclock)
 176 {
 177         u32 __iomem *clkdvdr;
 178         u32 temp;
 179         /* variables for pixel clock calcs */
 180         ulong  bestval, bestfreq, speed_ccb, minpixclock, maxpixclock;
 181         ulong pixval;
 182         long err;
 183         int i;
 184
 185         clkdvdr = ioremap(get_immrbase() + 0xe0800, sizeof(u32));
 186         if (!clkdvdr) {
 187                 printk(KERN_ERR "Err: can't map clock divider register!\n");
 188                 return;
 189         }
 190
 191         /* Pixel Clock configuration */
 192         pr_debug("DIU: Bus Frequency = %d\n", get_busfreq());
 193         speed_ccb = get_busfreq();
 194
 195         /* Calculate the pixel clock with the smallest error */
 196         /* calculate the following in steps to avoid overflow */
 197         pr_debug("DIU pixclock in ps - %d\n", pixclock);
 198         temp = 1000000000/pixclock;
 199         temp *= 1000;
 200         pixclock = temp;
 201         pr_debug("DIU pixclock freq - %u\n", pixclock);
 202
 203         temp = pixclock * 5 / 100;
 204         pr_debug("deviation = %d\n", temp);
 205         minpixclock = pixclock - temp;
 206         maxpixclock = pixclock + temp;
 207         pr_debug("DIU minpixclock - %lu\n", minpixclock);
 208         pr_debug("DIU maxpixclock - %lu\n", maxpixclock);
 209         pixval = speed_ccb/pixclock;
 210         pr_debug("DIU pixval = %lu\n", pixval);
 211
 212         err = 100000000;
 213         bestval = pixval;
 214         pr_debug("DIU bestval = %lu\n", bestval);
 215
 216         bestfreq = 0;
 217         for (i = -1; i <= 1; i++) {
 218                 temp = speed_ccb / ((pixval+i) + 1);
 219                 pr_debug("DIU test pixval i= %d, pixval=%lu, temp freq. = %u\n",
 220                                                         i, pixval, temp);
 221                 if ((temp < minpixclock) || (temp > maxpixclock))
 222                         pr_debug("DIU exceeds monitor range (%lu to %lu)\n",
 223                                 minpixclock, maxpixclock);
 224                 else if (abs(temp - pixclock) < err) {
 225                   pr_debug("Entered the else if block %d\n", i);
 226                         err = abs(temp - pixclock);
 227                         bestval = pixval+i;
 228                         bestfreq = temp;
 229                 }
 230         }
 231
 232         pr_debug("DIU chose = %lx\n", bestval);
 233         pr_debug("DIU error = %ld\n NomPixClk ", err);
 234         pr_debug("DIU: Best Freq = %lx\n", bestfreq);
 235         /* Modify PXCLK in GUTS CLKDVDR */
 236         pr_debug("DIU: Current value of CLKDVDR = 0x%08x\n", (*clkdvdr));
 237         temp = (*clkdvdr) & 0x2000FFFF;
 238         *clkdvdr = temp;                /* turn off clock */
 239         *clkdvdr = temp | 0x80000000 | (((bestval) & 0x1F) << 16);
 240         pr_debug("DIU: Modified value of CLKDVDR = 0x%08x\n", (*clkdvdr));
 241         iounmap(clkdvdr);
 242 }
 243
 244 ssize_t mpc8610hpcd_show_monitor_port(int monitor_port, char *buf)
 245 {
 246         return snprintf(buf, PAGE_SIZE,
 247                         "%c0 - DVI\n"
 248                         "%c1 - Single link LVDS\n"
 249                         "%c2 - Dual link LVDS\n",
 250                         monitor_port == 0 ? '*' : ' ',
 251                         monitor_port == 1 ? '*' : ' ',
 252                         monitor_port == 2 ? '*' : ' ');
 253 }
 254
 255 int mpc8610hpcd_set_sysfs_monitor_port(int val)
 256 {
 257         return val < 3 ? val : 0;
 258 }
 259
 260 #endif
 261
 262 static void __init mpc86xx_hpcd_setup_arch(void)
 263 {
 264         struct resource r;
 265         struct device_node *np;
 266         unsigned char *pixis;
 267
 268         if (ppc_md.progress)
 269                 ppc_md.progress("mpc86xx_hpcd_setup_arch()", 0);
 270
 271 #ifdef CONFIG_PCI
 272         for_each_node_by_type(np, "pci") {
 273                 if (of_device_is_compatible(np, "fsl,mpc8610-pci")
 274                     || of_device_is_compatible(np, "fsl,mpc8641-pcie")) {
 275                         struct resource rsrc;
 276                         of_address_to_resource(np, 0, &rsrc);
 277                         if ((rsrc.start & 0xfffff) == 0xa000)
 278                                 fsl_add_bridge(np, 1);
 279                         else
 280                                 fsl_add_bridge(np, 0);
 281                 }
 282         }
 283 #endif
 284 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
 285         diu_ops.get_pixel_format        = mpc8610hpcd_get_pixel_format;
 286         diu_ops.set_gamma_table         = mpc8610hpcd_set_gamma_table;
 287         diu_ops.set_monitor_port        = mpc8610hpcd_set_monitor_port;
 288         diu_ops.set_pixel_clock         = mpc8610hpcd_set_pixel_clock;
 289         diu_ops.show_monitor_port       = mpc8610hpcd_show_monitor_port;
 290         diu_ops.set_sysfs_monitor_port  = mpc8610hpcd_set_sysfs_monitor_port;
 291 #endif
 292
 293         pixis_node = of_find_compatible_node(NULL, NULL, "fsl,fpga-pixis");
 294         if (pixis_node) {
 295                 of_address_to_resource(pixis_node, 0, &r);
 296                 of_node_put(pixis_node);
 297                 pixis = ioremap(r.start, 32);
 298                 if (!pixis) {
 299                         printk(KERN_ERR "Err: can't map FPGA cfg register!\n");
 300                         return;
 301                 }
 302                 pixis_bdcfg0 = pixis + 8;
 303                 pixis_arch = pixis + 1;
 304         } else
 305                 printk(KERN_ERR "Err: "
 306                                 "can't find device node 'fsl,fpga-pixis'\n");
 307
 308         printk("MPC86xx HPCD board from Freescale Semiconductor\n");
 309 }
 310
 311 /*
 312  * Called very early, device-tree isn't unflattened
 313  */
 314 static int __init mpc86xx_hpcd_probe(void)
 315 {
 316         unsigned long root = of_get_flat_dt_root();
 317
 318         if (of_flat_dt_is_compatible(root, "fsl,MPC8610HPCD"))
 319                 return 1;       /* Looks good */
 320
 321         return 0;
 322 }
 323
 324 static long __init mpc86xx_time_init(void)
 325 {
 326         unsigned int temp;
 327
 328         /* Set the time base to zero */
 329         mtspr(SPRN_TBWL, 0);
 330         mtspr(SPRN_TBWU, 0);
 331
 332         temp = mfspr(SPRN_HID0);
 333         temp |= HID0_TBEN;
 334         mtspr(SPRN_HID0, temp);
 335         asm volatile("isync");
 336
 337         return 0;
 338 }
 339
 340 define_machine(mpc86xx_hpcd) {
 341         .name                   = "MPC86xx HPCD",
 342         .probe                  = mpc86xx_hpcd_probe,
 343         .setup_arch             = mpc86xx_hpcd_setup_arch,
 344         .init_IRQ               = mpc86xx_init_irq,
 345         .get_irq                = mpic_get_irq,
 346         .restart                = fsl_rstcr_restart,
 347         .time_init              = mpc86xx_time_init,
 348         .calibrate_decr         = generic_calibrate_decr,
 349         .progress               = udbg_progress,
 350         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 351 };