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Merge remote-tracking branch 'moduleh/module.h-split'
[linux-2.6/next.git] / drivers / tty / serial / imx.c
blob54ffdc6243f9bb2d529e16e80f450d33c28710ee
1 /*
2 * Driver for Motorola IMX serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Author: Sascha Hauer <sascha@saschahauer.de>
7 * Copyright (C) 2004 Pengutronix
8 *
9 * Copyright (C) 2009 emlix GmbH
10 * Author: Fabian Godehardt (added IrDA support for iMX)
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 * [29-Mar-2005] Mike Lee
27 * Added hardware handshake
28 */
29
30 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
31 #define SUPPORT_SYSRQ
32 #endif
33
34 #include <linux/module.h>
35 #include <linux/ioport.h>
36 #include <linux/init.h>
37 #include <linux/console.h>
38 #include <linux/sysrq.h>
39 #include <linux/platform_device.h>
40 #include <linux/tty.h>
41 #include <linux/tty_flip.h>
42 #include <linux/serial_core.h>
43 #include <linux/serial.h>
44 #include <linux/clk.h>
45 #include <linux/delay.h>
46 #include <linux/rational.h>
47 #include <linux/slab.h>
48 #include <linux/of.h>
49 #include <linux/of_device.h>
50
51 #include <asm/io.h>
52 #include <asm/irq.h>
53 #include <mach/imx-uart.h>
54
55 /* Register definitions */
56 #define URXD0 0x0 /* Receiver Register */
57 #define URTX0 0x40 /* Transmitter Register */
58 #define UCR1 0x80 /* Control Register 1 */
59 #define UCR2 0x84 /* Control Register 2 */
60 #define UCR3 0x88 /* Control Register 3 */
61 #define UCR4 0x8c /* Control Register 4 */
62 #define UFCR 0x90 /* FIFO Control Register */
63 #define USR1 0x94 /* Status Register 1 */
64 #define USR2 0x98 /* Status Register 2 */
65 #define UESC 0x9c /* Escape Character Register */
66 #define UTIM 0xa0 /* Escape Timer Register */
67 #define UBIR 0xa4 /* BRM Incremental Register */
68 #define UBMR 0xa8 /* BRM Modulator Register */
69 #define UBRC 0xac /* Baud Rate Count Register */
70 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
71 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
72 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
73
74 /* UART Control Register Bit Fields.*/
75 #define URXD_CHARRDY (1<<15)
76 #define URXD_ERR (1<<14)
77 #define URXD_OVRRUN (1<<13)
78 #define URXD_FRMERR (1<<12)
79 #define URXD_BRK (1<<11)
80 #define URXD_PRERR (1<<10)
81 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
82 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
83 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
84 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
85 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
86 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
87 #define UCR1_IREN (1<<7) /* Infrared interface enable */
88 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
89 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
90 #define UCR1_SNDBRK (1<<4) /* Send break */
91 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
92 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
93 #define UCR1_DOZE (1<<1) /* Doze */
94 #define UCR1_UARTEN (1<<0) /* UART enabled */
95 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
96 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
97 #define UCR2_CTSC (1<<13) /* CTS pin control */
98 #define UCR2_CTS (1<<12) /* Clear to send */
99 #define UCR2_ESCEN (1<<11) /* Escape enable */
100 #define UCR2_PREN (1<<8) /* Parity enable */
101 #define UCR2_PROE (1<<7) /* Parity odd/even */
102 #define UCR2_STPB (1<<6) /* Stop */
103 #define UCR2_WS (1<<5) /* Word size */
104 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
105 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
106 #define UCR2_RXEN (1<<1) /* Receiver enabled */
107 #define UCR2_SRST (1<<0) /* SW reset */
108 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
109 #define UCR3_PARERREN (1<<12) /* Parity enable */
110 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
111 #define UCR3_DSR (1<<10) /* Data set ready */
112 #define UCR3_DCD (1<<9) /* Data carrier detect */
113 #define UCR3_RI (1<<8) /* Ring indicator */
114 #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
115 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
116 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
117 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
118 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
119 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
120 #define UCR3_BPEN (1<<0) /* Preset registers enable */
121 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
122 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
123 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
124 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
125 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
126 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
127 #define UCR4_IRSC (1<<5) /* IR special case */
128 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
129 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
130 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
131 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
132 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
133 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
134 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
135 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
136 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
137 #define USR1_RTSS (1<<14) /* RTS pin status */
138 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
139 #define USR1_RTSD (1<<12) /* RTS delta */
140 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
141 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
142 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
143 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
144 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
145 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
146 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
147 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
148 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
149 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
150 #define USR2_IDLE (1<<12) /* Idle condition */
151 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
152 #define USR2_WAKE (1<<7) /* Wake */
153 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
154 #define USR2_TXDC (1<<3) /* Transmitter complete */
155 #define USR2_BRCD (1<<2) /* Break condition */
156 #define USR2_ORE (1<<1) /* Overrun error */
157 #define USR2_RDR (1<<0) /* Recv data ready */
158 #define UTS_FRCPERR (1<<13) /* Force parity error */
159 #define UTS_LOOP (1<<12) /* Loop tx and rx */
160 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
161 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
162 #define UTS_TXFULL (1<<4) /* TxFIFO full */
163 #define UTS_RXFULL (1<<3) /* RxFIFO full */
164 #define UTS_SOFTRST (1<<0) /* Software reset */
165
166 /* We've been assigned a range on the "Low-density serial ports" major */
167 #define SERIAL_IMX_MAJOR 207
168 #define MINOR_START 16
169 #define DEV_NAME "ttymxc"
170 #define MAX_INTERNAL_IRQ MXC_INTERNAL_IRQS
171
172 /*
173 * This determines how often we check the modem status signals
174 * for any change. They generally aren't connected to an IRQ
175 * so we have to poll them. We also check immediately before
176 * filling the TX fifo incase CTS has been dropped.
177 */
178 #define MCTRL_TIMEOUT (250*HZ/1000)
179
180 #define DRIVER_NAME "IMX-uart"
181
182 #define UART_NR 8
183
184 /* i.mx21 type uart runs on all i.mx except i.mx1 */
185 enum imx_uart_type {
186 IMX1_UART,
187 IMX21_UART,
188 };
189
190 /* device type dependent stuff */
191 struct imx_uart_data {
192 unsigned uts_reg;
193 enum imx_uart_type devtype;
194 };
195
196 struct imx_port {
197 struct uart_port port;
198 struct timer_list timer;
199 unsigned int old_status;
200 int txirq,rxirq,rtsirq;
201 unsigned int have_rtscts:1;
202 unsigned int use_irda:1;
203 unsigned int irda_inv_rx:1;
204 unsigned int irda_inv_tx:1;
205 unsigned short trcv_delay; /* transceiver delay */
206 struct clk *clk;
207 struct imx_uart_data *devdata;
208 };
209
210 #ifdef CONFIG_IRDA
211 #define USE_IRDA(sport) ((sport)->use_irda)
212 #else
213 #define USE_IRDA(sport) (0)
214 #endif
215
216 static struct imx_uart_data imx_uart_devdata[] = {
217 [IMX1_UART] = {
218 .uts_reg = IMX1_UTS,
219 .devtype = IMX1_UART,
220 },
221 [IMX21_UART] = {
222 .uts_reg = IMX21_UTS,
223 .devtype = IMX21_UART,
224 },
225 };
226
227 static struct platform_device_id imx_uart_devtype[] = {
228 {
229 .name = "imx1-uart",
230 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
231 }, {
232 .name = "imx21-uart",
233 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
234 }, {
235 /* sentinel */
236 }
237 };
238 MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
239
240 static struct of_device_id imx_uart_dt_ids[] = {
241 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
242 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
243 { /* sentinel */ }
244 };
245 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
246
247 static inline unsigned uts_reg(struct imx_port *sport)
248 {
249 return sport->devdata->uts_reg;
250 }
251
252 static inline int is_imx1_uart(struct imx_port *sport)
253 {
254 return sport->devdata->devtype == IMX1_UART;
255 }
256
257 static inline int is_imx21_uart(struct imx_port *sport)
258 {
259 return sport->devdata->devtype == IMX21_UART;
260 }
261
262 /*
263 * Handle any change of modem status signal since we were last called.
264 */
265 static void imx_mctrl_check(struct imx_port *sport)
266 {
267 unsigned int status, changed;
268
269 status = sport->port.ops->get_mctrl(&sport->port);
270 changed = status ^ sport->old_status;
271
272 if (changed == 0)
273 return;
274
275 sport->old_status = status;
276
277 if (changed & TIOCM_RI)
278 sport->port.icount.rng++;
279 if (changed & TIOCM_DSR)
280 sport->port.icount.dsr++;
281 if (changed & TIOCM_CAR)
282 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
283 if (changed & TIOCM_CTS)
284 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
285
286 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
287 }
288
289 /*
290 * This is our per-port timeout handler, for checking the
291 * modem status signals.
292 */
293 static void imx_timeout(unsigned long data)
294 {
295 struct imx_port *sport = (struct imx_port *)data;
296 unsigned long flags;
297
298 if (sport->port.state) {
299 spin_lock_irqsave(&sport->port.lock, flags);
300 imx_mctrl_check(sport);
301 spin_unlock_irqrestore(&sport->port.lock, flags);
302
303 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
304 }
305 }
306
307 /*
308 * interrupts disabled on entry
309 */
310 static void imx_stop_tx(struct uart_port *port)
311 {
312 struct imx_port *sport = (struct imx_port *)port;
313 unsigned long temp;
314
315 if (USE_IRDA(sport)) {
316 /* half duplex - wait for end of transmission */
317 int n = 256;
318 while ((--n > 0) &&
319 !(readl(sport->port.membase + USR2) & USR2_TXDC)) {
320 udelay(5);
321 barrier();
322 }
323 /*
324 * irda transceiver - wait a bit more to avoid
325 * cutoff, hardware dependent
326 */
327 udelay(sport->trcv_delay);
328
329 /*
330 * half duplex - reactivate receive mode,
331 * flush receive pipe echo crap
332 */
333 if (readl(sport->port.membase + USR2) & USR2_TXDC) {
334 temp = readl(sport->port.membase + UCR1);
335 temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN);
336 writel(temp, sport->port.membase + UCR1);
337
338 temp = readl(sport->port.membase + UCR4);
339 temp &= ~(UCR4_TCEN);
340 writel(temp, sport->port.membase + UCR4);
341
342 while (readl(sport->port.membase + URXD0) &
343 URXD_CHARRDY)
344 barrier();
345
346 temp = readl(sport->port.membase + UCR1);
347 temp |= UCR1_RRDYEN;
348 writel(temp, sport->port.membase + UCR1);
349
350 temp = readl(sport->port.membase + UCR4);
351 temp |= UCR4_DREN;
352 writel(temp, sport->port.membase + UCR4);
353 }
354 return;
355 }
356
357 temp = readl(sport->port.membase + UCR1);
358 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
359 }
360
361 /*
362 * interrupts disabled on entry
363 */
364 static void imx_stop_rx(struct uart_port *port)
365 {
366 struct imx_port *sport = (struct imx_port *)port;
367 unsigned long temp;
368
369 temp = readl(sport->port.membase + UCR2);
370 writel(temp &~ UCR2_RXEN, sport->port.membase + UCR2);
371 }
372
373 /*
374 * Set the modem control timer to fire immediately.
375 */
376 static void imx_enable_ms(struct uart_port *port)
377 {
378 struct imx_port *sport = (struct imx_port *)port;
379
380 mod_timer(&sport->timer, jiffies);
381 }
382
383 static inline void imx_transmit_buffer(struct imx_port *sport)
384 {
385 struct circ_buf *xmit = &sport->port.state->xmit;
386
387 while (!uart_circ_empty(xmit) &&
388 !(readl(sport->port.membase + uts_reg(sport))
389 & UTS_TXFULL)) {
390 /* send xmit->buf[xmit->tail]
391 * out the port here */
392 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
393 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
394 sport->port.icount.tx++;
395 }
396
397 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
398 uart_write_wakeup(&sport->port);
399
400 if (uart_circ_empty(xmit))
401 imx_stop_tx(&sport->port);
402 }
403
404 /*
405 * interrupts disabled on entry
406 */
407 static void imx_start_tx(struct uart_port *port)
408 {
409 struct imx_port *sport = (struct imx_port *)port;
410 unsigned long temp;
411
412 if (USE_IRDA(sport)) {
413 /* half duplex in IrDA mode; have to disable receive mode */
414 temp = readl(sport->port.membase + UCR4);
415 temp &= ~(UCR4_DREN);
416 writel(temp, sport->port.membase + UCR4);
417
418 temp = readl(sport->port.membase + UCR1);
419 temp &= ~(UCR1_RRDYEN);
420 writel(temp, sport->port.membase + UCR1);
421 }
422
423 temp = readl(sport->port.membase + UCR1);
424 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
425
426 if (USE_IRDA(sport)) {
427 temp = readl(sport->port.membase + UCR1);
428 temp |= UCR1_TRDYEN;
429 writel(temp, sport->port.membase + UCR1);
430
431 temp = readl(sport->port.membase + UCR4);
432 temp |= UCR4_TCEN;
433 writel(temp, sport->port.membase + UCR4);
434 }
435
436 if (readl(sport->port.membase + uts_reg(sport)) & UTS_TXEMPTY)
437 imx_transmit_buffer(sport);
438 }
439
440 static irqreturn_t imx_rtsint(int irq, void *dev_id)
441 {
442 struct imx_port *sport = dev_id;
443 unsigned int val;
444 unsigned long flags;
445
446 spin_lock_irqsave(&sport->port.lock, flags);
447
448 writel(USR1_RTSD, sport->port.membase + USR1);
449 val = readl(sport->port.membase + USR1) & USR1_RTSS;
450 uart_handle_cts_change(&sport->port, !!val);
451 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
452
453 spin_unlock_irqrestore(&sport->port.lock, flags);
454 return IRQ_HANDLED;
455 }
456
457 static irqreturn_t imx_txint(int irq, void *dev_id)
458 {
459 struct imx_port *sport = dev_id;
460 struct circ_buf *xmit = &sport->port.state->xmit;
461 unsigned long flags;
462
463 spin_lock_irqsave(&sport->port.lock,flags);
464 if (sport->port.x_char)
465 {
466 /* Send next char */
467 writel(sport->port.x_char, sport->port.membase + URTX0);
468 goto out;
469 }
470
471 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
472 imx_stop_tx(&sport->port);
473 goto out;
474 }
475
476 imx_transmit_buffer(sport);
477
478 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
479 uart_write_wakeup(&sport->port);
480
481 out:
482 spin_unlock_irqrestore(&sport->port.lock,flags);
483 return IRQ_HANDLED;
484 }
485
486 static irqreturn_t imx_rxint(int irq, void *dev_id)
487 {
488 struct imx_port *sport = dev_id;
489 unsigned int rx,flg,ignored = 0;
490 struct tty_struct *tty = sport->port.state->port.tty;
491 unsigned long flags, temp;
492
493 spin_lock_irqsave(&sport->port.lock,flags);
494
495 while (readl(sport->port.membase + USR2) & USR2_RDR) {
496 flg = TTY_NORMAL;
497 sport->port.icount.rx++;
498
499 rx = readl(sport->port.membase + URXD0);
500
501 temp = readl(sport->port.membase + USR2);
502 if (temp & USR2_BRCD) {
503 writel(USR2_BRCD, sport->port.membase + USR2);
504 if (uart_handle_break(&sport->port))
505 continue;
506 }
507
508 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
509 continue;
510
511 if (unlikely(rx & URXD_ERR)) {
512 if (rx & URXD_BRK)
513 sport->port.icount.brk++;
514 else if (rx & URXD_PRERR)
515 sport->port.icount.parity++;
516 else if (rx & URXD_FRMERR)
517 sport->port.icount.frame++;
518 if (rx & URXD_OVRRUN)
519 sport->port.icount.overrun++;
520
521 if (rx & sport->port.ignore_status_mask) {
522 if (++ignored > 100)
523 goto out;
524 continue;
525 }
526
527 rx &= sport->port.read_status_mask;
528
529 if (rx & URXD_BRK)
530 flg = TTY_BREAK;
531 else if (rx & URXD_PRERR)
532 flg = TTY_PARITY;
533 else if (rx & URXD_FRMERR)
534 flg = TTY_FRAME;
535 if (rx & URXD_OVRRUN)
536 flg = TTY_OVERRUN;
537
538 #ifdef SUPPORT_SYSRQ
539 sport->port.sysrq = 0;
540 #endif
541 }
542
543 tty_insert_flip_char(tty, rx, flg);
544 }
545
546 out:
547 spin_unlock_irqrestore(&sport->port.lock,flags);
548 tty_flip_buffer_push(tty);
549 return IRQ_HANDLED;
550 }
551
552 static irqreturn_t imx_int(int irq, void *dev_id)
553 {
554 struct imx_port *sport = dev_id;
555 unsigned int sts;
556
557 sts = readl(sport->port.membase + USR1);
558
559 if (sts & USR1_RRDY)
560 imx_rxint(irq, dev_id);
561
562 if (sts & USR1_TRDY &&
563 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)
564 imx_txint(irq, dev_id);
565
566 if (sts & USR1_RTSD)
567 imx_rtsint(irq, dev_id);
568
569 return IRQ_HANDLED;
570 }
571
572 /*
573 * Return TIOCSER_TEMT when transmitter is not busy.
574 */
575 static unsigned int imx_tx_empty(struct uart_port *port)
576 {
577 struct imx_port *sport = (struct imx_port *)port;
578
579 return (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
580 }
581
582 /*
583 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
584 */
585 static unsigned int imx_get_mctrl(struct uart_port *port)
586 {
587 struct imx_port *sport = (struct imx_port *)port;
588 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
589
590 if (readl(sport->port.membase + USR1) & USR1_RTSS)
591 tmp |= TIOCM_CTS;
592
593 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
594 tmp |= TIOCM_RTS;
595
596 return tmp;
597 }
598
599 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
600 {
601 struct imx_port *sport = (struct imx_port *)port;
602 unsigned long temp;
603
604 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
605
606 if (mctrl & TIOCM_RTS)
607 temp |= UCR2_CTS;
608
609 writel(temp, sport->port.membase + UCR2);
610 }
611
612 /*
613 * Interrupts always disabled.
614 */
615 static void imx_break_ctl(struct uart_port *port, int break_state)
616 {
617 struct imx_port *sport = (struct imx_port *)port;
618 unsigned long flags, temp;
619
620 spin_lock_irqsave(&sport->port.lock, flags);
621
622 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
623
624 if ( break_state != 0 )
625 temp |= UCR1_SNDBRK;
626
627 writel(temp, sport->port.membase + UCR1);
628
629 spin_unlock_irqrestore(&sport->port.lock, flags);
630 }
631
632 #define TXTL 2 /* reset default */
633 #define RXTL 1 /* reset default */
634
635 static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
636 {
637 unsigned int val;
638 unsigned int ufcr_rfdiv;
639
640 /* set receiver / transmitter trigger level.
641 * RFDIV is set such way to satisfy requested uartclk value
642 */
643 val = TXTL << 10 | RXTL;
644 ufcr_rfdiv = (clk_get_rate(sport->clk) + sport->port.uartclk / 2)
645 / sport->port.uartclk;
646
647 if(!ufcr_rfdiv)
648 ufcr_rfdiv = 1;
649
650 val |= UFCR_RFDIV_REG(ufcr_rfdiv);
651
652 writel(val, sport->port.membase + UFCR);
653
654 return 0;
655 }
656
657 /* half the RX buffer size */
658 #define CTSTL 16
659
660 static int imx_startup(struct uart_port *port)
661 {
662 struct imx_port *sport = (struct imx_port *)port;
663 int retval;
664 unsigned long flags, temp;
665
666 imx_setup_ufcr(sport, 0);
667
668 /* disable the DREN bit (Data Ready interrupt enable) before
669 * requesting IRQs
670 */
671 temp = readl(sport->port.membase + UCR4);
672
673 if (USE_IRDA(sport))
674 temp |= UCR4_IRSC;
675
676 /* set the trigger level for CTS */
677 temp &= ~(UCR4_CTSTL_MASK<< UCR4_CTSTL_SHF);
678 temp |= CTSTL<< UCR4_CTSTL_SHF;
679
680 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
681
682 if (USE_IRDA(sport)) {
683 /* reset fifo's and state machines */
684 int i = 100;
685 temp = readl(sport->port.membase + UCR2);
686 temp &= ~UCR2_SRST;
687 writel(temp, sport->port.membase + UCR2);
688 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) &&
689 (--i > 0)) {
690 udelay(1);
691 }
692 }
693
694 /*
695 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
696 * chips only have one interrupt.
697 */
698 if (sport->txirq > 0) {
699 retval = request_irq(sport->rxirq, imx_rxint, 0,
700 DRIVER_NAME, sport);
701 if (retval)
702 goto error_out1;
703
704 retval = request_irq(sport->txirq, imx_txint, 0,
705 DRIVER_NAME, sport);
706 if (retval)
707 goto error_out2;
708
709 /* do not use RTS IRQ on IrDA */
710 if (!USE_IRDA(sport)) {
711 retval = request_irq(sport->rtsirq, imx_rtsint,
712 (sport->rtsirq < MAX_INTERNAL_IRQ) ? 0 :
713 IRQF_TRIGGER_FALLING |
714 IRQF_TRIGGER_RISING,
715 DRIVER_NAME, sport);
716 if (retval)
717 goto error_out3;
718 }
719 } else {
720 retval = request_irq(sport->port.irq, imx_int, 0,
721 DRIVER_NAME, sport);
722 if (retval) {
723 free_irq(sport->port.irq, sport);
724 goto error_out1;
725 }
726 }
727
728 /*
729 * Finally, clear and enable interrupts
730 */
731 writel(USR1_RTSD, sport->port.membase + USR1);
732
733 temp = readl(sport->port.membase + UCR1);
734 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
735
736 if (USE_IRDA(sport)) {
737 temp |= UCR1_IREN;
738 temp &= ~(UCR1_RTSDEN);
739 }
740
741 writel(temp, sport->port.membase + UCR1);
742
743 temp = readl(sport->port.membase + UCR2);
744 temp |= (UCR2_RXEN | UCR2_TXEN);
745 writel(temp, sport->port.membase + UCR2);
746
747 if (USE_IRDA(sport)) {
748 /* clear RX-FIFO */
749 int i = 64;
750 while ((--i > 0) &&
751 (readl(sport->port.membase + URXD0) & URXD_CHARRDY)) {
752 barrier();
753 }
754 }
755
756 if (is_imx21_uart(sport)) {
757 temp = readl(sport->port.membase + UCR3);
758 temp |= IMX21_UCR3_RXDMUXSEL;
759 writel(temp, sport->port.membase + UCR3);
760 }
761
762 if (USE_IRDA(sport)) {
763 temp = readl(sport->port.membase + UCR4);
764 if (sport->irda_inv_rx)
765 temp |= UCR4_INVR;
766 else
767 temp &= ~(UCR4_INVR);
768 writel(temp | UCR4_DREN, sport->port.membase + UCR4);
769
770 temp = readl(sport->port.membase + UCR3);
771 if (sport->irda_inv_tx)
772 temp |= UCR3_INVT;
773 else
774 temp &= ~(UCR3_INVT);
775 writel(temp, sport->port.membase + UCR3);
776 }
777
778 /*
779 * Enable modem status interrupts
780 */
781 spin_lock_irqsave(&sport->port.lock,flags);
782 imx_enable_ms(&sport->port);
783 spin_unlock_irqrestore(&sport->port.lock,flags);
784
785 if (USE_IRDA(sport)) {
786 struct imxuart_platform_data *pdata;
787 pdata = sport->port.dev->platform_data;
788 sport->irda_inv_rx = pdata->irda_inv_rx;
789 sport->irda_inv_tx = pdata->irda_inv_tx;
790 sport->trcv_delay = pdata->transceiver_delay;
791 if (pdata->irda_enable)
792 pdata->irda_enable(1);
793 }
794
795 return 0;
796
797 error_out3:
798 if (sport->txirq)
799 free_irq(sport->txirq, sport);
800 error_out2:
801 if (sport->rxirq)
802 free_irq(sport->rxirq, sport);
803 error_out1:
804 return retval;
805 }
806
807 static void imx_shutdown(struct uart_port *port)
808 {
809 struct imx_port *sport = (struct imx_port *)port;
810 unsigned long temp;
811
812 temp = readl(sport->port.membase + UCR2);
813 temp &= ~(UCR2_TXEN);
814 writel(temp, sport->port.membase + UCR2);
815
816 if (USE_IRDA(sport)) {
817 struct imxuart_platform_data *pdata;
818 pdata = sport->port.dev->platform_data;
819 if (pdata->irda_enable)
820 pdata->irda_enable(0);
821 }
822
823 /*
824 * Stop our timer.
825 */
826 del_timer_sync(&sport->timer);
827
828 /*
829 * Free the interrupts
830 */
831 if (sport->txirq > 0) {
832 if (!USE_IRDA(sport))
833 free_irq(sport->rtsirq, sport);
834 free_irq(sport->txirq, sport);
835 free_irq(sport->rxirq, sport);
836 } else
837 free_irq(sport->port.irq, sport);
838
839 /*
840 * Disable all interrupts, port and break condition.
841 */
842
843 temp = readl(sport->port.membase + UCR1);
844 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
845 if (USE_IRDA(sport))
846 temp &= ~(UCR1_IREN);
847
848 writel(temp, sport->port.membase + UCR1);
849 }
850
851 static void
852 imx_set_termios(struct uart_port *port, struct ktermios *termios,
853 struct ktermios *old)
854 {
855 struct imx_port *sport = (struct imx_port *)port;
856 unsigned long flags;
857 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
858 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
859 unsigned int div, ufcr;
860 unsigned long num, denom;
861 uint64_t tdiv64;
862
863 /*
864 * If we don't support modem control lines, don't allow
865 * these to be set.
866 */
867 if (0) {
868 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
869 termios->c_cflag |= CLOCAL;
870 }
871
872 /*
873 * We only support CS7 and CS8.
874 */
875 while ((termios->c_cflag & CSIZE) != CS7 &&
876 (termios->c_cflag & CSIZE) != CS8) {
877 termios->c_cflag &= ~CSIZE;
878 termios->c_cflag |= old_csize;
879 old_csize = CS8;
880 }
881
882 if ((termios->c_cflag & CSIZE) == CS8)
883 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
884 else
885 ucr2 = UCR2_SRST | UCR2_IRTS;
886
887 if (termios->c_cflag & CRTSCTS) {
888 if( sport->have_rtscts ) {
889 ucr2 &= ~UCR2_IRTS;
890 ucr2 |= UCR2_CTSC;
891 } else {
892 termios->c_cflag &= ~CRTSCTS;
893 }
894 }
895
896 if (termios->c_cflag & CSTOPB)
897 ucr2 |= UCR2_STPB;
898 if (termios->c_cflag & PARENB) {
899 ucr2 |= UCR2_PREN;
900 if (termios->c_cflag & PARODD)
901 ucr2 |= UCR2_PROE;
902 }
903
904 /*
905 * Ask the core to calculate the divisor for us.
906 */
907 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
908 quot = uart_get_divisor(port, baud);
909
910 spin_lock_irqsave(&sport->port.lock, flags);
911
912 sport->port.read_status_mask = 0;
913 if (termios->c_iflag & INPCK)
914 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
915 if (termios->c_iflag & (BRKINT | PARMRK))
916 sport->port.read_status_mask |= URXD_BRK;
917
918 /*
919 * Characters to ignore
920 */
921 sport->port.ignore_status_mask = 0;
922 if (termios->c_iflag & IGNPAR)
923 sport->port.ignore_status_mask |= URXD_PRERR;
924 if (termios->c_iflag & IGNBRK) {
925 sport->port.ignore_status_mask |= URXD_BRK;
926 /*
927 * If we're ignoring parity and break indicators,
928 * ignore overruns too (for real raw support).
929 */
930 if (termios->c_iflag & IGNPAR)
931 sport->port.ignore_status_mask |= URXD_OVRRUN;
932 }
933
934 del_timer_sync(&sport->timer);
935
936 /*
937 * Update the per-port timeout.
938 */
939 uart_update_timeout(port, termios->c_cflag, baud);
940
941 /*
942 * disable interrupts and drain transmitter
943 */
944 old_ucr1 = readl(sport->port.membase + UCR1);
945 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
946 sport->port.membase + UCR1);
947
948 while ( !(readl(sport->port.membase + USR2) & USR2_TXDC))
949 barrier();
950
951 /* then, disable everything */
952 old_txrxen = readl(sport->port.membase + UCR2);
953 writel(old_txrxen & ~( UCR2_TXEN | UCR2_RXEN),
954 sport->port.membase + UCR2);
955 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
956
957 if (USE_IRDA(sport)) {
958 /*
959 * use maximum available submodule frequency to
960 * avoid missing short pulses due to low sampling rate
961 */
962 div = 1;
963 } else {
964 div = sport->port.uartclk / (baud * 16);
965 if (div > 7)
966 div = 7;
967 if (!div)
968 div = 1;
969 }
970
971 rational_best_approximation(16 * div * baud, sport->port.uartclk,
972 1 << 16, 1 << 16, &num, &denom);
973
974 tdiv64 = sport->port.uartclk;
975 tdiv64 *= num;
976 do_div(tdiv64, denom * 16 * div);
977 tty_termios_encode_baud_rate(termios,
978 (speed_t)tdiv64, (speed_t)tdiv64);
979
980 num -= 1;
981 denom -= 1;
982
983 ufcr = readl(sport->port.membase + UFCR);
984 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
985 writel(ufcr, sport->port.membase + UFCR);
986
987 writel(num, sport->port.membase + UBIR);
988 writel(denom, sport->port.membase + UBMR);
989
990 if (is_imx21_uart(sport))
991 writel(sport->port.uartclk / div / 1000,
992 sport->port.membase + IMX21_ONEMS);
993
994 writel(old_ucr1, sport->port.membase + UCR1);
995
996 /* set the parity, stop bits and data size */
997 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
998
999 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1000 imx_enable_ms(&sport->port);
1001
1002 spin_unlock_irqrestore(&sport->port.lock, flags);
1003 }
1004
1005 static const char *imx_type(struct uart_port *port)
1006 {
1007 struct imx_port *sport = (struct imx_port *)port;
1008
1009 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1010 }
1011
1012 /*
1013 * Release the memory region(s) being used by 'port'.
1014 */
1015 static void imx_release_port(struct uart_port *port)
1016 {
1017 struct platform_device *pdev = to_platform_device(port->dev);
1018 struct resource *mmres;
1019
1020 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1021 release_mem_region(mmres->start, resource_size(mmres));
1022 }
1023
1024 /*
1025 * Request the memory region(s) being used by 'port'.
1026 */
1027 static int imx_request_port(struct uart_port *port)
1028 {
1029 struct platform_device *pdev = to_platform_device(port->dev);
1030 struct resource *mmres;
1031 void *ret;
1032
1033 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1034 if (!mmres)
1035 return -ENODEV;
1036
1037 ret = request_mem_region(mmres->start, resource_size(mmres), "imx-uart");
1038
1039 return ret ? 0 : -EBUSY;
1040 }
1041
1042 /*
1043 * Configure/autoconfigure the port.
1044 */
1045 static void imx_config_port(struct uart_port *port, int flags)
1046 {
1047 struct imx_port *sport = (struct imx_port *)port;
1048
1049 if (flags & UART_CONFIG_TYPE &&
1050 imx_request_port(&sport->port) == 0)
1051 sport->port.type = PORT_IMX;
1052 }
1053
1054 /*
1055 * Verify the new serial_struct (for TIOCSSERIAL).
1056 * The only change we allow are to the flags and type, and
1057 * even then only between PORT_IMX and PORT_UNKNOWN
1058 */
1059 static int
1060 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1061 {
1062 struct imx_port *sport = (struct imx_port *)port;
1063 int ret = 0;
1064
1065 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1066 ret = -EINVAL;
1067 if (sport->port.irq != ser->irq)
1068 ret = -EINVAL;
1069 if (ser->io_type != UPIO_MEM)
1070 ret = -EINVAL;
1071 if (sport->port.uartclk / 16 != ser->baud_base)
1072 ret = -EINVAL;
1073 if ((void *)sport->port.mapbase != ser->iomem_base)
1074 ret = -EINVAL;
1075 if (sport->port.iobase != ser->port)
1076 ret = -EINVAL;
1077 if (ser->hub6 != 0)
1078 ret = -EINVAL;
1079 return ret;
1080 }
1081
1082 static struct uart_ops imx_pops = {
1083 .tx_empty = imx_tx_empty,
1084 .set_mctrl = imx_set_mctrl,
1085 .get_mctrl = imx_get_mctrl,
1086 .stop_tx = imx_stop_tx,
1087 .start_tx = imx_start_tx,
1088 .stop_rx = imx_stop_rx,
1089 .enable_ms = imx_enable_ms,
1090 .break_ctl = imx_break_ctl,
1091 .startup = imx_startup,
1092 .shutdown = imx_shutdown,
1093 .set_termios = imx_set_termios,
1094 .type = imx_type,
1095 .release_port = imx_release_port,
1096 .request_port = imx_request_port,
1097 .config_port = imx_config_port,
1098 .verify_port = imx_verify_port,
1099 };
1100
1101 static struct imx_port *imx_ports[UART_NR];
1102
1103 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1104 static void imx_console_putchar(struct uart_port *port, int ch)
1105 {
1106 struct imx_port *sport = (struct imx_port *)port;
1107
1108 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
1109 barrier();
1110
1111 writel(ch, sport->port.membase + URTX0);
1112 }
1113
1114 /*
1115 * Interrupts are disabled on entering
1116 */
1117 static void
1118 imx_console_write(struct console *co, const char *s, unsigned int count)
1119 {
1120 struct imx_port *sport = imx_ports[co->index];
1121 unsigned int old_ucr1, old_ucr2, ucr1;
1122
1123 /*
1124 * First, save UCR1/2 and then disable interrupts
1125 */
1126 ucr1 = old_ucr1 = readl(sport->port.membase + UCR1);
1127 old_ucr2 = readl(sport->port.membase + UCR2);
1128
1129 if (is_imx1_uart(sport))
1130 ucr1 |= IMX1_UCR1_UARTCLKEN;
1131 ucr1 |= UCR1_UARTEN;
1132 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1133
1134 writel(ucr1, sport->port.membase + UCR1);
1135
1136 writel(old_ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1137
1138 uart_console_write(&sport->port, s, count, imx_console_putchar);
1139
1140 /*
1141 * Finally, wait for transmitter to become empty
1142 * and restore UCR1/2
1143 */
1144 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1145
1146 writel(old_ucr1, sport->port.membase + UCR1);
1147 writel(old_ucr2, sport->port.membase + UCR2);
1148 }
1149
1150 /*
1151 * If the port was already initialised (eg, by a boot loader),
1152 * try to determine the current setup.
1153 */
1154 static void __init
1155 imx_console_get_options(struct imx_port *sport, int *baud,
1156 int *parity, int *bits)
1157 {
1158
1159 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1160 /* ok, the port was enabled */
1161 unsigned int ucr2, ubir,ubmr, uartclk;
1162 unsigned int baud_raw;
1163 unsigned int ucfr_rfdiv;
1164
1165 ucr2 = readl(sport->port.membase + UCR2);
1166
1167 *parity = 'n';
1168 if (ucr2 & UCR2_PREN) {
1169 if (ucr2 & UCR2_PROE)
1170 *parity = 'o';
1171 else
1172 *parity = 'e';
1173 }
1174
1175 if (ucr2 & UCR2_WS)
1176 *bits = 8;
1177 else
1178 *bits = 7;
1179
1180 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1181 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1182
1183 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1184 if (ucfr_rfdiv == 6)
1185 ucfr_rfdiv = 7;
1186 else
1187 ucfr_rfdiv = 6 - ucfr_rfdiv;
1188
1189 uartclk = clk_get_rate(sport->clk);
1190 uartclk /= ucfr_rfdiv;
1191
1192 { /*
1193 * The next code provides exact computation of
1194 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1195 * without need of float support or long long division,
1196 * which would be required to prevent 32bit arithmetic overflow
1197 */
1198 unsigned int mul = ubir + 1;
1199 unsigned int div = 16 * (ubmr + 1);
1200 unsigned int rem = uartclk % div;
1201
1202 baud_raw = (uartclk / div) * mul;
1203 baud_raw += (rem * mul + div / 2) / div;
1204 *baud = (baud_raw + 50) / 100 * 100;
1205 }
1206
1207 if(*baud != baud_raw)
1208 printk(KERN_INFO "Serial: Console IMX rounded baud rate from %d to %d\n",
1209 baud_raw, *baud);
1210 }
1211 }
1212
1213 static int __init
1214 imx_console_setup(struct console *co, char *options)
1215 {
1216 struct imx_port *sport;
1217 int baud = 9600;
1218 int bits = 8;
1219 int parity = 'n';
1220 int flow = 'n';
1221
1222 /*
1223 * Check whether an invalid uart number has been specified, and
1224 * if so, search for the first available port that does have
1225 * console support.
1226 */
1227 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1228 co->index = 0;
1229 sport = imx_ports[co->index];
1230 if(sport == NULL)
1231 return -ENODEV;
1232
1233 if (options)
1234 uart_parse_options(options, &baud, &parity, &bits, &flow);
1235 else
1236 imx_console_get_options(sport, &baud, &parity, &bits);
1237
1238 imx_setup_ufcr(sport, 0);
1239
1240 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
1241 }
1242
1243 static struct uart_driver imx_reg;
1244 static struct console imx_console = {
1245 .name = DEV_NAME,
1246 .write = imx_console_write,
1247 .device = uart_console_device,
1248 .setup = imx_console_setup,
1249 .flags = CON_PRINTBUFFER,
1250 .index = -1,
1251 .data = &imx_reg,
1252 };
1253
1254 #define IMX_CONSOLE &imx_console
1255 #else
1256 #define IMX_CONSOLE NULL
1257 #endif
1258
1259 static struct uart_driver imx_reg = {
1260 .owner = THIS_MODULE,
1261 .driver_name = DRIVER_NAME,
1262 .dev_name = DEV_NAME,
1263 .major = SERIAL_IMX_MAJOR,
1264 .minor = MINOR_START,
1265 .nr = ARRAY_SIZE(imx_ports),
1266 .cons = IMX_CONSOLE,
1267 };
1268
1269 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1270 {
1271 struct imx_port *sport = platform_get_drvdata(dev);
1272
1273 if (sport)
1274 uart_suspend_port(&imx_reg, &sport->port);
1275
1276 return 0;
1277 }
1278
1279 static int serial_imx_resume(struct platform_device *dev)
1280 {
1281 struct imx_port *sport = platform_get_drvdata(dev);
1282
1283 if (sport)
1284 uart_resume_port(&imx_reg, &sport->port);
1285
1286 return 0;
1287 }
1288
1289 #ifdef CONFIG_OF
1290 static int serial_imx_probe_dt(struct imx_port *sport,
1291 struct platform_device *pdev)
1292 {
1293 static int portnum = 0;
1294 struct device_node *np = pdev->dev.of_node;
1295 const struct of_device_id *of_id =
1296 of_match_device(imx_uart_dt_ids, &pdev->dev);
1297
1298 if (!np)
1299 return -ENODEV;
1300
1301 sport->port.line = portnum++;
1302 if (sport->port.line >= UART_NR)
1303 return -EINVAL;
1304
1305 if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1306 sport->have_rtscts = 1;
1307
1308 if (of_get_property(np, "fsl,irda-mode", NULL))
1309 sport->use_irda = 1;
1310
1311 sport->devdata = of_id->data;
1312
1313 return 0;
1314 }
1315 #else
1316 static inline int serial_imx_probe_dt(struct imx_port *sport,
1317 struct platform_device *pdev)
1318 {
1319 return -ENODEV;
1320 }
1321 #endif
1322
1323 static void serial_imx_probe_pdata(struct imx_port *sport,
1324 struct platform_device *pdev)
1325 {
1326 struct imxuart_platform_data *pdata = pdev->dev.platform_data;
1327
1328 sport->port.line = pdev->id;
1329 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
1330
1331 if (!pdata)
1332 return;
1333
1334 if (pdata->flags & IMXUART_HAVE_RTSCTS)
1335 sport->have_rtscts = 1;
1336
1337 if (pdata->flags & IMXUART_IRDA)
1338 sport->use_irda = 1;
1339 }
1340
1341 static int serial_imx_probe(struct platform_device *pdev)
1342 {
1343 struct imx_port *sport;
1344 struct imxuart_platform_data *pdata;
1345 void __iomem *base;
1346 int ret = 0;
1347 struct resource *res;
1348
1349 sport = kzalloc(sizeof(*sport), GFP_KERNEL);
1350 if (!sport)
1351 return -ENOMEM;
1352
1353 ret = serial_imx_probe_dt(sport, pdev);
1354 if (ret == -ENODEV)
1355 serial_imx_probe_pdata(sport, pdev);
1356
1357 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1358 if (!res) {
1359 ret = -ENODEV;
1360 goto free;
1361 }
1362
1363 base = ioremap(res->start, PAGE_SIZE);
1364 if (!base) {
1365 ret = -ENOMEM;
1366 goto free;
1367 }
1368
1369 sport->port.dev = &pdev->dev;
1370 sport->port.mapbase = res->start;
1371 sport->port.membase = base;
1372 sport->port.type = PORT_IMX,
1373 sport->port.iotype = UPIO_MEM;
1374 sport->port.irq = platform_get_irq(pdev, 0);
1375 sport->rxirq = platform_get_irq(pdev, 0);
1376 sport->txirq = platform_get_irq(pdev, 1);
1377 sport->rtsirq = platform_get_irq(pdev, 2);
1378 sport->port.fifosize = 32;
1379 sport->port.ops = &imx_pops;
1380 sport->port.flags = UPF_BOOT_AUTOCONF;
1381 init_timer(&sport->timer);
1382 sport->timer.function = imx_timeout;
1383 sport->timer.data = (unsigned long)sport;
1384
1385 sport->clk = clk_get(&pdev->dev, "uart");
1386 if (IS_ERR(sport->clk)) {
1387 ret = PTR_ERR(sport->clk);
1388 goto unmap;
1389 }
1390 clk_enable(sport->clk);
1391
1392 sport->port.uartclk = clk_get_rate(sport->clk);
1393
1394 imx_ports[sport->port.line] = sport;
1395
1396 pdata = pdev->dev.platform_data;
1397 if (pdata && pdata->init) {
1398 ret = pdata->init(pdev);
1399 if (ret)
1400 goto clkput;
1401 }
1402
1403 ret = uart_add_one_port(&imx_reg, &sport->port);
1404 if (ret)
1405 goto deinit;
1406 platform_set_drvdata(pdev, &sport->port);
1407
1408 return 0;
1409 deinit:
1410 if (pdata && pdata->exit)
1411 pdata->exit(pdev);
1412 clkput:
1413 clk_put(sport->clk);
1414 clk_disable(sport->clk);
1415 unmap:
1416 iounmap(sport->port.membase);
1417 free:
1418 kfree(sport);
1419
1420 return ret;
1421 }
1422
1423 static int serial_imx_remove(struct platform_device *pdev)
1424 {
1425 struct imxuart_platform_data *pdata;
1426 struct imx_port *sport = platform_get_drvdata(pdev);
1427
1428 pdata = pdev->dev.platform_data;
1429
1430 platform_set_drvdata(pdev, NULL);
1431
1432 if (sport) {
1433 uart_remove_one_port(&imx_reg, &sport->port);
1434 clk_put(sport->clk);
1435 }
1436
1437 clk_disable(sport->clk);
1438
1439 if (pdata && pdata->exit)
1440 pdata->exit(pdev);
1441
1442 iounmap(sport->port.membase);
1443 kfree(sport);
1444
1445 return 0;
1446 }
1447
1448 static struct platform_driver serial_imx_driver = {
1449 .probe = serial_imx_probe,
1450 .remove = serial_imx_remove,
1451
1452 .suspend = serial_imx_suspend,
1453 .resume = serial_imx_resume,
1454 .id_table = imx_uart_devtype,
1455 .driver = {
1456 .name = "imx-uart",
1457 .owner = THIS_MODULE,
1458 .of_match_table = imx_uart_dt_ids,
1459 },
1460 };
1461
1462 static int __init imx_serial_init(void)
1463 {
1464 int ret;
1465
1466 printk(KERN_INFO "Serial: IMX driver\n");
1467
1468 ret = uart_register_driver(&imx_reg);
1469 if (ret)
1470 return ret;
1471
1472 ret = platform_driver_register(&serial_imx_driver);
1473 if (ret != 0)
1474 uart_unregister_driver(&imx_reg);
1475
1476 return 0;
1477 }
1478
1479 static void __exit imx_serial_exit(void)
1480 {
1481 platform_driver_unregister(&serial_imx_driver);
1482 uart_unregister_driver(&imx_reg);
1483 }
1484
1485 module_init(imx_serial_init);
1486 module_exit(imx_serial_exit);
1487
1488 MODULE_AUTHOR("Sascha Hauer");
1489 MODULE_DESCRIPTION("IMX generic serial port driver");
1490 MODULE_LICENSE("GPL");
1491 MODULE_ALIAS("platform:imx-uart");
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