?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Add linux-next specific files for 20110516
[linux-2.6/next.git] / arch / arm / mach-omap2 / io.c
blob441e79d043a71245bde9b5e4256a88a8eabb2367
1 /*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments
8 *
9 * Author:
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
12 *
13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/io.h>
24 #include <linux/clk.h>
25 #include <linux/omapfb.h>
26
27 #include <asm/tlb.h>
28
29 #include <asm/mach/map.h>
30
31 #include <plat/sram.h>
32 #include <plat/sdrc.h>
33 #include <plat/serial.h>
34
35 #include "clock2xxx.h"
36 #include "clock3xxx.h"
37 #include "clock44xx.h"
38 #include "io.h"
39
40 #include <plat/omap-pm.h>
41 #include "powerdomain.h"
42
43 #include "clockdomain.h"
44 #include <plat/omap_hwmod.h>
45 #include <plat/multi.h>
46
47 /*
48 * The machine specific code may provide the extra mapping besides the
49 * default mapping provided here.
50 */
51
52 #ifdef CONFIG_ARCH_OMAP2
53 static struct map_desc omap24xx_io_desc[] __initdata = {
54 {
55 .virtual = L3_24XX_VIRT,
56 .pfn = __phys_to_pfn(L3_24XX_PHYS),
57 .length = L3_24XX_SIZE,
58 .type = MT_DEVICE
59 },
60 {
61 .virtual = L4_24XX_VIRT,
62 .pfn = __phys_to_pfn(L4_24XX_PHYS),
63 .length = L4_24XX_SIZE,
64 .type = MT_DEVICE
65 },
66 };
67
68 #ifdef CONFIG_SOC_OMAP2420
69 static struct map_desc omap242x_io_desc[] __initdata = {
70 {
71 .virtual = DSP_MEM_2420_VIRT,
72 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
73 .length = DSP_MEM_2420_SIZE,
74 .type = MT_DEVICE
75 },
76 {
77 .virtual = DSP_IPI_2420_VIRT,
78 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
79 .length = DSP_IPI_2420_SIZE,
80 .type = MT_DEVICE
81 },
82 {
83 .virtual = DSP_MMU_2420_VIRT,
84 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
85 .length = DSP_MMU_2420_SIZE,
86 .type = MT_DEVICE
87 },
88 };
89
90 #endif
91
92 #ifdef CONFIG_SOC_OMAP2430
93 static struct map_desc omap243x_io_desc[] __initdata = {
94 {
95 .virtual = L4_WK_243X_VIRT,
96 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
97 .length = L4_WK_243X_SIZE,
98 .type = MT_DEVICE
99 },
100 {
101 .virtual = OMAP243X_GPMC_VIRT,
102 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
103 .length = OMAP243X_GPMC_SIZE,
104 .type = MT_DEVICE
105 },
106 {
107 .virtual = OMAP243X_SDRC_VIRT,
108 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
109 .length = OMAP243X_SDRC_SIZE,
110 .type = MT_DEVICE
111 },
112 {
113 .virtual = OMAP243X_SMS_VIRT,
114 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
115 .length = OMAP243X_SMS_SIZE,
116 .type = MT_DEVICE
117 },
118 };
119 #endif
120 #endif
121
122 #ifdef CONFIG_ARCH_OMAP3
123 static struct map_desc omap34xx_io_desc[] __initdata = {
124 {
125 .virtual = L3_34XX_VIRT,
126 .pfn = __phys_to_pfn(L3_34XX_PHYS),
127 .length = L3_34XX_SIZE,
128 .type = MT_DEVICE
129 },
130 {
131 .virtual = L4_34XX_VIRT,
132 .pfn = __phys_to_pfn(L4_34XX_PHYS),
133 .length = L4_34XX_SIZE,
134 .type = MT_DEVICE
135 },
136 {
137 .virtual = OMAP34XX_GPMC_VIRT,
138 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
139 .length = OMAP34XX_GPMC_SIZE,
140 .type = MT_DEVICE
141 },
142 {
143 .virtual = OMAP343X_SMS_VIRT,
144 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
145 .length = OMAP343X_SMS_SIZE,
146 .type = MT_DEVICE
147 },
148 {
149 .virtual = OMAP343X_SDRC_VIRT,
150 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
151 .length = OMAP343X_SDRC_SIZE,
152 .type = MT_DEVICE
153 },
154 {
155 .virtual = L4_PER_34XX_VIRT,
156 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
157 .length = L4_PER_34XX_SIZE,
158 .type = MT_DEVICE
159 },
160 {
161 .virtual = L4_EMU_34XX_VIRT,
162 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
163 .length = L4_EMU_34XX_SIZE,
164 .type = MT_DEVICE
165 },
166 #if defined(CONFIG_DEBUG_LL) && \
167 (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3))
168 {
169 .virtual = ZOOM_UART_VIRT,
170 .pfn = __phys_to_pfn(ZOOM_UART_BASE),
171 .length = SZ_1M,
172 .type = MT_DEVICE
173 },
174 #endif
175 };
176 #endif
177
178 #ifdef CONFIG_SOC_OMAPTI816X
179 static struct map_desc omapti816x_io_desc[] __initdata = {
180 {
181 .virtual = L4_34XX_VIRT,
182 .pfn = __phys_to_pfn(L4_34XX_PHYS),
183 .length = L4_34XX_SIZE,
184 .type = MT_DEVICE
185 },
186 };
187 #endif
188
189 #ifdef CONFIG_ARCH_OMAP4
190 static struct map_desc omap44xx_io_desc[] __initdata = {
191 {
192 .virtual = L3_44XX_VIRT,
193 .pfn = __phys_to_pfn(L3_44XX_PHYS),
194 .length = L3_44XX_SIZE,
195 .type = MT_DEVICE,
196 },
197 {
198 .virtual = L4_44XX_VIRT,
199 .pfn = __phys_to_pfn(L4_44XX_PHYS),
200 .length = L4_44XX_SIZE,
201 .type = MT_DEVICE,
202 },
203 {
204 .virtual = OMAP44XX_GPMC_VIRT,
205 .pfn = __phys_to_pfn(OMAP44XX_GPMC_PHYS),
206 .length = OMAP44XX_GPMC_SIZE,
207 .type = MT_DEVICE,
208 },
209 {
210 .virtual = OMAP44XX_EMIF1_VIRT,
211 .pfn = __phys_to_pfn(OMAP44XX_EMIF1_PHYS),
212 .length = OMAP44XX_EMIF1_SIZE,
213 .type = MT_DEVICE,
214 },
215 {
216 .virtual = OMAP44XX_EMIF2_VIRT,
217 .pfn = __phys_to_pfn(OMAP44XX_EMIF2_PHYS),
218 .length = OMAP44XX_EMIF2_SIZE,
219 .type = MT_DEVICE,
220 },
221 {
222 .virtual = OMAP44XX_DMM_VIRT,
223 .pfn = __phys_to_pfn(OMAP44XX_DMM_PHYS),
224 .length = OMAP44XX_DMM_SIZE,
225 .type = MT_DEVICE,
226 },
227 {
228 .virtual = L4_PER_44XX_VIRT,
229 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
230 .length = L4_PER_44XX_SIZE,
231 .type = MT_DEVICE,
232 },
233 {
234 .virtual = L4_EMU_44XX_VIRT,
235 .pfn = __phys_to_pfn(L4_EMU_44XX_PHYS),
236 .length = L4_EMU_44XX_SIZE,
237 .type = MT_DEVICE,
238 },
239 };
240 #endif
241
242 static void __init _omap2_map_common_io(void)
243 {
244 /* Normally devicemaps_init() would flush caches and tlb after
245 * mdesc->map_io(), but we must also do it here because of the CPU
246 * revision check below.
247 */
248 local_flush_tlb_all();
249 flush_cache_all();
250
251 omap2_check_revision();
252 omap_sram_init();
253 }
254
255 #ifdef CONFIG_SOC_OMAP2420
256 void __init omap242x_map_common_io(void)
257 {
258 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
259 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
260 _omap2_map_common_io();
261 }
262 #endif
263
264 #ifdef CONFIG_SOC_OMAP2430
265 void __init omap243x_map_common_io(void)
266 {
267 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
268 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
269 _omap2_map_common_io();
270 }
271 #endif
272
273 #ifdef CONFIG_ARCH_OMAP3
274 void __init omap34xx_map_common_io(void)
275 {
276 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
277 _omap2_map_common_io();
278 }
279 #endif
280
281 #ifdef CONFIG_SOC_OMAPTI816X
282 void __init omapti816x_map_common_io(void)
283 {
284 iotable_init(omapti816x_io_desc, ARRAY_SIZE(omapti816x_io_desc));
285 _omap2_map_common_io();
286 }
287 #endif
288
289 #ifdef CONFIG_ARCH_OMAP4
290 void __init omap44xx_map_common_io(void)
291 {
292 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
293 _omap2_map_common_io();
294 }
295 #endif
296
297 /*
298 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
299 *
300 * Sets the CORE DPLL3 M2 divider to the same value that it's at
301 * currently. This has the effect of setting the SDRC SDRAM AC timing
302 * registers to the values currently defined by the kernel. Currently
303 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
304 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
305 * or passes along the return value of clk_set_rate().
306 */
307 static int __init _omap2_init_reprogram_sdrc(void)
308 {
309 struct clk *dpll3_m2_ck;
310 int v = -EINVAL;
311 long rate;
312
313 if (!cpu_is_omap34xx())
314 return 0;
315
316 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
317 if (IS_ERR(dpll3_m2_ck))
318 return -EINVAL;
319
320 rate = clk_get_rate(dpll3_m2_ck);
321 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
322 v = clk_set_rate(dpll3_m2_ck, rate);
323 if (v)
324 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
325
326 clk_put(dpll3_m2_ck);
327
328 return v;
329 }
330
331 static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
332 {
333 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
334 }
335
336 void __iomem *omap_irq_base;
337
338 /*
339 * Initialize asm_irq_base for entry-macro.S
340 */
341 static inline void omap_irq_base_init(void)
342 {
343 if (cpu_is_omap24xx())
344 omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE);
345 else if (cpu_is_omap34xx())
346 omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE);
347 else if (cpu_is_omap44xx())
348 omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE);
349 else
350 pr_err("Could not initialize omap_irq_base\n");
351 }
352
353 void __init omap2_init_common_infrastructure(void)
354 {
355 u8 postsetup_state;
356
357 if (cpu_is_omap242x()) {
358 omap2xxx_powerdomains_init();
359 omap2xxx_clockdomains_init();
360 omap2420_hwmod_init();
361 } else if (cpu_is_omap243x()) {
362 omap2xxx_powerdomains_init();
363 omap2xxx_clockdomains_init();
364 omap2430_hwmod_init();
365 } else if (cpu_is_omap34xx()) {
366 omap3xxx_powerdomains_init();
367 omap3xxx_clockdomains_init();
368 omap3xxx_hwmod_init();
369 } else if (cpu_is_omap44xx()) {
370 omap44xx_powerdomains_init();
371 omap44xx_clockdomains_init();
372 omap44xx_hwmod_init();
373 } else {
374 pr_err("Could not init hwmod data - unknown SoC\n");
375 }
376
377 /* Set the default postsetup state for all hwmods */
378 #ifdef CONFIG_PM_RUNTIME
379 postsetup_state = _HWMOD_STATE_IDLE;
380 #else
381 postsetup_state = _HWMOD_STATE_ENABLED;
382 #endif
383 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
384
385 /*
386 * Set the default postsetup state for unusual modules (like
387 * MPU WDT).
388 *
389 * The postsetup_state is not actually used until
390 * omap_hwmod_late_init(), so boards that desire full watchdog
391 * coverage of kernel initialization can reprogram the
392 * postsetup_state between the calls to
393 * omap2_init_common_infra() and omap2_init_common_devices().
394 *
395 * XXX ideally we could detect whether the MPU WDT was currently
396 * enabled here and make this conditional
397 */
398 postsetup_state = _HWMOD_STATE_DISABLED;
399 omap_hwmod_for_each_by_class("wd_timer",
400 _set_hwmod_postsetup_state,
401 &postsetup_state);
402
403 omap_pm_if_early_init();
404
405 if (cpu_is_omap2420())
406 omap2420_clk_init();
407 else if (cpu_is_omap2430())
408 omap2430_clk_init();
409 else if (cpu_is_omap34xx())
410 omap3xxx_clk_init();
411 else if (cpu_is_omap44xx())
412 omap4xxx_clk_init();
413 else
414 pr_err("Could not init clock framework - unknown SoC\n");
415 }
416
417 void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0,
418 struct omap_sdrc_params *sdrc_cs1)
419 {
420 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
421 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
422 _omap2_init_reprogram_sdrc();
423 }
424
425 omap_irq_base_init();
426 }
427
428 /*
429 * NOTE: Please use ioremap + __raw_read/write where possible instead of these
430 */
431
432 u8 omap_readb(u32 pa)
433 {
434 return __raw_readb(OMAP2_L4_IO_ADDRESS(pa));
435 }
436 EXPORT_SYMBOL(omap_readb);
437
438 u16 omap_readw(u32 pa)
439 {
440 return __raw_readw(OMAP2_L4_IO_ADDRESS(pa));
441 }
442 EXPORT_SYMBOL(omap_readw);
443
444 u32 omap_readl(u32 pa)
445 {
446 return __raw_readl(OMAP2_L4_IO_ADDRESS(pa));
447 }
448 EXPORT_SYMBOL(omap_readl);
449
450 void omap_writeb(u8 v, u32 pa)
451 {
452 __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa));
453 }
454 EXPORT_SYMBOL(omap_writeb);
455
456 void omap_writew(u16 v, u32 pa)
457 {
458 __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa));
459 }
460 EXPORT_SYMBOL(omap_writew);
461
462 void omap_writel(u32 v, u32 pa)
463 {
464 __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa));
465 }
466 EXPORT_SYMBOL(omap_writel);
linux-next