include/asm-blackfin/mach-bf548/defBF542.h

   1 /*
   2  * File:         include/asm-blackfin/mach-bf548/defBF542.h
   3  * Based on:
   4  * Author:
   5  *
   6  * Created:
   7  * Description:
   8  *
   9  * Rev:
  10  *
  11  * Modified:
  12  *
  13  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License as published by
  17  * the Free Software Foundation; either version 2, or (at your option)
  18  * any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; see the file COPYING.
  27  * If not, write to the Free Software Foundation,
  28  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  29  */
  30
  31 #ifndef _DEF_BF542_H
  32 #define _DEF_BF542_H
  33
  34 /* Include all Core registers and bit definitions */
  35 #include <asm/mach-common/def_LPBlackfin.h>
  36
  37 /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF542 */
  38
  39 /* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
  40 #include "defBF54x_base.h"
  41
  42 /* The following are the #defines needed by ADSP-BF542 that are not in the common header */
  43
  44 /* ATAPI Registers */
  45
  46 #define                    ATAPI_CONTROL  0xffc03800   /* ATAPI Control Register */
  47 #define                     ATAPI_STATUS  0xffc03804   /* ATAPI Status Register */
  48 #define                   ATAPI_DEV_ADDR  0xffc03808   /* ATAPI Device Register Address */
  49 #define                  ATAPI_DEV_TXBUF  0xffc0380c   /* ATAPI Device Register Write Data */
  50 #define                  ATAPI_DEV_RXBUF  0xffc03810   /* ATAPI Device Register Read Data */
  51 #define                   ATAPI_INT_MASK  0xffc03814   /* ATAPI Interrupt Mask Register */
  52 #define                 ATAPI_INT_STATUS  0xffc03818   /* ATAPI Interrupt Status Register */
  53 #define                   ATAPI_XFER_LEN  0xffc0381c   /* ATAPI Length of Transfer */
  54 #define                ATAPI_LINE_STATUS  0xffc03820   /* ATAPI Line Status */
  55 #define                   ATAPI_SM_STATE  0xffc03824   /* ATAPI State Machine Status */
  56 #define                  ATAPI_TERMINATE  0xffc03828   /* ATAPI Host Terminate */
  57 #define                 ATAPI_PIO_TFRCNT  0xffc0382c   /* ATAPI PIO mode transfer count */
  58 #define                 ATAPI_DMA_TFRCNT  0xffc03830   /* ATAPI DMA mode transfer count */
  59 #define               ATAPI_UMAIN_TFRCNT  0xffc03834   /* ATAPI UDMAIN transfer count */
  60 #define             ATAPI_UDMAOUT_TFRCNT  0xffc03838   /* ATAPI UDMAOUT transfer count */
  61 #define                  ATAPI_REG_TIM_0  0xffc03840   /* ATAPI Register Transfer Timing 0 */
  62 #define                  ATAPI_PIO_TIM_0  0xffc03844   /* ATAPI PIO Timing 0 Register */
  63 #define                  ATAPI_PIO_TIM_1  0xffc03848   /* ATAPI PIO Timing 1 Register */
  64 #define                ATAPI_MULTI_TIM_0  0xffc03850   /* ATAPI Multi-DMA Timing 0 Register */
  65 #define                ATAPI_MULTI_TIM_1  0xffc03854   /* ATAPI Multi-DMA Timing 1 Register */
  66 #define                ATAPI_MULTI_TIM_2  0xffc03858   /* ATAPI Multi-DMA Timing 2 Register */
  67 #define                ATAPI_ULTRA_TIM_0  0xffc03860   /* ATAPI Ultra-DMA Timing 0 Register */
  68 #define                ATAPI_ULTRA_TIM_1  0xffc03864   /* ATAPI Ultra-DMA Timing 1 Register */
  69 #define                ATAPI_ULTRA_TIM_2  0xffc03868   /* ATAPI Ultra-DMA Timing 2 Register */
  70 #define                ATAPI_ULTRA_TIM_3  0xffc0386c   /* ATAPI Ultra-DMA Timing 3 Register */
  71
  72 /* SDH Registers */
  73
  74 #define                      SDH_PWR_CTL  0xffc03900   /* SDH Power Control */
  75 #define                      SDH_CLK_CTL  0xffc03904   /* SDH Clock Control */
  76 #define                     SDH_ARGUMENT  0xffc03908   /* SDH Argument */
  77 #define                      SDH_COMMAND  0xffc0390c   /* SDH Command */
  78 #define                     SDH_RESP_CMD  0xffc03910   /* SDH Response Command */
  79 #define                    SDH_RESPONSE0  0xffc03914   /* SDH Response0 */
  80 #define                    SDH_RESPONSE1  0xffc03918   /* SDH Response1 */
  81 #define                    SDH_RESPONSE2  0xffc0391c   /* SDH Response2 */
  82 #define                    SDH_RESPONSE3  0xffc03920   /* SDH Response3 */
  83 #define                   SDH_DATA_TIMER  0xffc03924   /* SDH Data Timer */
  84 #define                    SDH_DATA_LGTH  0xffc03928   /* SDH Data Length */
  85 #define                     SDH_DATA_CTL  0xffc0392c   /* SDH Data Control */
  86 #define                     SDH_DATA_CNT  0xffc03930   /* SDH Data Counter */
  87 #define                       SDH_STATUS  0xffc03934   /* SDH Status */
  88 #define                   SDH_STATUS_CLR  0xffc03938   /* SDH Status Clear */
  89 #define                        SDH_MASK0  0xffc0393c   /* SDH Interrupt0 Mask */
  90 #define                        SDH_MASK1  0xffc03940   /* SDH Interrupt1 Mask */
  91 #define                     SDH_FIFO_CNT  0xffc03948   /* SDH FIFO Counter */
  92 #define                         SDH_FIFO  0xffc03980   /* SDH Data FIFO */
  93 #define                     SDH_E_STATUS  0xffc039c0   /* SDH Exception Status */
  94 #define                       SDH_E_MASK  0xffc039c4   /* SDH Exception Mask */
  95 #define                          SDH_CFG  0xffc039c8   /* SDH Configuration */
  96 #define                   SDH_RD_WAIT_EN  0xffc039cc   /* SDH Read Wait Enable */
  97 #define                         SDH_PID0  0xffc039d0   /* SDH Peripheral Identification0 */
  98 #define                         SDH_PID1  0xffc039d4   /* SDH Peripheral Identification1 */
  99 #define                         SDH_PID2  0xffc039d8   /* SDH Peripheral Identification2 */
 100 #define                         SDH_PID3  0xffc039dc   /* SDH Peripheral Identification3 */
 101 #define                         SDH_PID4  0xffc039e0   /* SDH Peripheral Identification4 */
 102 #define                         SDH_PID5  0xffc039e4   /* SDH Peripheral Identification5 */
 103 #define                         SDH_PID6  0xffc039e8   /* SDH Peripheral Identification6 */
 104 #define                         SDH_PID7  0xffc039ec   /* SDH Peripheral Identification7 */
 105
 106 /* USB Control Registers */
 107
 108 #define                        USB_FADDR  0xffc03c00   /* Function address register */
 109 #define                        USB_POWER  0xffc03c04   /* Power management register */
 110 #define                       USB_INTRTX  0xffc03c08   /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
 111 #define                       USB_INTRRX  0xffc03c0c   /* Interrupt register for Rx endpoints 1 to 7 */
 112 #define                      USB_INTRTXE  0xffc03c10   /* Interrupt enable register for IntrTx */
 113 #define                      USB_INTRRXE  0xffc03c14   /* Interrupt enable register for IntrRx */
 114 #define                      USB_INTRUSB  0xffc03c18   /* Interrupt register for common USB interrupts */
 115 #define                     USB_INTRUSBE  0xffc03c1c   /* Interrupt enable register for IntrUSB */
 116 #define                        USB_FRAME  0xffc03c20   /* USB frame number */
 117 #define                        USB_INDEX  0xffc03c24   /* Index register for selecting the indexed endpoint registers */
 118 #define                     USB_TESTMODE  0xffc03c28   /* Enabled USB 20 test modes */
 119 #define                     USB_GLOBINTR  0xffc03c2c   /* Global Interrupt Mask register and Wakeup Exception Interrupt */
 120 #define                   USB_GLOBAL_CTL  0xffc03c30   /* Global Clock Control for the core */
 121
 122 /* USB Packet Control Registers */
 123
 124 #define                USB_TX_MAX_PACKET  0xffc03c40   /* Maximum packet size for Host Tx endpoint */
 125 #define                         USB_CSR0  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
 126 #define                        USB_TXCSR  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
 127 #define                USB_RX_MAX_PACKET  0xffc03c48   /* Maximum packet size for Host Rx endpoint */
 128 #define                        USB_RXCSR  0xffc03c4c   /* Control Status register for Host Rx endpoint */
 129 #define                       USB_COUNT0  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
 130 #define                      USB_RXCOUNT  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
 131 #define                       USB_TXTYPE  0xffc03c54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
 132 #define                    USB_NAKLIMIT0  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
 133 #define                   USB_TXINTERVAL  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
 134 #define                       USB_RXTYPE  0xffc03c5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
 135 #define                   USB_RXINTERVAL  0xffc03c60   /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
 136 #define                      USB_TXCOUNT  0xffc03c68   /* Number of bytes to be written to the selected endpoint Tx FIFO */
 137
 138 /* USB Endpoint FIFO Registers */
 139
 140 #define                     USB_EP0_FIFO  0xffc03c80   /* Endpoint 0 FIFO */
 141 #define                     USB_EP1_FIFO  0xffc03c88   /* Endpoint 1 FIFO */
 142 #define                     USB_EP2_FIFO  0xffc03c90   /* Endpoint 2 FIFO */
 143 #define                     USB_EP3_FIFO  0xffc03c98   /* Endpoint 3 FIFO */
 144 #define                     USB_EP4_FIFO  0xffc03ca0   /* Endpoint 4 FIFO */
 145 #define                     USB_EP5_FIFO  0xffc03ca8   /* Endpoint 5 FIFO */
 146 #define                     USB_EP6_FIFO  0xffc03cb0   /* Endpoint 6 FIFO */
 147 #define                     USB_EP7_FIFO  0xffc03cb8   /* Endpoint 7 FIFO */
 148
 149 /* USB OTG Control Registers */
 150
 151 #define                  USB_OTG_DEV_CTL  0xffc03d00   /* OTG Device Control Register */
 152 #define                 USB_OTG_VBUS_IRQ  0xffc03d04   /* OTG VBUS Control Interrupts */
 153 #define                USB_OTG_VBUS_MASK  0xffc03d08   /* VBUS Control Interrupt Enable */
 154
 155 /* USB Phy Control Registers */
 156
 157 #define                     USB_LINKINFO  0xffc03d48   /* Enables programming of some PHY-side delays */
 158 #define                        USB_VPLEN  0xffc03d4c   /* Determines duration of VBUS pulse for VBUS charging */
 159 #define                      USB_HS_EOF1  0xffc03d50   /* Time buffer for High-Speed transactions */
 160 #define                      USB_FS_EOF1  0xffc03d54   /* Time buffer for Full-Speed transactions */
 161 #define                      USB_LS_EOF1  0xffc03d58   /* Time buffer for Low-Speed transactions */
 162
 163 /* (APHY_CNTRL is for ADI usage only) */
 164
 165 #define                   USB_APHY_CNTRL  0xffc03de0   /* Register that increases visibility of Analog PHY */
 166
 167 /* (APHY_CALIB is for ADI usage only) */
 168
 169 #define                   USB_APHY_CALIB  0xffc03de4   /* Register used to set some calibration values */
 170 #define                  USB_APHY_CNTRL2  0xffc03de8   /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
 171
 172 /* (PHY_TEST is for ADI usage only) */
 173
 174 #define                     USB_PHY_TEST  0xffc03dec   /* Used for reducing simulation time and simplifies FIFO testability */
 175 #define                  USB_PLLOSC_CTRL  0xffc03df0   /* Used to program different parameters for USB PLL and Oscillator */
 176 #define                   USB_SRP_CLKDIV  0xffc03df4   /* Used to program clock divide value for the clock fed to the SRP detection logic */
 177
 178 /* USB Endpoint 0 Control Registers */
 179
 180 #define                USB_EP_NI0_TXMAXP  0xffc03e00   /* Maximum packet size for Host Tx endpoint0 */
 181 #define                 USB_EP_NI0_TXCSR  0xffc03e04   /* Control Status register for endpoint 0 */
 182 #define                USB_EP_NI0_RXMAXP  0xffc03e08   /* Maximum packet size for Host Rx endpoint0 */
 183 #define                 USB_EP_NI0_RXCSR  0xffc03e0c   /* Control Status register for Host Rx endpoint0 */
 184 #define               USB_EP_NI0_RXCOUNT  0xffc03e10   /* Number of bytes received in endpoint 0 FIFO */
 185 #define                USB_EP_NI0_TXTYPE  0xffc03e14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
 186 #define            USB_EP_NI0_TXINTERVAL  0xffc03e18   /* Sets the NAK response timeout on Endpoint 0 */
 187 #define                USB_EP_NI0_RXTYPE  0xffc03e1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
 188 #define            USB_EP_NI0_RXINTERVAL  0xffc03e20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
 189
 190 /* USB Endpoint 1 Control Registers */
 191
 192 #define               USB_EP_NI0_TXCOUNT  0xffc03e28   /* Number of bytes to be written to the endpoint0 Tx FIFO */
 193 #define                USB_EP_NI1_TXMAXP  0xffc03e40   /* Maximum packet size for Host Tx endpoint1 */
 194 #define                 USB_EP_NI1_TXCSR  0xffc03e44   /* Control Status register for endpoint1 */
 195 #define                USB_EP_NI1_RXMAXP  0xffc03e48   /* Maximum packet size for Host Rx endpoint1 */
 196 #define                 USB_EP_NI1_RXCSR  0xffc03e4c   /* Control Status register for Host Rx endpoint1 */
 197 #define               USB_EP_NI1_RXCOUNT  0xffc03e50   /* Number of bytes received in endpoint1 FIFO */
 198 #define                USB_EP_NI1_TXTYPE  0xffc03e54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
 199 #define            USB_EP_NI1_TXINTERVAL  0xffc03e58   /* Sets the NAK response timeout on Endpoint1 */
 200 #define                USB_EP_NI1_RXTYPE  0xffc03e5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
 201 #define            USB_EP_NI1_RXINTERVAL  0xffc03e60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
 202
 203 /* USB Endpoint 2 Control Registers */
 204
 205 #define               USB_EP_NI1_TXCOUNT  0xffc03e68   /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
 206 #define                USB_EP_NI2_TXMAXP  0xffc03e80   /* Maximum packet size for Host Tx endpoint2 */
 207 #define                 USB_EP_NI2_TXCSR  0xffc03e84   /* Control Status register for endpoint2 */
 208 #define                USB_EP_NI2_RXMAXP  0xffc03e88   /* Maximum packet size for Host Rx endpoint2 */
 209 #define                 USB_EP_NI2_RXCSR  0xffc03e8c   /* Control Status register for Host Rx endpoint2 */
 210 #define               USB_EP_NI2_RXCOUNT  0xffc03e90   /* Number of bytes received in endpoint2 FIFO */
 211 #define                USB_EP_NI2_TXTYPE  0xffc03e94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
 212 #define            USB_EP_NI2_TXINTERVAL  0xffc03e98   /* Sets the NAK response timeout on Endpoint2 */
 213 #define                USB_EP_NI2_RXTYPE  0xffc03e9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
 214 #define            USB_EP_NI2_RXINTERVAL  0xffc03ea0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
 215
 216 /* USB Endpoint 3 Control Registers */
 217
 218 #define               USB_EP_NI2_TXCOUNT  0xffc03ea8   /* Number of bytes to be written to the endpoint2 Tx FIFO */
 219 #define                USB_EP_NI3_TXMAXP  0xffc03ec0   /* Maximum packet size for Host Tx endpoint3 */
 220 #define                 USB_EP_NI3_TXCSR  0xffc03ec4   /* Control Status register for endpoint3 */
 221 #define                USB_EP_NI3_RXMAXP  0xffc03ec8   /* Maximum packet size for Host Rx endpoint3 */
 222 #define                 USB_EP_NI3_RXCSR  0xffc03ecc   /* Control Status register for Host Rx endpoint3 */
 223 #define               USB_EP_NI3_RXCOUNT  0xffc03ed0   /* Number of bytes received in endpoint3 FIFO */
 224 #define                USB_EP_NI3_TXTYPE  0xffc03ed4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
 225 #define            USB_EP_NI3_TXINTERVAL  0xffc03ed8   /* Sets the NAK response timeout on Endpoint3 */
 226 #define                USB_EP_NI3_RXTYPE  0xffc03edc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
 227 #define            USB_EP_NI3_RXINTERVAL  0xffc03ee0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
 228
 229 /* USB Endpoint 4 Control Registers */
 230
 231 #define               USB_EP_NI3_TXCOUNT  0xffc03ee8   /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
 232 #define                USB_EP_NI4_TXMAXP  0xffc03f00   /* Maximum packet size for Host Tx endpoint4 */
 233 #define                 USB_EP_NI4_TXCSR  0xffc03f04   /* Control Status register for endpoint4 */
 234 #define                USB_EP_NI4_RXMAXP  0xffc03f08   /* Maximum packet size for Host Rx endpoint4 */
 235 #define                 USB_EP_NI4_RXCSR  0xffc03f0c   /* Control Status register for Host Rx endpoint4 */
 236 #define               USB_EP_NI4_RXCOUNT  0xffc03f10   /* Number of bytes received in endpoint4 FIFO */
 237 #define                USB_EP_NI4_TXTYPE  0xffc03f14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
 238 #define            USB_EP_NI4_TXINTERVAL  0xffc03f18   /* Sets the NAK response timeout on Endpoint4 */
 239 #define                USB_EP_NI4_RXTYPE  0xffc03f1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
 240 #define            USB_EP_NI4_RXINTERVAL  0xffc03f20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
 241
 242 /* USB Endpoint 5 Control Registers */
 243
 244 #define               USB_EP_NI4_TXCOUNT  0xffc03f28   /* Number of bytes to be written to the endpoint4 Tx FIFO */
 245 #define                USB_EP_NI5_TXMAXP  0xffc03f40   /* Maximum packet size for Host Tx endpoint5 */
 246 #define                 USB_EP_NI5_TXCSR  0xffc03f44   /* Control Status register for endpoint5 */
 247 #define                USB_EP_NI5_RXMAXP  0xffc03f48   /* Maximum packet size for Host Rx endpoint5 */
 248 #define                 USB_EP_NI5_RXCSR  0xffc03f4c   /* Control Status register for Host Rx endpoint5 */
 249 #define               USB_EP_NI5_RXCOUNT  0xffc03f50   /* Number of bytes received in endpoint5 FIFO */
 250 #define                USB_EP_NI5_TXTYPE  0xffc03f54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
 251 #define            USB_EP_NI5_TXINTERVAL  0xffc03f58   /* Sets the NAK response timeout on Endpoint5 */
 252 #define                USB_EP_NI5_RXTYPE  0xffc03f5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
 253 #define            USB_EP_NI5_RXINTERVAL  0xffc03f60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
 254
 255 /* USB Endpoint 6 Control Registers */
 256
 257 #define               USB_EP_NI5_TXCOUNT  0xffc03f68   /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
 258 #define                USB_EP_NI6_TXMAXP  0xffc03f80   /* Maximum packet size for Host Tx endpoint6 */
 259 #define                 USB_EP_NI6_TXCSR  0xffc03f84   /* Control Status register for endpoint6 */
 260 #define                USB_EP_NI6_RXMAXP  0xffc03f88   /* Maximum packet size for Host Rx endpoint6 */
 261 #define                 USB_EP_NI6_RXCSR  0xffc03f8c   /* Control Status register for Host Rx endpoint6 */
 262 #define               USB_EP_NI6_RXCOUNT  0xffc03f90   /* Number of bytes received in endpoint6 FIFO */
 263 #define                USB_EP_NI6_TXTYPE  0xffc03f94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
 264 #define            USB_EP_NI6_TXINTERVAL  0xffc03f98   /* Sets the NAK response timeout on Endpoint6 */
 265 #define                USB_EP_NI6_RXTYPE  0xffc03f9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
 266 #define            USB_EP_NI6_RXINTERVAL  0xffc03fa0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
 267
 268 /* USB Endpoint 7 Control Registers */
 269
 270 #define               USB_EP_NI6_TXCOUNT  0xffc03fa8   /* Number of bytes to be written to the endpoint6 Tx FIFO */
 271 #define                USB_EP_NI7_TXMAXP  0xffc03fc0   /* Maximum packet size for Host Tx endpoint7 */
 272 #define                 USB_EP_NI7_TXCSR  0xffc03fc4   /* Control Status register for endpoint7 */
 273 #define                USB_EP_NI7_RXMAXP  0xffc03fc8   /* Maximum packet size for Host Rx endpoint7 */
 274 #define                 USB_EP_NI7_RXCSR  0xffc03fcc   /* Control Status register for Host Rx endpoint7 */
 275 #define               USB_EP_NI7_RXCOUNT  0xffc03fd0   /* Number of bytes received in endpoint7 FIFO */
 276 #define                USB_EP_NI7_TXTYPE  0xffc03fd4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
 277 #define            USB_EP_NI7_TXINTERVAL  0xffc03fd8   /* Sets the NAK response timeout on Endpoint7 */
 278 #define                USB_EP_NI7_RXTYPE  0xffc03fdc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
 279 #define            USB_EP_NI7_RXINTERVAL  0xffc03ff0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
 280 #define               USB_EP_NI7_TXCOUNT  0xffc03ff8   /* Number of bytes to be written to the endpoint7 Tx FIFO */
 281 #define                USB_DMA_INTERRUPT  0xffc04000   /* Indicates pending interrupts for the DMA channels */
 282
 283 /* USB Channel 0 Config Registers */
 284
 285 #define                  USB_DMA0CONTROL  0xffc04004   /* DMA master channel 0 configuration */
 286 #define                  USB_DMA0ADDRLOW  0xffc04008   /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
 287 #define                 USB_DMA0ADDRHIGH  0xffc0400c   /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
 288 #define                 USB_DMA0COUNTLOW  0xffc04010   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
 289 #define                USB_DMA0COUNTHIGH  0xffc04014   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
 290
 291 /* USB Channel 1 Config Registers */
 292
 293 #define                  USB_DMA1CONTROL  0xffc04024   /* DMA master channel 1 configuration */
 294 #define                  USB_DMA1ADDRLOW  0xffc04028   /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
 295 #define                 USB_DMA1ADDRHIGH  0xffc0402c   /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
 296 #define                 USB_DMA1COUNTLOW  0xffc04030   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
 297 #define                USB_DMA1COUNTHIGH  0xffc04034   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
 298
 299 /* USB Channel 2 Config Registers */
 300
 301 #define                  USB_DMA2CONTROL  0xffc04044   /* DMA master channel 2 configuration */
 302 #define                  USB_DMA2ADDRLOW  0xffc04048   /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
 303 #define                 USB_DMA2ADDRHIGH  0xffc0404c   /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
 304 #define                 USB_DMA2COUNTLOW  0xffc04050   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
 305 #define                USB_DMA2COUNTHIGH  0xffc04054   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
 306
 307 /* USB Channel 3 Config Registers */
 308
 309 #define                  USB_DMA3CONTROL  0xffc04064   /* DMA master channel 3 configuration */
 310 #define                  USB_DMA3ADDRLOW  0xffc04068   /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
 311 #define                 USB_DMA3ADDRHIGH  0xffc0406c   /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
 312 #define                 USB_DMA3COUNTLOW  0xffc04070   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
 313 #define                USB_DMA3COUNTHIGH  0xffc04074   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
 314
 315 /* USB Channel 4 Config Registers */
 316
 317 #define                  USB_DMA4CONTROL  0xffc04084   /* DMA master channel 4 configuration */
 318 #define                  USB_DMA4ADDRLOW  0xffc04088   /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
 319 #define                 USB_DMA4ADDRHIGH  0xffc0408c   /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
 320 #define                 USB_DMA4COUNTLOW  0xffc04090   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
 321 #define                USB_DMA4COUNTHIGH  0xffc04094   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
 322
 323 /* USB Channel 5 Config Registers */
 324
 325 #define                  USB_DMA5CONTROL  0xffc040a4   /* DMA master channel 5 configuration */
 326 #define                  USB_DMA5ADDRLOW  0xffc040a8   /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
 327 #define                 USB_DMA5ADDRHIGH  0xffc040ac   /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
 328 #define                 USB_DMA5COUNTLOW  0xffc040b0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
 329 #define                USB_DMA5COUNTHIGH  0xffc040b4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
 330
 331 /* USB Channel 6 Config Registers */
 332
 333 #define                  USB_DMA6CONTROL  0xffc040c4   /* DMA master channel 6 configuration */
 334 #define                  USB_DMA6ADDRLOW  0xffc040c8   /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
 335 #define                 USB_DMA6ADDRHIGH  0xffc040cc   /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
 336 #define                 USB_DMA6COUNTLOW  0xffc040d0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
 337 #define                USB_DMA6COUNTHIGH  0xffc040d4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
 338
 339 /* USB Channel 7 Config Registers */
 340
 341 #define                  USB_DMA7CONTROL  0xffc040e4   /* DMA master channel 7 configuration */
 342 #define                  USB_DMA7ADDRLOW  0xffc040e8   /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
 343 #define                 USB_DMA7ADDRHIGH  0xffc040ec   /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
 344 #define                 USB_DMA7COUNTLOW  0xffc040f0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
 345 #define                USB_DMA7COUNTHIGH  0xffc040f4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
 346
 347 /* Keypad Registers */
 348
 349 #define                         KPAD_CTL  0xffc04100   /* Controls keypad module enable and disable */
 350 #define                    KPAD_PRESCALE  0xffc04104   /* Establish a time base for programing the KPAD_MSEL register */
 351 #define                        KPAD_MSEL  0xffc04108   /* Selects delay parameters for keypad interface sensitivity */
 352 #define                      KPAD_ROWCOL  0xffc0410c   /* Captures the row and column output values of the keys pressed */
 353 #define                        KPAD_STAT  0xffc04110   /* Holds and clears the status of the keypad interface interrupt */
 354 #define                    KPAD_SOFTEVAL  0xffc04114   /* Lets software force keypad interface to check for keys being pressed */
 355
 356
 357 /* ********************************************************** */
 358 /*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
 359 /*     and MULTI BIT READ MACROS                              */
 360 /* ********************************************************** */
 361
 362 /* Bit masks for KPAD_CTL */
 363
 364 #define                   KPAD_EN  0x1        /* Keypad Enable */
 365 #define              KPAD_IRQMODE  0x6        /* Key Press Interrupt Enable */
 366 #define                KPAD_ROWEN  0x1c00     /* Row Enable Width */
 367 #define                KPAD_COLEN  0xe000     /* Column Enable Width */
 368
 369 /* Bit masks for KPAD_PRESCALE */
 370
 371 #define         KPAD_PRESCALE_VAL  0x3f       /* Key Prescale Value */
 372
 373 /* Bit masks for KPAD_MSEL */
 374
 375 #define                DBON_SCALE  0xff       /* Debounce Scale Value */
 376 #define              COLDRV_SCALE  0xff00     /* Column Driver Scale Value */
 377
 378 /* Bit masks for KPAD_ROWCOL */
 379
 380 #define                  KPAD_ROW  0xff       /* Rows Pressed */
 381 #define                  KPAD_COL  0xff00     /* Columns Pressed */
 382
 383 /* Bit masks for KPAD_STAT */
 384
 385 #define                  KPAD_IRQ  0x1        /* Keypad Interrupt Status */
 386 #define              KPAD_MROWCOL  0x6        /* Multiple Row/Column Keypress Status */
 387 #define              KPAD_PRESSED  0x8        /* Key press current status */
 388
 389 /* Bit masks for KPAD_SOFTEVAL */
 390
 391 #define           KPAD_SOFTEVAL_E  0x2        /* Software Programmable Force Evaluate */
 392
 393 /* Bit masks for SDH_COMMAND */
 394
 395 #define                   CMD_IDX  0x3f       /* Command Index */
 396 #define                   CMD_RSP  0x40       /* Response */
 397 #define                 CMD_L_RSP  0x80       /* Long Response */
 398 #define                 CMD_INT_E  0x100      /* Command Interrupt */
 399 #define                CMD_PEND_E  0x200      /* Command Pending */
 400 #define                     CMD_E  0x400      /* Command Enable */
 401
 402 /* Bit masks for SDH_PWR_CTL */
 403
 404 #define                    PWR_ON  0x3        /* Power On */
 405 #if 0
 406 #define                       TBD  0x3c       /* TBD */
 407 #endif
 408 #define                 SD_CMD_OD  0x40       /* Open Drain Output */
 409 #define                   ROD_CTL  0x80       /* Rod Control */
 410
 411 /* Bit masks for SDH_CLK_CTL */
 412
 413 #define                    CLKDIV  0xff       /* MC_CLK Divisor */
 414 #define                     CLK_E  0x100      /* MC_CLK Bus Clock Enable */
 415 #define                  PWR_SV_E  0x200      /* Power Save Enable */
 416 #define             CLKDIV_BYPASS  0x400      /* Bypass Divisor */
 417 #define                  WIDE_BUS  0x800      /* Wide Bus Mode Enable */
 418
 419 /* Bit masks for SDH_RESP_CMD */
 420
 421 #define                  RESP_CMD  0x3f       /* Response Command */
 422
 423 /* Bit masks for SDH_DATA_CTL */
 424
 425 #define                     DTX_E  0x1        /* Data Transfer Enable */
 426 #define                   DTX_DIR  0x2        /* Data Transfer Direction */
 427 #define                  DTX_MODE  0x4        /* Data Transfer Mode */
 428 #define                 DTX_DMA_E  0x8        /* Data Transfer DMA Enable */
 429 #define              DTX_BLK_LGTH  0xf0       /* Data Transfer Block Length */
 430
 431 /* Bit masks for SDH_STATUS */
 432
 433 #define              CMD_CRC_FAIL  0x1        /* CMD CRC Fail */
 434 #define              DAT_CRC_FAIL  0x2        /* Data CRC Fail */
 435 #define               CMD_TIME_OUT  0x4        /* CMD Time Out */
 436 #define               DAT_TIME_OUT  0x8        /* Data Time Out */
 437 #define               TX_UNDERRUN  0x10       /* Transmit Underrun */
 438 #define                RX_OVERRUN  0x20       /* Receive Overrun */
 439 #define              CMD_RESP_END  0x40       /* CMD Response End */
 440 #define                  CMD_SENT  0x80       /* CMD Sent */
 441 #define                   DAT_END  0x100      /* Data End */
 442 #define             START_BIT_ERR  0x200      /* Start Bit Error */
 443 #define               DAT_BLK_END  0x400      /* Data Block End */
 444 #define                   CMD_ACT  0x800      /* CMD Active */
 445 #define                    TX_ACT  0x1000     /* Transmit Active */
 446 #define                    RX_ACT  0x2000     /* Receive Active */
 447 #define              TX_FIFO_STAT  0x4000     /* Transmit FIFO Status */
 448 #define              RX_FIFO_STAT  0x8000     /* Receive FIFO Status */
 449 #define              TX_FIFO_FULL  0x10000    /* Transmit FIFO Full */
 450 #define              RX_FIFO_FULL  0x20000    /* Receive FIFO Full */
 451 #define              TX_FIFO_ZERO  0x40000    /* Transmit FIFO Empty */
 452 #define               RX_DAT_ZERO  0x80000    /* Receive FIFO Empty */
 453 #define                TX_DAT_RDY  0x100000   /* Transmit Data Available */
 454 #define               RX_FIFO_RDY  0x200000   /* Receive Data Available */
 455
 456 /* Bit masks for SDH_STATUS_CLR */
 457
 458 #define         CMD_CRC_FAIL_STAT  0x1        /* CMD CRC Fail Status */
 459 #define         DAT_CRC_FAIL_STAT  0x2        /* Data CRC Fail Status */
 460 #define          CMD_TIMEOUT_STAT  0x4        /* CMD Time Out Status */
 461 #define          DAT_TIMEOUT_STAT  0x8        /* Data Time Out status */
 462 #define          TX_UNDERRUN_STAT  0x10       /* Transmit Underrun Status */
 463 #define           RX_OVERRUN_STAT  0x20       /* Receive Overrun Status */
 464 #define         CMD_RESP_END_STAT  0x40       /* CMD Response End Status */
 465 #define             CMD_SENT_STAT  0x80       /* CMD Sent Status */
 466 #define              DAT_END_STAT  0x100      /* Data End Status */
 467 #define        START_BIT_ERR_STAT  0x200      /* Start Bit Error Status */
 468 #define          DAT_BLK_END_STAT  0x400      /* Data Block End Status */
 469
 470 /* Bit masks for SDH_MASK0 */
 471
 472 #define         CMD_CRC_FAIL_MASK  0x1        /* CMD CRC Fail Mask */
 473 #define         DAT_CRC_FAIL_MASK  0x2        /* Data CRC Fail Mask */
 474 #define          CMD_TIMEOUT_MASK  0x4        /* CMD Time Out Mask */
 475 #define          DAT_TIMEOUT_MASK  0x8        /* Data Time Out Mask */
 476 #define          TX_UNDERRUN_MASK  0x10       /* Transmit Underrun Mask */
 477 #define           RX_OVERRUN_MASK  0x20       /* Receive Overrun Mask */
 478 #define         CMD_RESP_END_MASK  0x40       /* CMD Response End Mask */
 479 #define             CMD_SENT_MASK  0x80       /* CMD Sent Mask */
 480 #define              DAT_END_MASK  0x100      /* Data End Mask */
 481 #define        START_BIT_ERR_MASK  0x200      /* Start Bit Error Mask */
 482 #define          DAT_BLK_END_MASK  0x400      /* Data Block End Mask */
 483 #define              CMD_ACT_MASK  0x800      /* CMD Active Mask */
 484 #define               TX_ACT_MASK  0x1000     /* Transmit Active Mask */
 485 #define               RX_ACT_MASK  0x2000     /* Receive Active Mask */
 486 #define         TX_FIFO_STAT_MASK  0x4000     /* Transmit FIFO Status Mask */
 487 #define         RX_FIFO_STAT_MASK  0x8000     /* Receive FIFO Status Mask */
 488 #define         TX_FIFO_FULL_MASK  0x10000    /* Transmit FIFO Full Mask */
 489 #define         RX_FIFO_FULL_MASK  0x20000    /* Receive FIFO Full Mask */
 490 #define         TX_FIFO_ZERO_MASK  0x40000    /* Transmit FIFO Empty Mask */
 491 #define          RX_DAT_ZERO_MASK  0x80000    /* Receive FIFO Empty Mask */
 492 #define           TX_DAT_RDY_MASK  0x100000   /* Transmit Data Available Mask */
 493 #define          RX_FIFO_RDY_MASK  0x200000   /* Receive Data Available Mask */
 494
 495 /* Bit masks for SDH_FIFO_CNT */
 496
 497 #define                FIFO_COUNT  0x7fff     /* FIFO Count */
 498
 499 /* Bit masks for SDH_E_STATUS */
 500
 501 #define              SDIO_INT_DET  0x2        /* SDIO Int Detected */
 502 #define               SD_CARD_DET  0x10       /* SD Card Detect */
 503
 504 /* Bit masks for SDH_E_MASK */
 505
 506 #define                  SDIO_MSK  0x2        /* Mask SDIO Int Detected */
 507 #define                   SCD_MSK  0x40       /* Mask Card Detect */
 508
 509 /* Bit masks for SDH_CFG */
 510
 511 #define                   CLKS_EN  0x1        /* Clocks Enable */
 512 #define                      SD4E  0x4        /* SDIO 4-Bit Enable */
 513 #define                       MWE  0x8        /* Moving Window Enable */
 514 #define                    SD_RST  0x10       /* SDMMC Reset */
 515 #define                 PUP_SDDAT  0x20       /* Pull-up SD_DAT */
 516 #define                PUP_SDDAT3  0x40       /* Pull-up SD_DAT3 */
 517 #define                 PD_SDDAT3  0x80       /* Pull-down SD_DAT3 */
 518
 519 /* Bit masks for SDH_RD_WAIT_EN */
 520
 521 #define                       RWR  0x1        /* Read Wait Request */
 522
 523 /* Bit masks for ATAPI_CONTROL */
 524
 525 #define                 PIO_START  0x1        /* Start PIO/Reg Op */
 526 #define               MULTI_START  0x2        /* Start Multi-DMA Op */
 527 #define               ULTRA_START  0x4        /* Start Ultra-DMA Op */
 528 #define                  XFER_DIR  0x8        /* Transfer Direction */
 529 #define                  IORDY_EN  0x10       /* IORDY Enable */
 530 #define                FIFO_FLUSH  0x20       /* Flush FIFOs */
 531 #define                  SOFT_RST  0x40       /* Soft Reset */
 532 #define                   DEV_RST  0x80       /* Device Reset */
 533 #define                TFRCNT_RST  0x100      /* Trans Count Reset */
 534 #define               END_ON_TERM  0x200      /* End/Terminate Select */
 535 #define               PIO_USE_DMA  0x400      /* PIO-DMA Enable */
 536 #define          UDMAIN_FIFO_THRS  0xf000     /* Ultra DMA-IN FIFO Threshold */
 537
 538 /* Bit masks for ATAPI_STATUS */
 539
 540 #define               PIO_XFER_ON  0x1        /* PIO transfer in progress */
 541 #define             MULTI_XFER_ON  0x2        /* Multi-word DMA transfer in progress */
 542 #define             ULTRA_XFER_ON  0x4        /* Ultra DMA transfer in progress */
 543 #define               ULTRA_IN_FL  0xf0       /* Ultra DMA Input FIFO Level */
 544
 545 /* Bit masks for ATAPI_DEV_ADDR */
 546
 547 #define                  DEV_ADDR  0x1f       /* Device Address */
 548
 549 /* Bit masks for ATAPI_INT_MASK */
 550
 551 #define        ATAPI_DEV_INT_MASK  0x1        /* Device interrupt mask */
 552 #define             PIO_DONE_MASK  0x2        /* PIO transfer done interrupt mask */
 553 #define           MULTI_DONE_MASK  0x4        /* Multi-DMA transfer done interrupt mask */
 554 #define          UDMAIN_DONE_MASK  0x8        /* Ultra-DMA in transfer done interrupt mask */
 555 #define         UDMAOUT_DONE_MASK  0x10       /* Ultra-DMA out transfer done interrupt mask */
 556 #define       HOST_TERM_XFER_MASK  0x20       /* Host terminate current transfer interrupt mask */
 557 #define           MULTI_TERM_MASK  0x40       /* Device terminate Multi-DMA transfer interrupt mask */
 558 #define          UDMAIN_TERM_MASK  0x80       /* Device terminate Ultra-DMA-in transfer interrupt mask */
 559 #define         UDMAOUT_TERM_MASK  0x100      /* Device terminate Ultra-DMA-out transfer interrupt mask */
 560
 561 /* Bit masks for ATAPI_INT_STATUS */
 562
 563 #define             ATAPI_DEV_INT  0x1        /* Device interrupt status */
 564 #define              PIO_DONE_INT  0x2        /* PIO transfer done interrupt status */
 565 #define            MULTI_DONE_INT  0x4        /* Multi-DMA transfer done interrupt status */
 566 #define           UDMAIN_DONE_INT  0x8        /* Ultra-DMA in transfer done interrupt status */
 567 #define          UDMAOUT_DONE_INT  0x10       /* Ultra-DMA out transfer done interrupt status */
 568 #define        HOST_TERM_XFER_INT  0x20       /* Host terminate current transfer interrupt status */
 569 #define            MULTI_TERM_INT  0x40       /* Device terminate Multi-DMA transfer interrupt status */
 570 #define           UDMAIN_TERM_INT  0x80       /* Device terminate Ultra-DMA-in transfer interrupt status */
 571 #define          UDMAOUT_TERM_INT  0x100      /* Device terminate Ultra-DMA-out transfer interrupt status */
 572
 573 /* Bit masks for ATAPI_LINE_STATUS */
 574
 575 #define                ATAPI_INTR  0x1        /* Device interrupt to host line status */
 576 #define                ATAPI_DASP  0x2        /* Device dasp to host line status */
 577 #define                ATAPI_CS0N  0x4        /* ATAPI chip select 0 line status */
 578 #define                ATAPI_CS1N  0x8        /* ATAPI chip select 1 line status */
 579 #define                ATAPI_ADDR  0x70       /* ATAPI address line status */
 580 #define              ATAPI_DMAREQ  0x80       /* ATAPI DMA request line status */
 581 #define             ATAPI_DMAACKN  0x100      /* ATAPI DMA acknowledge line status */
 582 #define               ATAPI_DIOWN  0x200      /* ATAPI write line status */
 583 #define               ATAPI_DIORN  0x400      /* ATAPI read line status */
 584 #define               ATAPI_IORDY  0x800      /* ATAPI IORDY line status */
 585
 586 /* Bit masks for ATAPI_SM_STATE */
 587
 588 #define                PIO_CSTATE  0xf        /* PIO mode state machine current state */
 589 #define                DMA_CSTATE  0xf0       /* DMA mode state machine current state */
 590 #define             UDMAIN_CSTATE  0xf00      /* Ultra DMA-In mode state machine current state */
 591 #define            UDMAOUT_CSTATE  0xf000     /* ATAPI IORDY line status */
 592
 593 /* Bit masks for ATAPI_TERMINATE */
 594
 595 #define           ATAPI_HOST_TERM  0x1        /* Host terminationation */
 596
 597 /* Bit masks for ATAPI_REG_TIM_0 */
 598
 599 #define                    T2_REG  0xff       /* End of cycle time for register access transfers */
 600 #define                  TEOC_REG  0xff00     /* Selects DIOR/DIOW pulsewidth */
 601
 602 /* Bit masks for ATAPI_PIO_TIM_0 */
 603
 604 #define                    T1_REG  0xf        /* Time from address valid to DIOR/DIOW */
 605 #define                T2_REG_PIO  0xff0      /* DIOR/DIOW pulsewidth */
 606 #define                    T4_REG  0xf000     /* DIOW data hold */
 607
 608 /* Bit masks for ATAPI_PIO_TIM_1 */
 609
 610 #define              TEOC_REG_PIO  0xff       /* End of cycle time for PIO access transfers. */
 611
 612 /* Bit masks for ATAPI_MULTI_TIM_0 */
 613
 614 #define                        TD  0xff       /* DIOR/DIOW asserted pulsewidth */
 615 #define                        TM  0xff00     /* Time from address valid to DIOR/DIOW */
 616
 617 /* Bit masks for ATAPI_MULTI_TIM_1 */
 618
 619 #define                       TKW  0xff       /* Selects DIOW negated pulsewidth */
 620 #define                       TKR  0xff00     /* Selects DIOR negated pulsewidth */
 621
 622 /* Bit masks for ATAPI_MULTI_TIM_2 */
 623
 624 #define                        TH  0xff       /* Selects DIOW data hold */
 625 #define                      TEOC  0xff00     /* Selects end of cycle for DMA */
 626
 627 /* Bit masks for ATAPI_ULTRA_TIM_0 */
 628
 629 #define                      TACK  0xff       /* Selects setup and hold times for TACK */
 630 #define                      TENV  0xff00     /* Selects envelope time */
 631
 632 /* Bit masks for ATAPI_ULTRA_TIM_1 */
 633
 634 #define                      TDVS  0xff       /* Selects data valid setup time */
 635 #define                 TCYC_TDVS  0xff00     /* Selects cycle time - TDVS time */
 636
 637 /* Bit masks for ATAPI_ULTRA_TIM_2 */
 638
 639 #define                       TSS  0xff       /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
 640 #define                      TMLI  0xff00     /* Selects interlock time */
 641
 642 /* Bit masks for ATAPI_ULTRA_TIM_3 */
 643
 644 #define                      TZAH  0xff       /* Selects minimum delay required for output */
 645 #define               READY_PAUSE  0xff00     /* Selects ready to pause */
 646
 647 /* Bit masks for USB_FADDR */
 648
 649 #define          FUNCTION_ADDRESS  0x7f       /* Function address */
 650
 651 /* Bit masks for USB_POWER */
 652
 653 #define           ENABLE_SUSPENDM  0x1        /* enable SuspendM output */
 654 #define              SUSPEND_MODE  0x2        /* Suspend Mode indicator */
 655 #define               RESUME_MODE  0x4        /* DMA Mode */
 656 #define                     RESET  0x8        /* Reset indicator */
 657 #define                   HS_MODE  0x10       /* High Speed mode indicator */
 658 #define                 HS_ENABLE  0x20       /* high Speed Enable */
 659 #define                 SOFT_CONN  0x40       /* Soft connect */
 660 #define                ISO_UPDATE  0x80       /* Isochronous update */
 661
 662 /* Bit masks for USB_INTRTX */
 663
 664 #define                    EP0_TX  0x1        /* Tx Endpoint 0 interrupt */
 665 #define                    EP1_TX  0x2        /* Tx Endpoint 1 interrupt */
 666 #define                    EP2_TX  0x4        /* Tx Endpoint 2 interrupt */
 667 #define                    EP3_TX  0x8        /* Tx Endpoint 3 interrupt */
 668 #define                    EP4_TX  0x10       /* Tx Endpoint 4 interrupt */
 669 #define                    EP5_TX  0x20       /* Tx Endpoint 5 interrupt */
 670 #define                    EP6_TX  0x40       /* Tx Endpoint 6 interrupt */
 671 #define                    EP7_TX  0x80       /* Tx Endpoint 7 interrupt */
 672
 673 /* Bit masks for USB_INTRRX */
 674
 675 #define                    EP1_RX  0x2        /* Rx Endpoint 1 interrupt */
 676 #define                    EP2_RX  0x4        /* Rx Endpoint 2 interrupt */
 677 #define                    EP3_RX  0x8        /* Rx Endpoint 3 interrupt */
 678 #define                    EP4_RX  0x10       /* Rx Endpoint 4 interrupt */
 679 #define                    EP5_RX  0x20       /* Rx Endpoint 5 interrupt */
 680 #define                    EP6_RX  0x40       /* Rx Endpoint 6 interrupt */
 681 #define                    EP7_RX  0x80       /* Rx Endpoint 7 interrupt */
 682
 683 /* Bit masks for USB_INTRTXE */
 684
 685 #define                  EP0_TX_E  0x1        /* Endpoint 0 interrupt Enable */
 686 #define                  EP1_TX_E  0x2        /* Tx Endpoint 1 interrupt  Enable */
 687 #define                  EP2_TX_E  0x4        /* Tx Endpoint 2 interrupt  Enable */
 688 #define                  EP3_TX_E  0x8        /* Tx Endpoint 3 interrupt  Enable */
 689 #define                  EP4_TX_E  0x10       /* Tx Endpoint 4 interrupt  Enable */
 690 #define                  EP5_TX_E  0x20       /* Tx Endpoint 5 interrupt  Enable */
 691 #define                  EP6_TX_E  0x40       /* Tx Endpoint 6 interrupt  Enable */
 692 #define                  EP7_TX_E  0x80       /* Tx Endpoint 7 interrupt  Enable */
 693
 694 /* Bit masks for USB_INTRRXE */
 695
 696 #define                  EP1_RX_E  0x2        /* Rx Endpoint 1 interrupt  Enable */
 697 #define                  EP2_RX_E  0x4        /* Rx Endpoint 2 interrupt  Enable */
 698 #define                  EP3_RX_E  0x8        /* Rx Endpoint 3 interrupt  Enable */
 699 #define                  EP4_RX_E  0x10       /* Rx Endpoint 4 interrupt  Enable */
 700 #define                  EP5_RX_E  0x20       /* Rx Endpoint 5 interrupt  Enable */
 701 #define                  EP6_RX_E  0x40       /* Rx Endpoint 6 interrupt  Enable */
 702 #define                  EP7_RX_E  0x80       /* Rx Endpoint 7 interrupt  Enable */
 703
 704 /* Bit masks for USB_INTRUSB */
 705
 706 #define                 SUSPEND_B  0x1        /* Suspend indicator */
 707 #define                  RESUME_B  0x2        /* Resume indicator */
 708 #define          RESET_OR_BABLE_B  0x4        /* Reset/babble indicator */
 709 #define                     SOF_B  0x8        /* Start of frame */
 710 #define                    CONN_B  0x10       /* Connection indicator */
 711 #define                  DISCON_B  0x20       /* Disconnect indicator */
 712 #define             SESSION_REQ_B  0x40       /* Session Request */
 713 #define              VBUS_ERROR_B  0x80       /* Vbus threshold indicator */
 714
 715 /* Bit masks for USB_INTRUSBE */
 716
 717 #define                SUSPEND_BE  0x1        /* Suspend indicator int enable */
 718 #define                 RESUME_BE  0x2        /* Resume indicator int enable */
 719 #define         RESET_OR_BABLE_BE  0x4        /* Reset/babble indicator int enable */
 720 #define                    SOF_BE  0x8        /* Start of frame int enable */
 721 #define                   CONN_BE  0x10       /* Connection indicator int enable */
 722 #define                 DISCON_BE  0x20       /* Disconnect indicator int enable */
 723 #define            SESSION_REQ_BE  0x40       /* Session Request int enable */
 724 #define             VBUS_ERROR_BE  0x80       /* Vbus threshold indicator int enable */
 725
 726 /* Bit masks for USB_FRAME */
 727
 728 #define              FRAME_NUMBER  0x7ff      /* Frame number */
 729
 730 /* Bit masks for USB_INDEX */
 731
 732 #define         SELECTED_ENDPOINT  0xf        /* selected endpoint */
 733
 734 /* Bit masks for USB_GLOBAL_CTL */
 735
 736 #define                GLOBAL_ENA  0x1        /* enables USB module */
 737 #define                EP1_TX_ENA  0x2        /* Transmit endpoint 1 enable */
 738 #define                EP2_TX_ENA  0x4        /* Transmit endpoint 2 enable */
 739 #define                EP3_TX_ENA  0x8        /* Transmit endpoint 3 enable */
 740 #define                EP4_TX_ENA  0x10       /* Transmit endpoint 4 enable */
 741 #define                EP5_TX_ENA  0x20       /* Transmit endpoint 5 enable */
 742 #define                EP6_TX_ENA  0x40       /* Transmit endpoint 6 enable */
 743 #define                EP7_TX_ENA  0x80       /* Transmit endpoint 7 enable */
 744 #define                EP1_RX_ENA  0x100      /* Receive endpoint 1 enable */
 745 #define                EP2_RX_ENA  0x200      /* Receive endpoint 2 enable */
 746 #define                EP3_RX_ENA  0x400      /* Receive endpoint 3 enable */
 747 #define                EP4_RX_ENA  0x800      /* Receive endpoint 4 enable */
 748 #define                EP5_RX_ENA  0x1000     /* Receive endpoint 5 enable */
 749 #define                EP6_RX_ENA  0x2000     /* Receive endpoint 6 enable */
 750 #define                EP7_RX_ENA  0x4000     /* Receive endpoint 7 enable */
 751
 752 /* Bit masks for USB_OTG_DEV_CTL */
 753
 754 #define                   SESSION  0x1        /* session indicator */
 755 #define                  HOST_REQ  0x2        /* Host negotiation request */
 756 #define                 HOST_MODE  0x4        /* indicates USBDRC is a host */
 757 #define                     VBUS0  0x8        /* Vbus level indicator[0] */
 758 #define                     VBUS1  0x10       /* Vbus level indicator[1] */
 759 #define                     LSDEV  0x20       /* Low-speed indicator */
 760 #define                     FSDEV  0x40       /* Full or High-speed indicator */
 761 #define                  B_DEVICE  0x80       /* A' or 'B' device indicator */
 762
 763 /* Bit masks for USB_OTG_VBUS_IRQ */
 764
 765 #define             DRIVE_VBUS_ON  0x1        /* indicator to drive VBUS control circuit */
 766 #define            DRIVE_VBUS_OFF  0x2        /* indicator to shut off charge pump */
 767 #define           CHRG_VBUS_START  0x4        /* indicator for external circuit to start charging VBUS */
 768 #define             CHRG_VBUS_END  0x8        /* indicator for external circuit to end charging VBUS */
 769 #define        DISCHRG_VBUS_START  0x10       /* indicator to start discharging VBUS */
 770 #define          DISCHRG_VBUS_END  0x20       /* indicator to stop discharging VBUS */
 771
 772 /* Bit masks for USB_OTG_VBUS_MASK */
 773
 774 #define         DRIVE_VBUS_ON_ENA  0x1        /* enable DRIVE_VBUS_ON interrupt */
 775 #define        DRIVE_VBUS_OFF_ENA  0x2        /* enable DRIVE_VBUS_OFF interrupt */
 776 #define       CHRG_VBUS_START_ENA  0x4        /* enable CHRG_VBUS_START interrupt */
 777 #define         CHRG_VBUS_END_ENA  0x8        /* enable CHRG_VBUS_END interrupt */
 778 #define    DISCHRG_VBUS_START_ENA  0x10       /* enable DISCHRG_VBUS_START interrupt */
 779 #define      DISCHRG_VBUS_END_ENA  0x20       /* enable DISCHRG_VBUS_END interrupt */
 780
 781 /* Bit masks for USB_CSR0 */
 782
 783 #define                  RXPKTRDY  0x1        /* data packet receive indicator */
 784 #define                  TXPKTRDY  0x2        /* data packet in FIFO indicator */
 785 #define                STALL_SENT  0x4        /* STALL handshake sent */
 786 #define                   DATAEND  0x8        /* Data end indicator */
 787 #define                  SETUPEND  0x10       /* Setup end */
 788 #define                 SENDSTALL  0x20       /* Send STALL handshake */
 789 #define         SERVICED_RXPKTRDY  0x40       /* used to clear the RxPktRdy bit */
 790 #define         SERVICED_SETUPEND  0x80       /* used to clear the SetupEnd bit */
 791 #define                 FLUSHFIFO  0x100      /* flush endpoint FIFO */
 792 #define          STALL_RECEIVED_H  0x4        /* STALL handshake received host mode */
 793 #define                SETUPPKT_H  0x8        /* send Setup token host mode */
 794 #define                   ERROR_H  0x10       /* timeout error indicator host mode */
 795 #define                  REQPKT_H  0x20       /* Request an IN transaction host mode */
 796 #define               STATUSPKT_H  0x40       /* Status stage transaction host mode */
 797 #define             NAK_TIMEOUT_H  0x80       /* EP0 halted after a NAK host mode */
 798
 799 /* Bit masks for USB_COUNT0 */
 800
 801 #define              EP0_RX_COUNT  0x7f       /* number of received bytes in EP0 FIFO */
 802
 803 /* Bit masks for USB_NAKLIMIT0 */
 804
 805 #define             EP0_NAK_LIMIT  0x1f       /* number of frames/micro frames after which EP0 timeouts */
 806
 807 /* Bit masks for USB_TX_MAX_PACKET */
 808
 809 #define         MAX_PACKET_SIZE_T  0x7ff      /* maximum data pay load in a frame */
 810
 811 /* Bit masks for USB_RX_MAX_PACKET */
 812
 813 #define         MAX_PACKET_SIZE_R  0x7ff      /* maximum data pay load in a frame */
 814
 815 /* Bit masks for USB_TXCSR */
 816
 817 #define                TXPKTRDY_T  0x1        /* data packet in FIFO indicator */
 818 #define          FIFO_NOT_EMPTY_T  0x2        /* FIFO not empty */
 819 #define                UNDERRUN_T  0x4        /* TxPktRdy not set  for an IN token */
 820 #define               FLUSHFIFO_T  0x8        /* flush endpoint FIFO */
 821 #define              STALL_SEND_T  0x10       /* issue a Stall handshake */
 822 #define              STALL_SENT_T  0x20       /* Stall handshake transmitted */
 823 #define        CLEAR_DATATOGGLE_T  0x40       /* clear endpoint data toggle */
 824 #define                INCOMPTX_T  0x80       /* indicates that a large packet is split */
 825 #define              DMAREQMODE_T  0x400      /* DMA mode (0 or 1) selection */
 826 #define        FORCE_DATATOGGLE_T  0x800      /* Force data toggle */
 827 #define              DMAREQ_ENA_T  0x1000     /* Enable DMA request for Tx EP */
 828 #define                     ISO_T  0x4000     /* enable Isochronous transfers */
 829 #define                 AUTOSET_T  0x8000     /* allows TxPktRdy to be set automatically */
 830 #define                  ERROR_TH  0x4        /* error condition host mode */
 831 #define         STALL_RECEIVED_TH  0x20       /* Stall handshake received host mode */
 832 #define            NAK_TIMEOUT_TH  0x80       /* NAK timeout host mode */
 833
 834 /* Bit masks for USB_TXCOUNT */
 835
 836 #define                  TX_COUNT  0x1fff     /* Number of bytes to be written to the selected endpoint Tx FIFO */
 837
 838 /* Bit masks for USB_RXCSR */
 839
 840 #define                RXPKTRDY_R  0x1        /* data packet in FIFO indicator */
 841 #define               FIFO_FULL_R  0x2        /* FIFO not empty */
 842 #define                 OVERRUN_R  0x4        /* TxPktRdy not set  for an IN token */
 843 #define               DATAERROR_R  0x8        /* Out packet cannot be loaded into Rx  FIFO */
 844 #define               FLUSHFIFO_R  0x10       /* flush endpoint FIFO */
 845 #define              STALL_SEND_R  0x20       /* issue a Stall handshake */
 846 #define              STALL_SENT_R  0x40       /* Stall handshake transmitted */
 847 #define        CLEAR_DATATOGGLE_R  0x80       /* clear endpoint data toggle */
 848 #define                INCOMPRX_R  0x100      /* indicates that a large packet is split */
 849 #define              DMAREQMODE_R  0x800      /* DMA mode (0 or 1) selection */
 850 #define                 DISNYET_R  0x1000     /* disable Nyet handshakes */
 851 #define              DMAREQ_ENA_R  0x2000     /* Enable DMA request for Tx EP */
 852 #define                     ISO_R  0x4000     /* enable Isochronous transfers */
 853 #define               AUTOCLEAR_R  0x8000     /* allows TxPktRdy to be set automatically */
 854 #define                  ERROR_RH  0x4        /* TxPktRdy not set  for an IN token host mode */
 855 #define                 REQPKT_RH  0x20       /* request an IN transaction host mode */
 856 #define         STALL_RECEIVED_RH  0x40       /* Stall handshake received host mode */
 857 #define               INCOMPRX_RH  0x100      /* indicates that a large packet is split host mode */
 858 #define             DMAREQMODE_RH  0x800      /* DMA mode (0 or 1) selection host mode */
 859 #define                AUTOREQ_RH  0x4000     /* sets ReqPkt automatically host mode */
 860
 861 /* Bit masks for USB_RXCOUNT */
 862
 863 #define                  RX_COUNT  0x1fff     /* Number of received bytes in the packet in the Rx FIFO */
 864
 865 /* Bit masks for USB_TXTYPE */
 866
 867 #define            TARGET_EP_NO_T  0xf        /* EP number */
 868 #define                PROTOCOL_T  0xc        /* transfer type */
 869
 870 /* Bit masks for USB_TXINTERVAL */
 871
 872 #define          TX_POLL_INTERVAL  0xff       /* polling interval for selected Tx EP */
 873
 874 /* Bit masks for USB_RXTYPE */
 875
 876 #define            TARGET_EP_NO_R  0xf        /* EP number */
 877 #define                PROTOCOL_R  0xc        /* transfer type */
 878
 879 /* Bit masks for USB_RXINTERVAL */
 880
 881 #define          RX_POLL_INTERVAL  0xff       /* polling interval for selected Rx EP */
 882
 883 /* Bit masks for USB_DMA_INTERRUPT */
 884
 885 #define                  DMA0_INT  0x1        /* DMA0 pending interrupt */
 886 #define                  DMA1_INT  0x2        /* DMA1 pending interrupt */
 887 #define                  DMA2_INT  0x4        /* DMA2 pending interrupt */
 888 #define                  DMA3_INT  0x8        /* DMA3 pending interrupt */
 889 #define                  DMA4_INT  0x10       /* DMA4 pending interrupt */
 890 #define                  DMA5_INT  0x20       /* DMA5 pending interrupt */
 891 #define                  DMA6_INT  0x40       /* DMA6 pending interrupt */
 892 #define                  DMA7_INT  0x80       /* DMA7 pending interrupt */
 893
 894 /* Bit masks for USB_DMAxCONTROL */
 895
 896 #define                   DMA_ENA  0x1        /* DMA enable */
 897 #define                 DIRECTION  0x2        /* direction of DMA transfer */
 898 #define                      MODE  0x4        /* DMA Bus error */
 899 #define                   INT_ENA  0x8        /* Interrupt enable */
 900 #define                     EPNUM  0xf0       /* EP number */
 901 #define                  BUSERROR  0x100      /* DMA Bus error */
 902
 903 /* Bit masks for USB_DMAxADDRHIGH */
 904
 905 #define             DMA_ADDR_HIGH  0xffff     /* Upper 16-bits of memory source/destination address for the DMA master channel */
 906
 907 /* Bit masks for USB_DMAxADDRLOW */
 908
 909 #define              DMA_ADDR_LOW  0xffff     /* Lower 16-bits of memory source/destination address for the DMA master channel */
 910
 911 /* Bit masks for USB_DMAxCOUNTHIGH */
 912
 913 #define            DMA_COUNT_HIGH  0xffff     /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
 914
 915 /* Bit masks for USB_DMAxCOUNTLOW */
 916
 917 #define             DMA_COUNT_LOW  0xffff     /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
 918
 919
 920 /* ******************************************* */
 921 /*     MULTI BIT MACRO ENUMERATIONS            */
 922 /* ******************************************* */
 923
 924
 925 #endif /* _DEF_BF542_H */