include/asm-blackfin/mach-bf548/mem_init.h

   1 /*
   2  * File:         include/asm-blackfin/mach-bf548/mem_init.h
   3  * Based on:
   4  * Author:
   5  *
   6  * Created:
   7  * Description:
   8  *
   9  * Rev:
  10  *
  11  * Modified:
  12  *               Copyright 2004-2006 Analog Devices Inc.
  13  *
  14  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License as published by
  18  * the Free Software Foundation; either version 2, or (at your option)
  19  * any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program; see the file COPYING.
  28  * If not, write to the Free Software Foundation,
  29  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  30  */
  31 #define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1)
  32
  33 #if (CONFIG_MEM_MT46V32M16_6T)
  34 #define DDR_SIZE        DEVSZ_512
  35 #define DDR_WIDTH       DEVWD_16
  36
  37 #define DDR_tRC         DDR_TRC(MIN_DDR_SCLK(60))
  38 #define DDR_tRAS        DDR_TRAS(MIN_DDR_SCLK(42))
  39 #define DDR_tRP         DDR_TRP(MIN_DDR_SCLK(15))
  40 #define DDR_tRFC        DDR_TRFC(MIN_DDR_SCLK(72))
  41 #define DDR_tREFI       DDR_TREFI(MIN_DDR_SCLK(7800))
  42
  43 #define DDR_tRCD        DDR_TRCD(MIN_DDR_SCLK(15))
  44 #define DDR_tWTR        DDR_TWTR(1)
  45 #define DDR_tMRD        DDR_TMRD(MIN_DDR_SCLK(12))
  46 #define DDR_tWR         DDR_TWR(MIN_DDR_SCLK(15))
  47 #endif
  48
  49 #if (CONFIG_MEM_MT46V32M16_5B)
  50 #define DDR_SIZE        DEVSZ_512
  51 #define DDR_WIDTH       DEVWD_16
  52
  53 #define DDR_tRC         DDR_TRC(MIN_DDR_SCLK(55))
  54 #define DDR_tRAS        DDR_TRAS(MIN_DDR_SCLK(40))
  55 #define DDR_tRP         DDR_TRP(MIN_DDR_SCLK(15))
  56 #define DDR_tRFC        DDR_TRFC(MIN_DDR_SCLK(70))
  57 #define DDR_tREFI       DDR_TREFI(MIN_DDR_SCLK(7800))
  58
  59 #define DDR_tRCD        DDR_TRCD(MIN_DDR_SCLK(15))
  60 #define DDR_tWTR        DDR_TWTR(2)
  61 #define DDR_tMRD        DDR_TMRD(MIN_DDR_SCLK(10))
  62 #define DDR_tWR         DDR_TWR(MIN_DDR_SCLK(15))
  63 #endif
  64
  65 #if (CONFIG_MEM_GENERIC_BOARD)
  66 #define DDR_SIZE        DEVSZ_512
  67 #define DDR_WIDTH       DEVWD_16
  68
  69 #define DDR_tRCD        DDR_TRCD(3)
  70 #define DDR_tWTR        DDR_TWTR(2)
  71 #define DDR_tWR         DDR_TWR(2)
  72 #define DDR_tMRD        DDR_TMRD(2)
  73 #define DDR_tRP         DDR_TRP(3)
  74 #define DDR_tRAS        DDR_TRAS(7)
  75 #define DDR_tRC         DDR_TRC(10)
  76 #define DDR_tRFC        DDR_TRFC(12)
  77 #define DDR_tREFI       DDR_TREFI(1288)
  78 #endif
  79
  80 #if (CONFIG_SCLK_HZ <= 133333333)
  81 #define DDR_CL          CL_2
  82 #elif (CONFIG_SCLK_HZ <= 166666666)
  83 #define DDR_CL          CL_2_5
  84 #else
  85 #define DDR_CL          CL_3
  86 #endif
  87
  88 #define mem_DDRCTL0     (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI)
  89 #define mem_DDRCTL1     (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \
  90                         | DDR_tMRD | DDR_tWR | DDR_tRCD)
  91 #define mem_DDRCTL2     DDR_CL
  92
  93
  94 #if defined CONFIG_CLKIN_HALF
  95 #define CLKIN_HALF       1
  96 #else
  97 #define CLKIN_HALF       0
  98 #endif
  99
 100 #if defined CONFIG_PLL_BYPASS
 101 #define PLL_BYPASS      1
 102 #else
 103 #define PLL_BYPASS       0
 104 #endif
 105
 106 /***************************************Currently Not Being Used *********************************/
 107 #define flash_EBIU_AMBCTL_WAT  ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
 108 #define flash_EBIU_AMBCTL_RAT  ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
 109 #define flash_EBIU_AMBCTL_HT   ((CONFIG_FLASH_SPEED_BHT  * 4) / (4000000000 / CONFIG_SCLK_HZ))
 110 #define flash_EBIU_AMBCTL_ST   ((CONFIG_FLASH_SPEED_BST  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
 111 #define flash_EBIU_AMBCTL_TT   ((CONFIG_FLASH_SPEED_BTT  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
 112
 113 #if (flash_EBIU_AMBCTL_TT > 3)
 114 #define flash_EBIU_AMBCTL0_TT   B0TT_4
 115 #endif
 116 #if (flash_EBIU_AMBCTL_TT == 3)
 117 #define flash_EBIU_AMBCTL0_TT   B0TT_3
 118 #endif
 119 #if (flash_EBIU_AMBCTL_TT == 2)
 120 #define flash_EBIU_AMBCTL0_TT   B0TT_2
 121 #endif
 122 #if (flash_EBIU_AMBCTL_TT < 2)
 123 #define flash_EBIU_AMBCTL0_TT   B0TT_1
 124 #endif
 125
 126 #if (flash_EBIU_AMBCTL_ST > 3)
 127 #define flash_EBIU_AMBCTL0_ST   B0ST_4
 128 #endif
 129 #if (flash_EBIU_AMBCTL_ST == 3)
 130 #define flash_EBIU_AMBCTL0_ST   B0ST_3
 131 #endif
 132 #if (flash_EBIU_AMBCTL_ST == 2)
 133 #define flash_EBIU_AMBCTL0_ST   B0ST_2
 134 #endif
 135 #if (flash_EBIU_AMBCTL_ST < 2)
 136 #define flash_EBIU_AMBCTL0_ST   B0ST_1
 137 #endif
 138
 139 #if (flash_EBIU_AMBCTL_HT > 2)
 140 #define flash_EBIU_AMBCTL0_HT   B0HT_3
 141 #endif
 142 #if (flash_EBIU_AMBCTL_HT == 2)
 143 #define flash_EBIU_AMBCTL0_HT   B0HT_2
 144 #endif
 145 #if (flash_EBIU_AMBCTL_HT == 1)
 146 #define flash_EBIU_AMBCTL0_HT   B0HT_1
 147 #endif
 148 #if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
 149 #define flash_EBIU_AMBCTL0_HT   B0HT_0
 150 #endif
 151 #if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
 152 #define flash_EBIU_AMBCTL0_HT   B0HT_1
 153 #endif
 154
 155 #if (flash_EBIU_AMBCTL_WAT > 14)
 156 #define flash_EBIU_AMBCTL0_WAT  B0WAT_15
 157 #endif
 158 #if (flash_EBIU_AMBCTL_WAT == 14)
 159 #define flash_EBIU_AMBCTL0_WAT  B0WAT_14
 160 #endif
 161 #if (flash_EBIU_AMBCTL_WAT == 13)
 162 #define flash_EBIU_AMBCTL0_WAT  B0WAT_13
 163 #endif
 164 #if (flash_EBIU_AMBCTL_WAT == 12)
 165 #define flash_EBIU_AMBCTL0_WAT  B0WAT_12
 166 #endif
 167 #if (flash_EBIU_AMBCTL_WAT == 11)
 168 #define flash_EBIU_AMBCTL0_WAT  B0WAT_11
 169 #endif
 170 #if (flash_EBIU_AMBCTL_WAT == 10)
 171 #define flash_EBIU_AMBCTL0_WAT  B0WAT_10
 172 #endif
 173 #if (flash_EBIU_AMBCTL_WAT == 9)
 174 #define flash_EBIU_AMBCTL0_WAT  B0WAT_9
 175 #endif
 176 #if (flash_EBIU_AMBCTL_WAT == 8)
 177 #define flash_EBIU_AMBCTL0_WAT  B0WAT_8
 178 #endif
 179 #if (flash_EBIU_AMBCTL_WAT == 7)
 180 #define flash_EBIU_AMBCTL0_WAT  B0WAT_7
 181 #endif
 182 #if (flash_EBIU_AMBCTL_WAT == 6)
 183 #define flash_EBIU_AMBCTL0_WAT  B0WAT_6
 184 #endif
 185 #if (flash_EBIU_AMBCTL_WAT == 5)
 186 #define flash_EBIU_AMBCTL0_WAT  B0WAT_5
 187 #endif
 188 #if (flash_EBIU_AMBCTL_WAT == 4)
 189 #define flash_EBIU_AMBCTL0_WAT  B0WAT_4
 190 #endif
 191 #if (flash_EBIU_AMBCTL_WAT == 3)
 192 #define flash_EBIU_AMBCTL0_WAT  B0WAT_3
 193 #endif
 194 #if (flash_EBIU_AMBCTL_WAT == 2)
 195 #define flash_EBIU_AMBCTL0_WAT  B0WAT_2
 196 #endif
 197 #if (flash_EBIU_AMBCTL_WAT == 1)
 198 #define flash_EBIU_AMBCTL0_WAT  B0WAT_1
 199 #endif
 200
 201 #if (flash_EBIU_AMBCTL_RAT > 14)
 202 #define flash_EBIU_AMBCTL0_RAT  B0RAT_15
 203 #endif
 204 #if (flash_EBIU_AMBCTL_RAT == 14)
 205 #define flash_EBIU_AMBCTL0_RAT  B0RAT_14
 206 #endif
 207 #if (flash_EBIU_AMBCTL_RAT == 13)
 208 #define flash_EBIU_AMBCTL0_RAT  B0RAT_13
 209 #endif
 210 #if (flash_EBIU_AMBCTL_RAT == 12)
 211 #define flash_EBIU_AMBCTL0_RAT  B0RAT_12
 212 #endif
 213 #if (flash_EBIU_AMBCTL_RAT == 11)
 214 #define flash_EBIU_AMBCTL0_RAT  B0RAT_11
 215 #endif
 216 #if (flash_EBIU_AMBCTL_RAT == 10)
 217 #define flash_EBIU_AMBCTL0_RAT  B0RAT_10
 218 #endif
 219 #if (flash_EBIU_AMBCTL_RAT == 9)
 220 #define flash_EBIU_AMBCTL0_RAT  B0RAT_9
 221 #endif
 222 #if (flash_EBIU_AMBCTL_RAT == 8)
 223 #define flash_EBIU_AMBCTL0_RAT  B0RAT_8
 224 #endif
 225 #if (flash_EBIU_AMBCTL_RAT == 7)
 226 #define flash_EBIU_AMBCTL0_RAT  B0RAT_7
 227 #endif
 228 #if (flash_EBIU_AMBCTL_RAT == 6)
 229 #define flash_EBIU_AMBCTL0_RAT  B0RAT_6
 230 #endif
 231 #if (flash_EBIU_AMBCTL_RAT == 5)
 232 #define flash_EBIU_AMBCTL0_RAT  B0RAT_5
 233 #endif
 234 #if (flash_EBIU_AMBCTL_RAT == 4)
 235 #define flash_EBIU_AMBCTL0_RAT  B0RAT_4
 236 #endif
 237 #if (flash_EBIU_AMBCTL_RAT == 3)
 238 #define flash_EBIU_AMBCTL0_RAT  B0RAT_3
 239 #endif
 240 #if (flash_EBIU_AMBCTL_RAT == 2)
 241 #define flash_EBIU_AMBCTL0_RAT  B0RAT_2
 242 #endif
 243 #if (flash_EBIU_AMBCTL_RAT == 1)
 244 #define flash_EBIU_AMBCTL0_RAT  B0RAT_1
 245 #endif
 246
 247 #define flash_EBIU_AMBCTL0  \
 248         (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
 249          flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)