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[PATCH] W1: w1_netlink: New init/fini netlink callbacks.
[linux-2.6/verdex.git] / drivers / net / pcmcia / nmclan_cs.c
blob980d7e5d66cb82b58b2bd085f35389a8b26d2d01
1 /* ----------------------------------------------------------------------------
2 Linux PCMCIA ethernet adapter driver for the New Media Ethernet LAN.
3 nmclan_cs.c,v 0.16 1995/07/01 06:42:17 rpao Exp rpao
4
5 The Ethernet LAN uses the Advanced Micro Devices (AMD) Am79C940 Media
6 Access Controller for Ethernet (MACE). It is essentially the Am2150
7 PCMCIA Ethernet card contained in the Am2150 Demo Kit.
8
9 Written by Roger C. Pao <rpao@paonet.org>
10 Copyright 1995 Roger C. Pao
11 Linux 2.5 cleanups Copyright Red Hat 2003
12
13 This software may be used and distributed according to the terms of
14 the GNU General Public License.
15
16 Ported to Linux 1.3.* network driver environment by
17 Matti Aarnio <mea@utu.fi>
18
19 References
20
21 Am2150 Technical Reference Manual, Revision 1.0, August 17, 1993
22 Am79C940 (MACE) Data Sheet, 1994
23 Am79C90 (C-LANCE) Data Sheet, 1994
24 Linux PCMCIA Programmer's Guide v1.17
25 /usr/src/linux/net/inet/dev.c, Linux kernel 1.2.8
26
27 Eric Mears, New Media Corporation
28 Tom Pollard, New Media Corporation
29 Dean Siasoyco, New Media Corporation
30 Ken Lesniak, Silicon Graphics, Inc. <lesniak@boston.sgi.com>
31 Donald Becker <becker@scyld.com>
32 David Hinds <dahinds@users.sourceforge.net>
33
34 The Linux client driver is based on the 3c589_cs.c client driver by
35 David Hinds.
36
37 The Linux network driver outline is based on the 3c589_cs.c driver,
38 the 8390.c driver, and the example skeleton.c kernel code, which are
39 by Donald Becker.
40
41 The Am2150 network driver hardware interface code is based on the
42 OS/9000 driver for the New Media Ethernet LAN by Eric Mears.
43
44 Special thanks for testing and help in debugging this driver goes
45 to Ken Lesniak.
46
47 -------------------------------------------------------------------------------
48 Driver Notes and Issues
49 -------------------------------------------------------------------------------
50
51 1. Developed on a Dell 320SLi
52 PCMCIA Card Services 2.6.2
53 Linux dell 1.2.10 #1 Thu Jun 29 20:23:41 PDT 1995 i386
54
55 2. rc.pcmcia may require loading pcmcia_core with io_speed=300:
56 'insmod pcmcia_core.o io_speed=300'.
57 This will avoid problems with fast systems which causes rx_framecnt
58 to return random values.
59
60 3. If hot extraction does not work for you, use 'ifconfig eth0 down'
61 before extraction.
62
63 4. There is a bad slow-down problem in this driver.
64
65 5. Future: Multicast processing. In the meantime, do _not_ compile your
66 kernel with multicast ip enabled.
67
68 -------------------------------------------------------------------------------
69 History
70 -------------------------------------------------------------------------------
71 Log: nmclan_cs.c,v
72 * 2.5.75-ac1 2003/07/11 Alan Cox <alan@redhat.com>
73 * Fixed hang on card eject as we probe it
74 * Cleaned up to use new style locking.
75 *
76 * Revision 0.16 1995/07/01 06:42:17 rpao
77 * Bug fix: nmclan_reset() called CardServices incorrectly.
78 *
79 * Revision 0.15 1995/05/24 08:09:47 rpao
80 * Re-implement MULTI_TX dev->tbusy handling.
81 *
82 * Revision 0.14 1995/05/23 03:19:30 rpao
83 * Added, in nmclan_config(), "tuple.Attributes = 0;".
84 * Modified MACE ID check to ignore chip revision level.
85 * Avoid tx_free_frames race condition between _start_xmit and _interrupt.
86 *
87 * Revision 0.13 1995/05/18 05:56:34 rpao
88 * Statistics changes.
89 * Bug fix: nmclan_reset did not enable TX and RX: call restore_multicast_list.
90 * Bug fix: mace_interrupt checks ~MACE_IMR_DEFAULT. Fixes driver lockup.
91 *
92 * Revision 0.12 1995/05/14 00:12:23 rpao
93 * Statistics overhaul.
94 *
95
96 95/05/13 rpao V0.10a
97 Bug fix: MACE statistics counters used wrong I/O ports.
98 Bug fix: mace_interrupt() needed to allow statistics to be
99 processed without RX or TX interrupts pending.
100 95/05/11 rpao V0.10
101 Multiple transmit request processing.
102 Modified statistics to use MACE counters where possible.
103 95/05/10 rpao V0.09 Bug fix: Must use IO_DATA_PATH_WIDTH_AUTO.
104 *Released
105 95/05/10 rpao V0.08
106 Bug fix: Make all non-exported functions private by using
107 static keyword.
108 Bug fix: Test IntrCnt _before_ reading MACE_IR.
109 95/05/10 rpao V0.07 Statistics.
110 95/05/09 rpao V0.06 Fix rx_framecnt problem by addition of PCIC wait states.
111
112 ---------------------------------------------------------------------------- */
113
114 #define DRV_NAME "nmclan_cs"
115 #define DRV_VERSION "0.16"
116
117
118 /* ----------------------------------------------------------------------------
119 Conditional Compilation Options
120 ---------------------------------------------------------------------------- */
121
122 #define MULTI_TX 0
123 #define RESET_ON_TIMEOUT 1
124 #define TX_INTERRUPTABLE 1
125 #define RESET_XILINX 0
126
127 /* ----------------------------------------------------------------------------
128 Include Files
129 ---------------------------------------------------------------------------- */
130
131 #include <linux/module.h>
132 #include <linux/kernel.h>
133 #include <linux/init.h>
134 #include <linux/ptrace.h>
135 #include <linux/slab.h>
136 #include <linux/string.h>
137 #include <linux/timer.h>
138 #include <linux/interrupt.h>
139 #include <linux/in.h>
140 #include <linux/delay.h>
141 #include <linux/ethtool.h>
142 #include <linux/netdevice.h>
143 #include <linux/etherdevice.h>
144 #include <linux/skbuff.h>
145 #include <linux/if_arp.h>
146 #include <linux/ioport.h>
147 #include <linux/bitops.h>
148
149 #include <pcmcia/cs_types.h>
150 #include <pcmcia/cs.h>
151 #include <pcmcia/cisreg.h>
152 #include <pcmcia/cistpl.h>
153 #include <pcmcia/ds.h>
154
155 #include <asm/uaccess.h>
156 #include <asm/io.h>
157 #include <asm/system.h>
158
159 /* ----------------------------------------------------------------------------
160 Defines
161 ---------------------------------------------------------------------------- */
162
163 #define ETHER_ADDR_LEN ETH_ALEN
164 /* 6 bytes in an Ethernet Address */
165 #define MACE_LADRF_LEN 8
166 /* 8 bytes in Logical Address Filter */
167
168 /* Loop Control Defines */
169 #define MACE_MAX_IR_ITERATIONS 10
170 #define MACE_MAX_RX_ITERATIONS 12
171 /*
172 TBD: Dean brought this up, and I assumed the hardware would
173 handle it:
174
175 If MACE_MAX_RX_ITERATIONS is > 1, rx_framecnt may still be
176 non-zero when the isr exits. We may not get another interrupt
177 to process the remaining packets for some time.
178 */
179
180 /*
181 The Am2150 has a Xilinx XC3042 field programmable gate array (FPGA)
182 which manages the interface between the MACE and the PCMCIA bus. It
183 also includes buffer management for the 32K x 8 SRAM to control up to
184 four transmit and 12 receive frames at a time.
185 */
186 #define AM2150_MAX_TX_FRAMES 4
187 #define AM2150_MAX_RX_FRAMES 12
188
189 /* Am2150 Ethernet Card I/O Mapping */
190 #define AM2150_RCV 0x00
191 #define AM2150_XMT 0x04
192 #define AM2150_XMT_SKIP 0x09
193 #define AM2150_RCV_NEXT 0x0A
194 #define AM2150_RCV_FRAME_COUNT 0x0B
195 #define AM2150_MACE_BANK 0x0C
196 #define AM2150_MACE_BASE 0x10
197
198 /* MACE Registers */
199 #define MACE_RCVFIFO 0
200 #define MACE_XMTFIFO 1
201 #define MACE_XMTFC 2
202 #define MACE_XMTFS 3
203 #define MACE_XMTRC 4
204 #define MACE_RCVFC 5
205 #define MACE_RCVFS 6
206 #define MACE_FIFOFC 7
207 #define MACE_IR 8
208 #define MACE_IMR 9
209 #define MACE_PR 10
210 #define MACE_BIUCC 11
211 #define MACE_FIFOCC 12
212 #define MACE_MACCC 13
213 #define MACE_PLSCC 14
214 #define MACE_PHYCC 15
215 #define MACE_CHIPIDL 16
216 #define MACE_CHIPIDH 17
217 #define MACE_IAC 18
218 /* Reserved */
219 #define MACE_LADRF 20
220 #define MACE_PADR 21
221 /* Reserved */
222 /* Reserved */
223 #define MACE_MPC 24
224 /* Reserved */
225 #define MACE_RNTPC 26
226 #define MACE_RCVCC 27
227 /* Reserved */
228 #define MACE_UTR 29
229 #define MACE_RTR1 30
230 #define MACE_RTR2 31
231
232 /* MACE Bit Masks */
233 #define MACE_XMTRC_EXDEF 0x80
234 #define MACE_XMTRC_XMTRC 0x0F
235
236 #define MACE_XMTFS_XMTSV 0x80
237 #define MACE_XMTFS_UFLO 0x40
238 #define MACE_XMTFS_LCOL 0x20
239 #define MACE_XMTFS_MORE 0x10
240 #define MACE_XMTFS_ONE 0x08
241 #define MACE_XMTFS_DEFER 0x04
242 #define MACE_XMTFS_LCAR 0x02
243 #define MACE_XMTFS_RTRY 0x01
244
245 #define MACE_RCVFS_RCVSTS 0xF000
246 #define MACE_RCVFS_OFLO 0x8000
247 #define MACE_RCVFS_CLSN 0x4000
248 #define MACE_RCVFS_FRAM 0x2000
249 #define MACE_RCVFS_FCS 0x1000
250
251 #define MACE_FIFOFC_RCVFC 0xF0
252 #define MACE_FIFOFC_XMTFC 0x0F
253
254 #define MACE_IR_JAB 0x80
255 #define MACE_IR_BABL 0x40
256 #define MACE_IR_CERR 0x20
257 #define MACE_IR_RCVCCO 0x10
258 #define MACE_IR_RNTPCO 0x08
259 #define MACE_IR_MPCO 0x04
260 #define MACE_IR_RCVINT 0x02
261 #define MACE_IR_XMTINT 0x01
262
263 #define MACE_MACCC_PROM 0x80
264 #define MACE_MACCC_DXMT2PD 0x40
265 #define MACE_MACCC_EMBA 0x20
266 #define MACE_MACCC_RESERVED 0x10
267 #define MACE_MACCC_DRCVPA 0x08
268 #define MACE_MACCC_DRCVBC 0x04
269 #define MACE_MACCC_ENXMT 0x02
270 #define MACE_MACCC_ENRCV 0x01
271
272 #define MACE_PHYCC_LNKFL 0x80
273 #define MACE_PHYCC_DLNKTST 0x40
274 #define MACE_PHYCC_REVPOL 0x20
275 #define MACE_PHYCC_DAPC 0x10
276 #define MACE_PHYCC_LRT 0x08
277 #define MACE_PHYCC_ASEL 0x04
278 #define MACE_PHYCC_RWAKE 0x02
279 #define MACE_PHYCC_AWAKE 0x01
280
281 #define MACE_IAC_ADDRCHG 0x80
282 #define MACE_IAC_PHYADDR 0x04
283 #define MACE_IAC_LOGADDR 0x02
284
285 #define MACE_UTR_RTRE 0x80
286 #define MACE_UTR_RTRD 0x40
287 #define MACE_UTR_RPA 0x20
288 #define MACE_UTR_FCOLL 0x10
289 #define MACE_UTR_RCVFCSE 0x08
290 #define MACE_UTR_LOOP_INCL_MENDEC 0x06
291 #define MACE_UTR_LOOP_NO_MENDEC 0x04
292 #define MACE_UTR_LOOP_EXTERNAL 0x02
293 #define MACE_UTR_LOOP_NONE 0x00
294 #define MACE_UTR_RESERVED 0x01
295
296 /* Switch MACE register bank (only 0 and 1 are valid) */
297 #define MACEBANK(win_num) outb((win_num), ioaddr + AM2150_MACE_BANK)
298
299 #define MACE_IMR_DEFAULT \
300 (0xFF - \
301 ( \
302 MACE_IR_CERR | \
303 MACE_IR_RCVCCO | \
304 MACE_IR_RNTPCO | \
305 MACE_IR_MPCO | \
306 MACE_IR_RCVINT | \
307 MACE_IR_XMTINT \
308 ) \
309 )
310 #undef MACE_IMR_DEFAULT
311 #define MACE_IMR_DEFAULT 0x00 /* New statistics handling: grab everything */
312
313 #define TX_TIMEOUT ((400*HZ)/1000)
314
315 /* ----------------------------------------------------------------------------
316 Type Definitions
317 ---------------------------------------------------------------------------- */
318
319 typedef struct _mace_statistics {
320 /* MACE_XMTFS */
321 int xmtsv;
322 int uflo;
323 int lcol;
324 int more;
325 int one;
326 int defer;
327 int lcar;
328 int rtry;
329
330 /* MACE_XMTRC */
331 int exdef;
332 int xmtrc;
333
334 /* RFS1--Receive Status (RCVSTS) */
335 int oflo;
336 int clsn;
337 int fram;
338 int fcs;
339
340 /* RFS2--Runt Packet Count (RNTPC) */
341 int rfs_rntpc;
342
343 /* RFS3--Receive Collision Count (RCVCC) */
344 int rfs_rcvcc;
345
346 /* MACE_IR */
347 int jab;
348 int babl;
349 int cerr;
350 int rcvcco;
351 int rntpco;
352 int mpco;
353
354 /* MACE_MPC */
355 int mpc;
356
357 /* MACE_RNTPC */
358 int rntpc;
359
360 /* MACE_RCVCC */
361 int rcvcc;
362 } mace_statistics;
363
364 typedef struct _mace_private {
365 dev_link_t link;
366 dev_node_t node;
367 struct net_device_stats linux_stats; /* Linux statistics counters */
368 mace_statistics mace_stats; /* MACE chip statistics counters */
369
370 /* restore_multicast_list() state variables */
371 int multicast_ladrf[MACE_LADRF_LEN]; /* Logical address filter */
372 int multicast_num_addrs;
373
374 char tx_free_frames; /* Number of free transmit frame buffers */
375 char tx_irq_disabled; /* MACE TX interrupt disabled */
376
377 spinlock_t bank_lock; /* Must be held if you step off bank 0 */
378 } mace_private;
379
380 /* ----------------------------------------------------------------------------
381 Private Global Variables
382 ---------------------------------------------------------------------------- */
383
384 #ifdef PCMCIA_DEBUG
385 static char rcsid[] =
386 "nmclan_cs.c,v 0.16 1995/07/01 06:42:17 rpao Exp rpao";
387 static char *version =
388 DRV_NAME " " DRV_VERSION " (Roger C. Pao)";
389 #endif
390
391 static dev_info_t dev_info="nmclan_cs";
392 static dev_link_t *dev_list;
393
394 static char *if_names[]={
395 "Auto", "10baseT", "BNC",
396 };
397
398 /* ----------------------------------------------------------------------------
399 Parameters
400 These are the parameters that can be set during loading with
401 'insmod'.
402 ---------------------------------------------------------------------------- */
403
404 MODULE_DESCRIPTION("New Media PCMCIA ethernet driver");
405 MODULE_LICENSE("GPL");
406
407 #define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0)
408
409 /* 0=auto, 1=10baseT, 2 = 10base2, default=auto */
410 INT_MODULE_PARM(if_port, 0);
411
412 #ifdef PCMCIA_DEBUG
413 INT_MODULE_PARM(pc_debug, PCMCIA_DEBUG);
414 #define DEBUG(n, args...) if (pc_debug>(n)) printk(KERN_DEBUG args)
415 #else
416 #define DEBUG(n, args...)
417 #endif
418
419 /* ----------------------------------------------------------------------------
420 Function Prototypes
421 ---------------------------------------------------------------------------- */
422
423 static void nmclan_config(dev_link_t *link);
424 static void nmclan_release(dev_link_t *link);
425 static int nmclan_event(event_t event, int priority,
426 event_callback_args_t *args);
427
428 static void nmclan_reset(struct net_device *dev);
429 static int mace_config(struct net_device *dev, struct ifmap *map);
430 static int mace_open(struct net_device *dev);
431 static int mace_close(struct net_device *dev);
432 static int mace_start_xmit(struct sk_buff *skb, struct net_device *dev);
433 static void mace_tx_timeout(struct net_device *dev);
434 static irqreturn_t mace_interrupt(int irq, void *dev_id, struct pt_regs *regs);
435 static struct net_device_stats *mace_get_stats(struct net_device *dev);
436 static int mace_rx(struct net_device *dev, unsigned char RxCnt);
437 static void restore_multicast_list(struct net_device *dev);
438 static void set_multicast_list(struct net_device *dev);
439 static struct ethtool_ops netdev_ethtool_ops;
440
441
442 static dev_link_t *nmclan_attach(void);
443 static void nmclan_detach(dev_link_t *);
444
445 /* ----------------------------------------------------------------------------
446 nmclan_attach
447 Creates an "instance" of the driver, allocating local data
448 structures for one device. The device is registered with Card
449 Services.
450 ---------------------------------------------------------------------------- */
451
452 static dev_link_t *nmclan_attach(void)
453 {
454 mace_private *lp;
455 dev_link_t *link;
456 struct net_device *dev;
457 client_reg_t client_reg;
458 int ret;
459
460 DEBUG(0, "nmclan_attach()\n");
461 DEBUG(1, "%s\n", rcsid);
462
463 /* Create new ethernet device */
464 dev = alloc_etherdev(sizeof(mace_private));
465 if (!dev)
466 return NULL;
467 lp = netdev_priv(dev);
468 link = &lp->link;
469 link->priv = dev;
470
471 spin_lock_init(&lp->bank_lock);
472 link->io.NumPorts1 = 32;
473 link->io.Attributes1 = IO_DATA_PATH_WIDTH_AUTO;
474 link->io.IOAddrLines = 5;
475 link->irq.Attributes = IRQ_TYPE_EXCLUSIVE | IRQ_HANDLE_PRESENT;
476 link->irq.IRQInfo1 = IRQ_LEVEL_ID;
477 link->irq.Handler = &mace_interrupt;
478 link->irq.Instance = dev;
479 link->conf.Attributes = CONF_ENABLE_IRQ;
480 link->conf.Vcc = 50;
481 link->conf.IntType = INT_MEMORY_AND_IO;
482 link->conf.ConfigIndex = 1;
483 link->conf.Present = PRESENT_OPTION;
484
485 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
486
487 SET_MODULE_OWNER(dev);
488 dev->hard_start_xmit = &mace_start_xmit;
489 dev->set_config = &mace_config;
490 dev->get_stats = &mace_get_stats;
491 dev->set_multicast_list = &set_multicast_list;
492 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
493 dev->open = &mace_open;
494 dev->stop = &mace_close;
495 #ifdef HAVE_TX_TIMEOUT
496 dev->tx_timeout = mace_tx_timeout;
497 dev->watchdog_timeo = TX_TIMEOUT;
498 #endif
499
500 /* Register with Card Services */
501 link->next = dev_list;
502 dev_list = link;
503 client_reg.dev_info = &dev_info;
504 client_reg.Version = 0x0210;
505 client_reg.event_callback_args.client_data = link;
506 ret = pcmcia_register_client(&link->handle, &client_reg);
507 if (ret != 0) {
508 cs_error(link->handle, RegisterClient, ret);
509 nmclan_detach(link);
510 return NULL;
511 }
512
513 return link;
514 } /* nmclan_attach */
515
516 /* ----------------------------------------------------------------------------
517 nmclan_detach
518 This deletes a driver "instance". The device is de-registered
519 with Card Services. If it has been released, all local data
520 structures are freed. Otherwise, the structures will be freed
521 when the device is released.
522 ---------------------------------------------------------------------------- */
523
524 static void nmclan_detach(dev_link_t *link)
525 {
526 struct net_device *dev = link->priv;
527 dev_link_t **linkp;
528
529 DEBUG(0, "nmclan_detach(0x%p)\n", link);
530
531 /* Locate device structure */
532 for (linkp = &dev_list; *linkp; linkp = &(*linkp)->next)
533 if (*linkp == link) break;
534 if (*linkp == NULL)
535 return;
536
537 if (link->dev)
538 unregister_netdev(dev);
539
540 if (link->state & DEV_CONFIG)
541 nmclan_release(link);
542
543 if (link->handle)
544 pcmcia_deregister_client(link->handle);
545
546 /* Unlink device structure, free bits */
547 *linkp = link->next;
548 free_netdev(dev);
549 } /* nmclan_detach */
550
551 /* ----------------------------------------------------------------------------
552 mace_read
553 Reads a MACE register. This is bank independent; however, the
554 caller must ensure that this call is not interruptable. We are
555 assuming that during normal operation, the MACE is always in
556 bank 0.
557 ---------------------------------------------------------------------------- */
558 static int mace_read(mace_private *lp, kio_addr_t ioaddr, int reg)
559 {
560 int data = 0xFF;
561 unsigned long flags;
562
563 switch (reg >> 4) {
564 case 0: /* register 0-15 */
565 data = inb(ioaddr + AM2150_MACE_BASE + reg);
566 break;
567 case 1: /* register 16-31 */
568 spin_lock_irqsave(&lp->bank_lock, flags);
569 MACEBANK(1);
570 data = inb(ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
571 MACEBANK(0);
572 spin_unlock_irqrestore(&lp->bank_lock, flags);
573 break;
574 }
575 return (data & 0xFF);
576 } /* mace_read */
577
578 /* ----------------------------------------------------------------------------
579 mace_write
580 Writes to a MACE register. This is bank independent; however,
581 the caller must ensure that this call is not interruptable. We
582 are assuming that during normal operation, the MACE is always in
583 bank 0.
584 ---------------------------------------------------------------------------- */
585 static void mace_write(mace_private *lp, kio_addr_t ioaddr, int reg, int data)
586 {
587 unsigned long flags;
588
589 switch (reg >> 4) {
590 case 0: /* register 0-15 */
591 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + reg);
592 break;
593 case 1: /* register 16-31 */
594 spin_lock_irqsave(&lp->bank_lock, flags);
595 MACEBANK(1);
596 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
597 MACEBANK(0);
598 spin_unlock_irqrestore(&lp->bank_lock, flags);
599 break;
600 }
601 } /* mace_write */
602
603 /* ----------------------------------------------------------------------------
604 mace_init
605 Resets the MACE chip.
606 ---------------------------------------------------------------------------- */
607 static int mace_init(mace_private *lp, kio_addr_t ioaddr, char *enet_addr)
608 {
609 int i;
610 int ct = 0;
611
612 /* MACE Software reset */
613 mace_write(lp, ioaddr, MACE_BIUCC, 1);
614 while (mace_read(lp, ioaddr, MACE_BIUCC) & 0x01) {
615 /* Wait for reset bit to be cleared automatically after <= 200ns */;
616 if(++ct > 500)
617 {
618 printk(KERN_ERR "mace: reset failed, card removed ?\n");
619 return -1;
620 }
621 udelay(1);
622 }
623 mace_write(lp, ioaddr, MACE_BIUCC, 0);
624
625 /* The Am2150 requires that the MACE FIFOs operate in burst mode. */
626 mace_write(lp, ioaddr, MACE_FIFOCC, 0x0F);
627
628 mace_write(lp,ioaddr, MACE_RCVFC, 0); /* Disable Auto Strip Receive */
629 mace_write(lp, ioaddr, MACE_IMR, 0xFF); /* Disable all interrupts until _open */
630
631 /*
632 * Bit 2-1 PORTSEL[1-0] Port Select.
633 * 00 AUI/10Base-2
634 * 01 10Base-T
635 * 10 DAI Port (reserved in Am2150)
636 * 11 GPSI
637 * For this card, only the first two are valid.
638 * So, PLSCC should be set to
639 * 0x00 for 10Base-2
640 * 0x02 for 10Base-T
641 * Or just set ASEL in PHYCC below!
642 */
643 switch (if_port) {
644 case 1:
645 mace_write(lp, ioaddr, MACE_PLSCC, 0x02);
646 break;
647 case 2:
648 mace_write(lp, ioaddr, MACE_PLSCC, 0x00);
649 break;
650 default:
651 mace_write(lp, ioaddr, MACE_PHYCC, /* ASEL */ 4);
652 /* ASEL Auto Select. When set, the PORTSEL[1-0] bits are overridden,
653 and the MACE device will automatically select the operating media
654 interface port. */
655 break;
656 }
657
658 mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_PHYADDR);
659 /* Poll ADDRCHG bit */
660 ct = 0;
661 while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
662 {
663 if(++ ct > 500)
664 {
665 printk(KERN_ERR "mace: ADDRCHG timeout, card removed ?\n");
666 return -1;
667 }
668 }
669 /* Set PADR register */
670 for (i = 0; i < ETHER_ADDR_LEN; i++)
671 mace_write(lp, ioaddr, MACE_PADR, enet_addr[i]);
672
673 /* MAC Configuration Control Register should be written last */
674 /* Let set_multicast_list set this. */
675 /* mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); */
676 mace_write(lp, ioaddr, MACE_MACCC, 0x00);
677 return 0;
678 } /* mace_init */
679
680 /* ----------------------------------------------------------------------------
681 nmclan_config
682 This routine is scheduled to run after a CARD_INSERTION event
683 is received, to configure the PCMCIA socket, and to make the
684 ethernet device available to the system.
685 ---------------------------------------------------------------------------- */
686
687 #define CS_CHECK(fn, ret) \
688 do { last_fn = (fn); if ((last_ret = (ret)) != 0) goto cs_failed; } while (0)
689
690 static void nmclan_config(dev_link_t *link)
691 {
692 client_handle_t handle = link->handle;
693 struct net_device *dev = link->priv;
694 mace_private *lp = netdev_priv(dev);
695 tuple_t tuple;
696 cisparse_t parse;
697 u_char buf[64];
698 int i, last_ret, last_fn;
699 kio_addr_t ioaddr;
700
701 DEBUG(0, "nmclan_config(0x%p)\n", link);
702
703 tuple.Attributes = 0;
704 tuple.TupleData = buf;
705 tuple.TupleDataMax = 64;
706 tuple.TupleOffset = 0;
707 tuple.DesiredTuple = CISTPL_CONFIG;
708 CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(handle, &tuple));
709 CS_CHECK(GetTupleData, pcmcia_get_tuple_data(handle, &tuple));
710 CS_CHECK(ParseTuple, pcmcia_parse_tuple(handle, &tuple, &parse));
711 link->conf.ConfigBase = parse.config.base;
712
713 /* Configure card */
714 link->state |= DEV_CONFIG;
715
716 CS_CHECK(RequestIO, pcmcia_request_io(handle, &link->io));
717 CS_CHECK(RequestIRQ, pcmcia_request_irq(handle, &link->irq));
718 CS_CHECK(RequestConfiguration, pcmcia_request_configuration(handle, &link->conf));
719 dev->irq = link->irq.AssignedIRQ;
720 dev->base_addr = link->io.BasePort1;
721
722 ioaddr = dev->base_addr;
723
724 /* Read the ethernet address from the CIS. */
725 tuple.DesiredTuple = 0x80 /* CISTPL_CFTABLE_ENTRY_MISC */;
726 tuple.TupleData = buf;
727 tuple.TupleDataMax = 64;
728 tuple.TupleOffset = 0;
729 CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(handle, &tuple));
730 CS_CHECK(GetTupleData, pcmcia_get_tuple_data(handle, &tuple));
731 memcpy(dev->dev_addr, tuple.TupleData, ETHER_ADDR_LEN);
732
733 /* Verify configuration by reading the MACE ID. */
734 {
735 char sig[2];
736
737 sig[0] = mace_read(lp, ioaddr, MACE_CHIPIDL);
738 sig[1] = mace_read(lp, ioaddr, MACE_CHIPIDH);
739 if ((sig[0] == 0x40) && ((sig[1] & 0x0F) == 0x09)) {
740 DEBUG(0, "nmclan_cs configured: mace id=%x %x\n",
741 sig[0], sig[1]);
742 } else {
743 printk(KERN_NOTICE "nmclan_cs: mace id not found: %x %x should"
744 " be 0x40 0x?9\n", sig[0], sig[1]);
745 link->state &= ~DEV_CONFIG_PENDING;
746 return;
747 }
748 }
749
750 if(mace_init(lp, ioaddr, dev->dev_addr) == -1)
751 goto failed;
752
753 /* The if_port symbol can be set when the module is loaded */
754 if (if_port <= 2)
755 dev->if_port = if_port;
756 else
757 printk(KERN_NOTICE "nmclan_cs: invalid if_port requested\n");
758
759 link->dev = &lp->node;
760 link->state &= ~DEV_CONFIG_PENDING;
761 SET_NETDEV_DEV(dev, &handle_to_dev(handle));
762
763 i = register_netdev(dev);
764 if (i != 0) {
765 printk(KERN_NOTICE "nmclan_cs: register_netdev() failed\n");
766 link->dev = NULL;
767 goto failed;
768 }
769
770 strcpy(lp->node.dev_name, dev->name);
771
772 printk(KERN_INFO "%s: nmclan: port %#3lx, irq %d, %s port, hw_addr ",
773 dev->name, dev->base_addr, dev->irq, if_names[dev->if_port]);
774 for (i = 0; i < 6; i++)
775 printk("%02X%s", dev->dev_addr[i], ((i<5) ? ":" : "\n"));
776 return;
777
778 cs_failed:
779 cs_error(link->handle, last_fn, last_ret);
780 failed:
781 nmclan_release(link);
782 return;
783
784 } /* nmclan_config */
785
786 /* ----------------------------------------------------------------------------
787 nmclan_release
788 After a card is removed, nmclan_release() will unregister the
789 net device, and release the PCMCIA configuration. If the device
790 is still open, this will be postponed until it is closed.
791 ---------------------------------------------------------------------------- */
792 static void nmclan_release(dev_link_t *link)
793 {
794
795 DEBUG(0, "nmclan_release(0x%p)\n", link);
796
797 pcmcia_release_configuration(link->handle);
798 pcmcia_release_io(link->handle, &link->io);
799 pcmcia_release_irq(link->handle, &link->irq);
800
801 link->state &= ~DEV_CONFIG;
802 }
803
804 /* ----------------------------------------------------------------------------
805 nmclan_event
806 The card status event handler. Mostly, this schedules other
807 stuff to run after an event is received. A CARD_REMOVAL event
808 also sets some flags to discourage the net drivers from trying
809 to talk to the card any more.
810 ---------------------------------------------------------------------------- */
811 static int nmclan_event(event_t event, int priority,
812 event_callback_args_t *args)
813 {
814 dev_link_t *link = args->client_data;
815 struct net_device *dev = link->priv;
816
817 DEBUG(1, "nmclan_event(0x%06x)\n", event);
818
819 switch (event) {
820 case CS_EVENT_CARD_REMOVAL:
821 link->state &= ~DEV_PRESENT;
822 if (link->state & DEV_CONFIG)
823 netif_device_detach(dev);
824 break;
825 case CS_EVENT_CARD_INSERTION:
826 link->state |= DEV_PRESENT | DEV_CONFIG_PENDING;
827 nmclan_config(link);
828 break;
829 case CS_EVENT_PM_SUSPEND:
830 link->state |= DEV_SUSPEND;
831 /* Fall through... */
832 case CS_EVENT_RESET_PHYSICAL:
833 if (link->state & DEV_CONFIG) {
834 if (link->open)
835 netif_device_detach(dev);
836 pcmcia_release_configuration(link->handle);
837 }
838 break;
839 case CS_EVENT_PM_RESUME:
840 link->state &= ~DEV_SUSPEND;
841 /* Fall through... */
842 case CS_EVENT_CARD_RESET:
843 if (link->state & DEV_CONFIG) {
844 pcmcia_request_configuration(link->handle, &link->conf);
845 if (link->open) {
846 nmclan_reset(dev);
847 netif_device_attach(dev);
848 }
849 }
850 break;
851 case CS_EVENT_RESET_REQUEST:
852 return 1;
853 break;
854 }
855 return 0;
856 } /* nmclan_event */
857
858 /* ----------------------------------------------------------------------------
859 nmclan_reset
860 Reset and restore all of the Xilinx and MACE registers.
861 ---------------------------------------------------------------------------- */
862 static void nmclan_reset(struct net_device *dev)
863 {
864 mace_private *lp = netdev_priv(dev);
865
866 #if RESET_XILINX
867 dev_link_t *link = &lp->link;
868 conf_reg_t reg;
869 u_long OrigCorValue;
870
871 /* Save original COR value */
872 reg.Function = 0;
873 reg.Action = CS_READ;
874 reg.Offset = CISREG_COR;
875 reg.Value = 0;
876 pcmcia_access_configuration_register(link->handle, &reg);
877 OrigCorValue = reg.Value;
878
879 /* Reset Xilinx */
880 reg.Action = CS_WRITE;
881 reg.Offset = CISREG_COR;
882 DEBUG(1, "nmclan_reset: OrigCorValue=0x%lX, resetting...\n",
883 OrigCorValue);
884 reg.Value = COR_SOFT_RESET;
885 pcmcia_access_configuration_register(link->handle, &reg);
886 /* Need to wait for 20 ms for PCMCIA to finish reset. */
887
888 /* Restore original COR configuration index */
889 reg.Value = COR_LEVEL_REQ | (OrigCorValue & COR_CONFIG_MASK);
890 pcmcia_access_configuration_register(link->handle, &reg);
891 /* Xilinx is now completely reset along with the MACE chip. */
892 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
893
894 #endif /* #if RESET_XILINX */
895
896 /* Xilinx is now completely reset along with the MACE chip. */
897 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
898
899 /* Reinitialize the MACE chip for operation. */
900 mace_init(lp, dev->base_addr, dev->dev_addr);
901 mace_write(lp, dev->base_addr, MACE_IMR, MACE_IMR_DEFAULT);
902
903 /* Restore the multicast list and enable TX and RX. */
904 restore_multicast_list(dev);
905 } /* nmclan_reset */
906
907 /* ----------------------------------------------------------------------------
908 mace_config
909 [Someone tell me what this is supposed to do? Is if_port a defined
910 standard? If so, there should be defines to indicate 1=10Base-T,
911 2=10Base-2, etc. including limited automatic detection.]
912 ---------------------------------------------------------------------------- */
913 static int mace_config(struct net_device *dev, struct ifmap *map)
914 {
915 if ((map->port != (u_char)(-1)) && (map->port != dev->if_port)) {
916 if (map->port <= 2) {
917 dev->if_port = map->port;
918 printk(KERN_INFO "%s: switched to %s port\n", dev->name,
919 if_names[dev->if_port]);
920 } else
921 return -EINVAL;
922 }
923 return 0;
924 } /* mace_config */
925
926 /* ----------------------------------------------------------------------------
927 mace_open
928 Open device driver.
929 ---------------------------------------------------------------------------- */
930 static int mace_open(struct net_device *dev)
931 {
932 kio_addr_t ioaddr = dev->base_addr;
933 mace_private *lp = netdev_priv(dev);
934 dev_link_t *link = &lp->link;
935
936 if (!DEV_OK(link))
937 return -ENODEV;
938
939 link->open++;
940
941 MACEBANK(0);
942
943 netif_start_queue(dev);
944 nmclan_reset(dev);
945
946 return 0; /* Always succeed */
947 } /* mace_open */
948
949 /* ----------------------------------------------------------------------------
950 mace_close
951 Closes device driver.
952 ---------------------------------------------------------------------------- */
953 static int mace_close(struct net_device *dev)
954 {
955 kio_addr_t ioaddr = dev->base_addr;
956 mace_private *lp = netdev_priv(dev);
957 dev_link_t *link = &lp->link;
958
959 DEBUG(2, "%s: shutting down ethercard.\n", dev->name);
960
961 /* Mask off all interrupts from the MACE chip. */
962 outb(0xFF, ioaddr + AM2150_MACE_BASE + MACE_IMR);
963
964 link->open--;
965 netif_stop_queue(dev);
966
967 return 0;
968 } /* mace_close */
969
970 static void netdev_get_drvinfo(struct net_device *dev,
971 struct ethtool_drvinfo *info)
972 {
973 strcpy(info->driver, DRV_NAME);
974 strcpy(info->version, DRV_VERSION);
975 sprintf(info->bus_info, "PCMCIA 0x%lx", dev->base_addr);
976 }
977
978 #ifdef PCMCIA_DEBUG
979 static u32 netdev_get_msglevel(struct net_device *dev)
980 {
981 return pc_debug;
982 }
983
984 static void netdev_set_msglevel(struct net_device *dev, u32 level)
985 {
986 pc_debug = level;
987 }
988 #endif /* PCMCIA_DEBUG */
989
990 static struct ethtool_ops netdev_ethtool_ops = {
991 .get_drvinfo = netdev_get_drvinfo,
992 #ifdef PCMCIA_DEBUG
993 .get_msglevel = netdev_get_msglevel,
994 .set_msglevel = netdev_set_msglevel,
995 #endif /* PCMCIA_DEBUG */
996 };
997
998 /* ----------------------------------------------------------------------------
999 mace_start_xmit
1000 This routine begins the packet transmit function. When completed,
1001 it will generate a transmit interrupt.
1002
1003 According to /usr/src/linux/net/inet/dev.c, if _start_xmit
1004 returns 0, the "packet is now solely the responsibility of the
1005 driver." If _start_xmit returns non-zero, the "transmission
1006 failed, put skb back into a list."
1007 ---------------------------------------------------------------------------- */
1008
1009 static void mace_tx_timeout(struct net_device *dev)
1010 {
1011 mace_private *lp = netdev_priv(dev);
1012 dev_link_t *link = &lp->link;
1013
1014 printk(KERN_NOTICE "%s: transmit timed out -- ", dev->name);
1015 #if RESET_ON_TIMEOUT
1016 printk("resetting card\n");
1017 pcmcia_reset_card(link->handle, NULL);
1018 #else /* #if RESET_ON_TIMEOUT */
1019 printk("NOT resetting card\n");
1020 #endif /* #if RESET_ON_TIMEOUT */
1021 dev->trans_start = jiffies;
1022 netif_wake_queue(dev);
1023 }
1024
1025 static int mace_start_xmit(struct sk_buff *skb, struct net_device *dev)
1026 {
1027 mace_private *lp = netdev_priv(dev);
1028 kio_addr_t ioaddr = dev->base_addr;
1029
1030 netif_stop_queue(dev);
1031
1032 DEBUG(3, "%s: mace_start_xmit(length = %ld) called.\n",
1033 dev->name, (long)skb->len);
1034
1035 #if (!TX_INTERRUPTABLE)
1036 /* Disable MACE TX interrupts. */
1037 outb(MACE_IMR_DEFAULT | MACE_IR_XMTINT,
1038 ioaddr + AM2150_MACE_BASE + MACE_IMR);
1039 lp->tx_irq_disabled=1;
1040 #endif /* #if (!TX_INTERRUPTABLE) */
1041
1042 {
1043 /* This block must not be interrupted by another transmit request!
1044 mace_tx_timeout will take care of timer-based retransmissions from
1045 the upper layers. The interrupt handler is guaranteed never to
1046 service a transmit interrupt while we are in here.
1047 */
1048
1049 lp->linux_stats.tx_bytes += skb->len;
1050 lp->tx_free_frames--;
1051
1052 /* WARNING: Write the _exact_ number of bytes written in the header! */
1053 /* Put out the word header [must be an outw()] . . . */
1054 outw(skb->len, ioaddr + AM2150_XMT);
1055 /* . . . and the packet [may be any combination of outw() and outb()] */
1056 outsw(ioaddr + AM2150_XMT, skb->data, skb->len >> 1);
1057 if (skb->len & 1) {
1058 /* Odd byte transfer */
1059 outb(skb->data[skb->len-1], ioaddr + AM2150_XMT);
1060 }
1061
1062 dev->trans_start = jiffies;
1063
1064 #if MULTI_TX
1065 if (lp->tx_free_frames > 0)
1066 netif_start_queue(dev);
1067 #endif /* #if MULTI_TX */
1068 }
1069
1070 #if (!TX_INTERRUPTABLE)
1071 /* Re-enable MACE TX interrupts. */
1072 lp->tx_irq_disabled=0;
1073 outb(MACE_IMR_DEFAULT, ioaddr + AM2150_MACE_BASE + MACE_IMR);
1074 #endif /* #if (!TX_INTERRUPTABLE) */
1075
1076 dev_kfree_skb(skb);
1077
1078 return 0;
1079 } /* mace_start_xmit */
1080
1081 /* ----------------------------------------------------------------------------
1082 mace_interrupt
1083 The interrupt handler.
1084 ---------------------------------------------------------------------------- */
1085 static irqreturn_t mace_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1086 {
1087 struct net_device *dev = (struct net_device *) dev_id;
1088 mace_private *lp = netdev_priv(dev);
1089 kio_addr_t ioaddr = dev->base_addr;
1090 int status;
1091 int IntrCnt = MACE_MAX_IR_ITERATIONS;
1092
1093 if (dev == NULL) {
1094 DEBUG(2, "mace_interrupt(): irq 0x%X for unknown device.\n",
1095 irq);
1096 return IRQ_NONE;
1097 }
1098
1099 if (lp->tx_irq_disabled) {
1100 printk(
1101 (lp->tx_irq_disabled?
1102 KERN_NOTICE "%s: Interrupt with tx_irq_disabled "
1103 "[isr=%02X, imr=%02X]\n":
1104 KERN_NOTICE "%s: Re-entering the interrupt handler "
1105 "[isr=%02X, imr=%02X]\n"),
1106 dev->name,
1107 inb(ioaddr + AM2150_MACE_BASE + MACE_IR),
1108 inb(ioaddr + AM2150_MACE_BASE + MACE_IMR)
1109 );
1110 /* WARNING: MACE_IR has been read! */
1111 return IRQ_NONE;
1112 }
1113
1114 if (!netif_device_present(dev)) {
1115 DEBUG(2, "%s: interrupt from dead card\n", dev->name);
1116 return IRQ_NONE;
1117 }
1118
1119 do {
1120 /* WARNING: MACE_IR is a READ/CLEAR port! */
1121 status = inb(ioaddr + AM2150_MACE_BASE + MACE_IR);
1122
1123 DEBUG(3, "mace_interrupt: irq 0x%X status 0x%X.\n", irq, status);
1124
1125 if (status & MACE_IR_RCVINT) {
1126 mace_rx(dev, MACE_MAX_RX_ITERATIONS);
1127 }
1128
1129 if (status & MACE_IR_XMTINT) {
1130 unsigned char fifofc;
1131 unsigned char xmtrc;
1132 unsigned char xmtfs;
1133
1134 fifofc = inb(ioaddr + AM2150_MACE_BASE + MACE_FIFOFC);
1135 if ((fifofc & MACE_FIFOFC_XMTFC)==0) {
1136 lp->linux_stats.tx_errors++;
1137 outb(0xFF, ioaddr + AM2150_XMT_SKIP);
1138 }
1139
1140 /* Transmit Retry Count (XMTRC, reg 4) */
1141 xmtrc = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTRC);
1142 if (xmtrc & MACE_XMTRC_EXDEF) lp->mace_stats.exdef++;
1143 lp->mace_stats.xmtrc += (xmtrc & MACE_XMTRC_XMTRC);
1144
1145 if (
1146 (xmtfs = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTFS)) &
1147 MACE_XMTFS_XMTSV /* Transmit Status Valid */
1148 ) {
1149 lp->mace_stats.xmtsv++;
1150
1151 if (xmtfs & ~MACE_XMTFS_XMTSV) {
1152 if (xmtfs & MACE_XMTFS_UFLO) {
1153 /* Underflow. Indicates that the Transmit FIFO emptied before
1154 the end of frame was reached. */
1155 lp->mace_stats.uflo++;
1156 }
1157 if (xmtfs & MACE_XMTFS_LCOL) {
1158 /* Late Collision */
1159 lp->mace_stats.lcol++;
1160 }
1161 if (xmtfs & MACE_XMTFS_MORE) {
1162 /* MORE than one retry was needed */
1163 lp->mace_stats.more++;
1164 }
1165 if (xmtfs & MACE_XMTFS_ONE) {
1166 /* Exactly ONE retry occurred */
1167 lp->mace_stats.one++;
1168 }
1169 if (xmtfs & MACE_XMTFS_DEFER) {
1170 /* Transmission was defered */
1171 lp->mace_stats.defer++;
1172 }
1173 if (xmtfs & MACE_XMTFS_LCAR) {
1174 /* Loss of carrier */
1175 lp->mace_stats.lcar++;
1176 }
1177 if (xmtfs & MACE_XMTFS_RTRY) {
1178 /* Retry error: transmit aborted after 16 attempts */
1179 lp->mace_stats.rtry++;
1180 }
1181 } /* if (xmtfs & ~MACE_XMTFS_XMTSV) */
1182
1183 } /* if (xmtfs & MACE_XMTFS_XMTSV) */
1184
1185 lp->linux_stats.tx_packets++;
1186 lp->tx_free_frames++;
1187 netif_wake_queue(dev);
1188 } /* if (status & MACE_IR_XMTINT) */
1189
1190 if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) {
1191 if (status & MACE_IR_JAB) {
1192 /* Jabber Error. Excessive transmit duration (20-150ms). */
1193 lp->mace_stats.jab++;
1194 }
1195 if (status & MACE_IR_BABL) {
1196 /* Babble Error. >1518 bytes transmitted. */
1197 lp->mace_stats.babl++;
1198 }
1199 if (status & MACE_IR_CERR) {
1200 /* Collision Error. CERR indicates the absence of the
1201 Signal Quality Error Test message after a packet
1202 transmission. */
1203 lp->mace_stats.cerr++;
1204 }
1205 if (status & MACE_IR_RCVCCO) {
1206 /* Receive Collision Count Overflow; */
1207 lp->mace_stats.rcvcco++;
1208 }
1209 if (status & MACE_IR_RNTPCO) {
1210 /* Runt Packet Count Overflow */
1211 lp->mace_stats.rntpco++;
1212 }
1213 if (status & MACE_IR_MPCO) {
1214 /* Missed Packet Count Overflow */
1215 lp->mace_stats.mpco++;
1216 }
1217 } /* if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) */
1218
1219 } while ((status & ~MACE_IMR_DEFAULT) && (--IntrCnt));
1220
1221 return IRQ_HANDLED;
1222 } /* mace_interrupt */
1223
1224 /* ----------------------------------------------------------------------------
1225 mace_rx
1226 Receives packets.
1227 ---------------------------------------------------------------------------- */
1228 static int mace_rx(struct net_device *dev, unsigned char RxCnt)
1229 {
1230 mace_private *lp = netdev_priv(dev);
1231 kio_addr_t ioaddr = dev->base_addr;
1232 unsigned char rx_framecnt;
1233 unsigned short rx_status;
1234
1235 while (
1236 ((rx_framecnt = inb(ioaddr + AM2150_RCV_FRAME_COUNT)) > 0) &&
1237 (rx_framecnt <= 12) && /* rx_framecnt==0xFF if card is extracted. */
1238 (RxCnt--)
1239 ) {
1240 rx_status = inw(ioaddr + AM2150_RCV);
1241
1242 DEBUG(3, "%s: in mace_rx(), framecnt 0x%X, rx_status"
1243 " 0x%X.\n", dev->name, rx_framecnt, rx_status);
1244
1245 if (rx_status & MACE_RCVFS_RCVSTS) { /* Error, update stats. */
1246 lp->linux_stats.rx_errors++;
1247 if (rx_status & MACE_RCVFS_OFLO) {
1248 lp->mace_stats.oflo++;
1249 }
1250 if (rx_status & MACE_RCVFS_CLSN) {
1251 lp->mace_stats.clsn++;
1252 }
1253 if (rx_status & MACE_RCVFS_FRAM) {
1254 lp->mace_stats.fram++;
1255 }
1256 if (rx_status & MACE_RCVFS_FCS) {
1257 lp->mace_stats.fcs++;
1258 }
1259 } else {
1260 short pkt_len = (rx_status & ~MACE_RCVFS_RCVSTS) - 4;
1261 /* Auto Strip is off, always subtract 4 */
1262 struct sk_buff *skb;
1263
1264 lp->mace_stats.rfs_rntpc += inb(ioaddr + AM2150_RCV);
1265 /* runt packet count */
1266 lp->mace_stats.rfs_rcvcc += inb(ioaddr + AM2150_RCV);
1267 /* rcv collision count */
1268
1269 DEBUG(3, " receiving packet size 0x%X rx_status"
1270 " 0x%X.\n", pkt_len, rx_status);
1271
1272 skb = dev_alloc_skb(pkt_len+2);
1273
1274 if (skb != NULL) {
1275 skb->dev = dev;
1276
1277 skb_reserve(skb, 2);
1278 insw(ioaddr + AM2150_RCV, skb_put(skb, pkt_len), pkt_len>>1);
1279 if (pkt_len & 1)
1280 *(skb->tail-1) = inb(ioaddr + AM2150_RCV);
1281 skb->protocol = eth_type_trans(skb, dev);
1282
1283 netif_rx(skb); /* Send the packet to the upper (protocol) layers. */
1284
1285 dev->last_rx = jiffies;
1286 lp->linux_stats.rx_packets++;
1287 lp->linux_stats.rx_bytes += skb->len;
1288 outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1289 continue;
1290 } else {
1291 DEBUG(1, "%s: couldn't allocate a sk_buff of size"
1292 " %d.\n", dev->name, pkt_len);
1293 lp->linux_stats.rx_dropped++;
1294 }
1295 }
1296 outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1297 } /* while */
1298
1299 return 0;
1300 } /* mace_rx */
1301
1302 /* ----------------------------------------------------------------------------
1303 pr_linux_stats
1304 ---------------------------------------------------------------------------- */
1305 static void pr_linux_stats(struct net_device_stats *pstats)
1306 {
1307 DEBUG(2, "pr_linux_stats\n");
1308 DEBUG(2, " rx_packets=%-7ld tx_packets=%ld\n",
1309 (long)pstats->rx_packets, (long)pstats->tx_packets);
1310 DEBUG(2, " rx_errors=%-7ld tx_errors=%ld\n",
1311 (long)pstats->rx_errors, (long)pstats->tx_errors);
1312 DEBUG(2, " rx_dropped=%-7ld tx_dropped=%ld\n",
1313 (long)pstats->rx_dropped, (long)pstats->tx_dropped);
1314 DEBUG(2, " multicast=%-7ld collisions=%ld\n",
1315 (long)pstats->multicast, (long)pstats->collisions);
1316
1317 DEBUG(2, " rx_length_errors=%-7ld rx_over_errors=%ld\n",
1318 (long)pstats->rx_length_errors, (long)pstats->rx_over_errors);
1319 DEBUG(2, " rx_crc_errors=%-7ld rx_frame_errors=%ld\n",
1320 (long)pstats->rx_crc_errors, (long)pstats->rx_frame_errors);
1321 DEBUG(2, " rx_fifo_errors=%-7ld rx_missed_errors=%ld\n",
1322 (long)pstats->rx_fifo_errors, (long)pstats->rx_missed_errors);
1323
1324 DEBUG(2, " tx_aborted_errors=%-7ld tx_carrier_errors=%ld\n",
1325 (long)pstats->tx_aborted_errors, (long)pstats->tx_carrier_errors);
1326 DEBUG(2, " tx_fifo_errors=%-7ld tx_heartbeat_errors=%ld\n",
1327 (long)pstats->tx_fifo_errors, (long)pstats->tx_heartbeat_errors);
1328 DEBUG(2, " tx_window_errors=%ld\n",
1329 (long)pstats->tx_window_errors);
1330 } /* pr_linux_stats */
1331
1332 /* ----------------------------------------------------------------------------
1333 pr_mace_stats
1334 ---------------------------------------------------------------------------- */
1335 static void pr_mace_stats(mace_statistics *pstats)
1336 {
1337 DEBUG(2, "pr_mace_stats\n");
1338
1339 DEBUG(2, " xmtsv=%-7d uflo=%d\n",
1340 pstats->xmtsv, pstats->uflo);
1341 DEBUG(2, " lcol=%-7d more=%d\n",
1342 pstats->lcol, pstats->more);
1343 DEBUG(2, " one=%-7d defer=%d\n",
1344 pstats->one, pstats->defer);
1345 DEBUG(2, " lcar=%-7d rtry=%d\n",
1346 pstats->lcar, pstats->rtry);
1347
1348 /* MACE_XMTRC */
1349 DEBUG(2, " exdef=%-7d xmtrc=%d\n",
1350 pstats->exdef, pstats->xmtrc);
1351
1352 /* RFS1--Receive Status (RCVSTS) */
1353 DEBUG(2, " oflo=%-7d clsn=%d\n",
1354 pstats->oflo, pstats->clsn);
1355 DEBUG(2, " fram=%-7d fcs=%d\n",
1356 pstats->fram, pstats->fcs);
1357
1358 /* RFS2--Runt Packet Count (RNTPC) */
1359 /* RFS3--Receive Collision Count (RCVCC) */
1360 DEBUG(2, " rfs_rntpc=%-7d rfs_rcvcc=%d\n",
1361 pstats->rfs_rntpc, pstats->rfs_rcvcc);
1362
1363 /* MACE_IR */
1364 DEBUG(2, " jab=%-7d babl=%d\n",
1365 pstats->jab, pstats->babl);
1366 DEBUG(2, " cerr=%-7d rcvcco=%d\n",
1367 pstats->cerr, pstats->rcvcco);
1368 DEBUG(2, " rntpco=%-7d mpco=%d\n",
1369 pstats->rntpco, pstats->mpco);
1370
1371 /* MACE_MPC */
1372 DEBUG(2, " mpc=%d\n", pstats->mpc);
1373
1374 /* MACE_RNTPC */
1375 DEBUG(2, " rntpc=%d\n", pstats->rntpc);
1376
1377 /* MACE_RCVCC */
1378 DEBUG(2, " rcvcc=%d\n", pstats->rcvcc);
1379
1380 } /* pr_mace_stats */
1381
1382 /* ----------------------------------------------------------------------------
1383 update_stats
1384 Update statistics. We change to register window 1, so this
1385 should be run single-threaded if the device is active. This is
1386 expected to be a rare operation, and it's simpler for the rest
1387 of the driver to assume that window 0 is always valid rather
1388 than use a special window-state variable.
1389
1390 oflo & uflo should _never_ occur since it would mean the Xilinx
1391 was not able to transfer data between the MACE FIFO and the
1392 card's SRAM fast enough. If this happens, something is
1393 seriously wrong with the hardware.
1394 ---------------------------------------------------------------------------- */
1395 static void update_stats(kio_addr_t ioaddr, struct net_device *dev)
1396 {
1397 mace_private *lp = netdev_priv(dev);
1398
1399 lp->mace_stats.rcvcc += mace_read(lp, ioaddr, MACE_RCVCC);
1400 lp->mace_stats.rntpc += mace_read(lp, ioaddr, MACE_RNTPC);
1401 lp->mace_stats.mpc += mace_read(lp, ioaddr, MACE_MPC);
1402 /* At this point, mace_stats is fully updated for this call.
1403 We may now update the linux_stats. */
1404
1405 /* The MACE has no equivalent for linux_stats field which are commented
1406 out. */
1407
1408 /* lp->linux_stats.multicast; */
1409 lp->linux_stats.collisions =
1410 lp->mace_stats.rcvcco * 256 + lp->mace_stats.rcvcc;
1411 /* Collision: The MACE may retry sending a packet 15 times
1412 before giving up. The retry count is in XMTRC.
1413 Does each retry constitute a collision?
1414 If so, why doesn't the RCVCC record these collisions? */
1415
1416 /* detailed rx_errors: */
1417 lp->linux_stats.rx_length_errors =
1418 lp->mace_stats.rntpco * 256 + lp->mace_stats.rntpc;
1419 /* lp->linux_stats.rx_over_errors */
1420 lp->linux_stats.rx_crc_errors = lp->mace_stats.fcs;
1421 lp->linux_stats.rx_frame_errors = lp->mace_stats.fram;
1422 lp->linux_stats.rx_fifo_errors = lp->mace_stats.oflo;
1423 lp->linux_stats.rx_missed_errors =
1424 lp->mace_stats.mpco * 256 + lp->mace_stats.mpc;
1425
1426 /* detailed tx_errors */
1427 lp->linux_stats.tx_aborted_errors = lp->mace_stats.rtry;
1428 lp->linux_stats.tx_carrier_errors = lp->mace_stats.lcar;
1429 /* LCAR usually results from bad cabling. */
1430 lp->linux_stats.tx_fifo_errors = lp->mace_stats.uflo;
1431 lp->linux_stats.tx_heartbeat_errors = lp->mace_stats.cerr;
1432 /* lp->linux_stats.tx_window_errors; */
1433
1434 return;
1435 } /* update_stats */
1436
1437 /* ----------------------------------------------------------------------------
1438 mace_get_stats
1439 Gathers ethernet statistics from the MACE chip.
1440 ---------------------------------------------------------------------------- */
1441 static struct net_device_stats *mace_get_stats(struct net_device *dev)
1442 {
1443 mace_private *lp = netdev_priv(dev);
1444
1445 update_stats(dev->base_addr, dev);
1446
1447 DEBUG(1, "%s: updating the statistics.\n", dev->name);
1448 pr_linux_stats(&lp->linux_stats);
1449 pr_mace_stats(&lp->mace_stats);
1450
1451 return &lp->linux_stats;
1452 } /* net_device_stats */
1453
1454 /* ----------------------------------------------------------------------------
1455 updateCRC
1456 Modified from Am79C90 data sheet.
1457 ---------------------------------------------------------------------------- */
1458
1459 #ifdef BROKEN_MULTICAST
1460
1461 static void updateCRC(int *CRC, int bit)
1462 {
1463 int poly[]={
1464 1,1,1,0, 1,1,0,1,
1465 1,0,1,1, 1,0,0,0,
1466 1,0,0,0, 0,0,1,1,
1467 0,0,1,0, 0,0,0,0
1468 }; /* CRC polynomial. poly[n] = coefficient of the x**n term of the
1469 CRC generator polynomial. */
1470
1471 int j;
1472
1473 /* shift CRC and control bit (CRC[32]) */
1474 for (j = 32; j > 0; j--)
1475 CRC[j] = CRC[j-1];
1476 CRC[0] = 0;
1477
1478 /* If bit XOR(control bit) = 1, set CRC = CRC XOR polynomial. */
1479 if (bit ^ CRC[32])
1480 for (j = 0; j < 32; j++)
1481 CRC[j] ^= poly[j];
1482 } /* updateCRC */
1483
1484 /* ----------------------------------------------------------------------------
1485 BuildLAF
1486 Build logical address filter.
1487 Modified from Am79C90 data sheet.
1488
1489 Input
1490 ladrf: logical address filter (contents initialized to 0)
1491 adr: ethernet address
1492 ---------------------------------------------------------------------------- */
1493 static void BuildLAF(int *ladrf, int *adr)
1494 {
1495 int CRC[33]={1}; /* CRC register, 1 word/bit + extra control bit */
1496
1497 int i, byte; /* temporary array indices */
1498 int hashcode; /* the output object */
1499
1500 CRC[32]=0;
1501
1502 for (byte = 0; byte < 6; byte++)
1503 for (i = 0; i < 8; i++)
1504 updateCRC(CRC, (adr[byte] >> i) & 1);
1505
1506 hashcode = 0;
1507 for (i = 0; i < 6; i++)
1508 hashcode = (hashcode << 1) + CRC[i];
1509
1510 byte = hashcode >> 3;
1511 ladrf[byte] |= (1 << (hashcode & 7));
1512
1513 #ifdef PCMCIA_DEBUG
1514 if (pc_debug > 2) {
1515 printk(KERN_DEBUG " adr =");
1516 for (i = 0; i < 6; i++)
1517 printk(" %02X", adr[i]);
1518 printk("\n" KERN_DEBUG " hashcode = %d(decimal), ladrf[0:63]"
1519 " =", hashcode);
1520 for (i = 0; i < 8; i++)
1521 printk(" %02X", ladrf[i]);
1522 printk("\n");
1523 }
1524 #endif
1525 } /* BuildLAF */
1526
1527 /* ----------------------------------------------------------------------------
1528 restore_multicast_list
1529 Restores the multicast filter for MACE chip to the last
1530 set_multicast_list() call.
1531
1532 Input
1533 multicast_num_addrs
1534 multicast_ladrf[]
1535 ---------------------------------------------------------------------------- */
1536 static void restore_multicast_list(struct net_device *dev)
1537 {
1538 mace_private *lp = netdev_priv(dev);
1539 int num_addrs = lp->multicast_num_addrs;
1540 int *ladrf = lp->multicast_ladrf;
1541 kio_addr_t ioaddr = dev->base_addr;
1542 int i;
1543
1544 DEBUG(2, "%s: restoring Rx mode to %d addresses.\n",
1545 dev->name, num_addrs);
1546
1547 if (num_addrs > 0) {
1548
1549 DEBUG(1, "Attempt to restore multicast list detected.\n");
1550
1551 mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_LOGADDR);
1552 /* Poll ADDRCHG bit */
1553 while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
1554 ;
1555 /* Set LADRF register */
1556 for (i = 0; i < MACE_LADRF_LEN; i++)
1557 mace_write(lp, ioaddr, MACE_LADRF, ladrf[i]);
1558
1559 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_RCVFCSE | MACE_UTR_LOOP_EXTERNAL);
1560 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1561
1562 } else if (num_addrs < 0) {
1563
1564 /* Promiscuous mode: receive all packets */
1565 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1566 mace_write(lp, ioaddr, MACE_MACCC,
1567 MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1568 );
1569
1570 } else {
1571
1572 /* Normal mode */
1573 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1574 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1575
1576 }
1577 } /* restore_multicast_list */
1578
1579 /* ----------------------------------------------------------------------------
1580 set_multicast_list
1581 Set or clear the multicast filter for this adaptor.
1582
1583 Input
1584 num_addrs == -1 Promiscuous mode, receive all packets
1585 num_addrs == 0 Normal mode, clear multicast list
1586 num_addrs > 0 Multicast mode, receive normal and MC packets, and do
1587 best-effort filtering.
1588 Output
1589 multicast_num_addrs
1590 multicast_ladrf[]
1591 ---------------------------------------------------------------------------- */
1592
1593 static void set_multicast_list(struct net_device *dev)
1594 {
1595 mace_private *lp = netdev_priv(dev);
1596 int adr[ETHER_ADDR_LEN] = {0}; /* Ethernet address */
1597 int i;
1598 struct dev_mc_list *dmi = dev->mc_list;
1599
1600 #ifdef PCMCIA_DEBUG
1601 if (pc_debug > 1) {
1602 static int old;
1603 if (dev->mc_count != old) {
1604 old = dev->mc_count;
1605 DEBUG(0, "%s: setting Rx mode to %d addresses.\n",
1606 dev->name, old);
1607 }
1608 }
1609 #endif
1610
1611 /* Set multicast_num_addrs. */
1612 lp->multicast_num_addrs = dev->mc_count;
1613
1614 /* Set multicast_ladrf. */
1615 if (num_addrs > 0) {
1616 /* Calculate multicast logical address filter */
1617 memset(lp->multicast_ladrf, 0, MACE_LADRF_LEN);
1618 for (i = 0; i < dev->mc_count; i++) {
1619 memcpy(adr, dmi->dmi_addr, ETHER_ADDR_LEN);
1620 dmi = dmi->next;
1621 BuildLAF(lp->multicast_ladrf, adr);
1622 }
1623 }
1624
1625 restore_multicast_list(dev);
1626
1627 } /* set_multicast_list */
1628
1629 #endif /* BROKEN_MULTICAST */
1630
1631 static void restore_multicast_list(struct net_device *dev)
1632 {
1633 kio_addr_t ioaddr = dev->base_addr;
1634 mace_private *lp = netdev_priv(dev);
1635
1636 DEBUG(2, "%s: restoring Rx mode to %d addresses.\n", dev->name,
1637 lp->multicast_num_addrs);
1638
1639 if (dev->flags & IFF_PROMISC) {
1640 /* Promiscuous mode: receive all packets */
1641 mace_write(lp,ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1642 mace_write(lp, ioaddr, MACE_MACCC,
1643 MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1644 );
1645 } else {
1646 /* Normal mode */
1647 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1648 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1649 }
1650 } /* restore_multicast_list */
1651
1652 static void set_multicast_list(struct net_device *dev)
1653 {
1654 mace_private *lp = netdev_priv(dev);
1655
1656 #ifdef PCMCIA_DEBUG
1657 if (pc_debug > 1) {
1658 static int old;
1659 if (dev->mc_count != old) {
1660 old = dev->mc_count;
1661 DEBUG(0, "%s: setting Rx mode to %d addresses.\n",
1662 dev->name, old);
1663 }
1664 }
1665 #endif
1666
1667 lp->multicast_num_addrs = dev->mc_count;
1668 restore_multicast_list(dev);
1669
1670 } /* set_multicast_list */
1671
1672 static struct pcmcia_device_id nmclan_ids[] = {
1673 PCMCIA_DEVICE_PROD_ID12("New Media Corporation", "Ethernet", 0x085a850b, 0x00b2e941),
1674 PCMCIA_DEVICE_PROD_ID12("Portable Add-ons", "Ethernet+", 0xebf1d60, 0xad673aaf),
1675 PCMCIA_DEVICE_NULL,
1676 };
1677 MODULE_DEVICE_TABLE(pcmcia, nmclan_ids);
1678
1679 static struct pcmcia_driver nmclan_cs_driver = {
1680 .owner = THIS_MODULE,
1681 .drv = {
1682 .name = "nmclan_cs",
1683 },
1684 .attach = nmclan_attach,
1685 .event = nmclan_event,
1686 .detach = nmclan_detach,
1687 .id_table = nmclan_ids,
1688 };
1689
1690 static int __init init_nmclan_cs(void)
1691 {
1692 return pcmcia_register_driver(&nmclan_cs_driver);
1693 }
1694
1695 static void __exit exit_nmclan_cs(void)
1696 {
1697 pcmcia_unregister_driver(&nmclan_cs_driver);
1698 BUG_ON(dev_list != NULL);
1699 }
1700
1701 module_init(init_nmclan_cs);
1702 module_exit(exit_nmclan_cs);
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