| blob | c72e9620bf8dc67164dfc64eaa9da2488e834282 |
1 /*
2 * amd5536.c -- AMD 5536 UDC high/full speed USB device controller
3 *
4 * Copyright (C) 2005-2007 AMD (http://www.amd.com)
5 * Author: Thomas Dahlmann
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
22 /*
23 * The AMD5536 UDC is part of the x86 southbridge AMD Geode CS5536.
24 * It is a USB Highspeed DMA capable USB device controller. Beside ep0 it
25 * provides 4 IN and 4 OUT endpoints (bulk or interrupt type).
26 *
27 * Make sure that UDC is assigned to port 4 by BIOS settings (port can also
28 * be used as host port) and UOC bits PAD_EN and APU are set (should be done
29 * by BIOS init).
30 *
31 * UDC DMA requires 32-bit aligned buffers so DMA with gadget ether does not
32 * work without updating NET_IP_ALIGN. Or PIO mode (module param "use_dma=0")
33 * can be used with gadget ether.
34 */
36 /* debug control */
37 /* #define UDC_VERBOSE */
39 /* Driver strings */
43 /* system */
44 #include <linux/module.h>
45 #include <linux/pci.h>
46 #include <linux/kernel.h>
47 #include <linux/version.h>
48 #include <linux/delay.h>
49 #include <linux/ioport.h>
50 #include <linux/sched.h>
51 #include <linux/slab.h>
52 #include <linux/smp_lock.h>
53 #include <linux/errno.h>
54 #include <linux/init.h>
55 #include <linux/timer.h>
56 #include <linux/list.h>
57 #include <linux/interrupt.h>
58 #include <linux/ioctl.h>
59 #include <linux/fs.h>
60 #include <linux/dmapool.h>
61 #include <linux/moduleparam.h>
62 #include <linux/device.h>
63 #include <linux/io.h>
64 #include <linux/irq.h>
66 #include <asm/byteorder.h>
67 #include <asm/system.h>
68 #include <asm/unaligned.h>
70 /* gadget stack */
71 #include <linux/usb/ch9.h>
72 #include <linux/usb/gadget.h>
74 /* udc specific */
93 /* description */
97 /* structure to hold endpoint function pointers */
100 /* received setup data */
103 /* pointer to device object */
106 /* irq spin lock for soft reset */
108 /* stall spin lock */
111 /*
112 * slave mode: pending bytes in rx fifo after nyet,
113 * used if EPIN irq came but no req was available
114 */
117 /* count soft resets after suspend to avoid loop */
121 /* timer */
125 /* set_rde -- Is used to control enabling of RX DMA. Problem is
126 * that UDC has only one bit (RDE) to enable/disable RX DMA for
127 * all OUT endpoints. So we have to handle race conditions like
128 * when OUT data reaches the fifo but no request was queued yet.
129 * This cannot be solved by letting the RX DMA disabled until a
130 * request gets queued because there may be other OUT packets
131 * in the FIFO (important for not blocking control traffic).
132 * The value of set_rde controls the correspondig timer.
133 *
134 * set_rde -1 == not used, means it is alloed to be set to 0 or 1
135 * set_rde 0 == do not touch RDE, do no start the RDE timer
136 * set_rde 1 == timer function will look whether FIFO has data
137 * set_rde 2 == set by timer function to enable RX DMA on next call
138 */
146 /* tasklet for usb disconnect */
151 /* endpoint names used for print */
154 ep0_string,
162 };
164 /* DMA usage flag */
166 /* packet per buffer dma */
168 /* with per descr. update */
170 /* buffer fill mode */
172 /* full speed only mode */
174 /* tx buffer size for high speed */
177 /* module parameters */
188 /*---------------------------------------------------------------------------*/
189 /* Prints UDC device registers and endpoint irq registers */
191 {
212 }
216 }
219 }
221 }
223 /* Masks unused interrupts */
225 {
226 u32 tmp;
228 /* mask all dev interrupts */
239 /* mask all ep interrupts */
243 }
245 /* Enables endpoint 0 interrupts */
247 {
248 u32 tmp;
252 /* read irq mask */
254 /* enable ep0 irq's */
260 }
262 /* Enables device interrupts for SET_INTF and SET_CONFIG */
264 {
265 u32 tmp;
269 /* read irq mask */
272 /* enable SET_INTERFACE, SET_CONFIG and other needed irq's */
281 }
283 /* Calculates fifo start of endpoint based on preceeding endpoints */
285 {
287 u32 tmp;
296 /* traverse ep's */
299 /* read fifo size */
303 }
304 }
306 }
308 /* CNAK pending field: bit0 = ep0in, bit16 = ep0out */
312 {
319 }
322 /* Enables endpoint, is called by gadget driver */
323 static int
325 {
328 u32 tmp;
330 u8 udc_csr_epix;
334 || !desc
351 /* set traffic type */
356 /* set max packet size */
362 /* IN ep */
365 /* ep ix in UDC CSR register space */
368 /* set buffer size (tx fifo entries) */
370 /* double buffering: fifo size = 2 x max packet size */
372 tmp,
375 UDC_EPIN_BUFF_SIZE);
378 /* calc. tx fifo base addr */
381 /* flush fifo */
386 /* OUT ep */
388 /* ep ix in UDC CSR register space */
391 /* set max packet size UDC CSR */
394 UDC_CSR_NE_MAX_PKT);
398 /* alloc and init BNA dummy request */
401 }
405 }
407 /* set ep values */
409 /* max packet */
411 /* ep number */
413 /* ep direction */
415 /* ep type */
417 /* ep config */
419 /* ep interface */
421 /* ep alt */
423 /* write reg */
426 /* enable ep irq */
431 /*
432 * clear NAK by writing CNAK
433 * avoid BNA for OUT DMA, don't clear NAK until DMA desc. written
434 */
441 }
447 }
449 /* Resets endpoint */
451 {
452 u32 tmp;
460 /* set NAK */
466 /* disable interrupt */
472 /* unset P and IN bit of potential former DMA */
481 /* flush the fifo */
486 }
487 /* reset desc pointer */
489 }
491 /* Disables endpoint, is called by gadget driver */
493 {
513 }
515 /* Allocates request packet, called by gadget driver */
518 {
537 /* ep0 in requests are allocated from data pool here */
543 }
549 /* prevent from using desc. - set HOST BUSY */
551 UDC_DMA_STP_STS_BS_HOST_BUSY,
552 UDC_DMA_STP_STS_BS);
557 }
560 }
562 /* Frees request packet, called by gadget driver */
563 static void
565 {
579 /* free dma chain if created */
582 }
586 }
588 }
590 /* Init BNA dummy descriptor for HOST BUSY and pointing to itself */
592 {
594 /* set last bit */
596 /* set next pointer to itself */
598 /* set HOST BUSY */
601 UDC_DMA_STP_STS_BS_DMA_DONE,
602 UDC_DMA_STP_STS_BS);
603 #ifdef UDC_VERBOSE
606 #endif
607 }
608 }
610 /* Allocate BNA dummy descriptor */
612 {
616 /* alloc the dummy request */
622 }
624 }
626 /* Write data to TX fifo for IN packets */
627 static void
629 {
649 /* dwords first */
652 }
654 /* remaining bytes must be written by byte access */
658 }
660 /* dummy write confirm */
662 }
664 /* Read dwords from RX fifo for OUT transfers */
666 {
673 }
675 }
677 /* Read bytes from RX fifo for OUT transfers */
679 {
681 u32 tmp;
685 /* dwords first */
688 }
690 /* remaining bytes must be read by byte access */
696 }
697 }
700 }
702 /* Read data from RX fifo for OUT transfers */
703 static int
705 {
711 /* received number bytes */
723 }
725 }
728 /* last packet ? */
733 /* read rx fifo bytes */
738 }
740 /* create/re-init a DMA descriptor or a DMA descriptor chain */
742 {
744 u32 tmp;
750 /* set buffer pointer */
753 /* set last bit */
756 /* build/re-init dma chain if maxpkt scatter mode, not for EP0 */
764 }
767 /* write tx bytes */
771 UDC_DMA_IN_STS_TXBYTES);
773 }
774 }
776 }
783 /*
784 * if bytes < max packet then tx bytes must
785 * be written in packet per buffer mode
786 */
790 /* write tx bytes */
794 UDC_DMA_IN_STS_TXBYTES);
795 /* reset frame num */
799 UDC_DMA_IN_STS_FRAMENUM);
800 }
801 /* set HOST BUSY */
804 UDC_DMA_STP_STS_BS_HOST_BUSY,
805 UDC_DMA_STP_STS_BS);
808 /* set HOST READY */
811 UDC_DMA_STP_STS_BS_HOST_READY,
812 UDC_DMA_STP_STS_BS);
815 /* clear NAK by writing CNAK */
822 }
824 }
827 }
829 /* Completes request packet ... caller MUST hold lock */
830 static void
834 {
841 /* unmap DMA */
847 PCI_DMA_TODEVICE);
848 else
852 PCI_DMA_FROMDEVICE);
855 }
860 /* set new status if pending */
864 /* remove from ep queue */
874 }
876 /* frees pci pool descriptors of a DMA chain */
878 {
887 /* do not free first desc., will be done by free for request */
897 }
900 }
902 /* Iterates to the end of a DMA chain and returns last descriptor */
904 {
910 }
914 }
916 /* Iterates to the end of a DMA chain and counts bytes received */
918 {
920 u32 count;
923 /* received number bytes */
928 /* received number bytes */
931 UDC_DMA_OUT_STS_RXBYTES);
932 }
933 }
937 }
939 /* Creates or re-inits a DMA chain */
944 )
945 {
948 dma_addr_t dma_addr;
959 /* unset L bit in first desc for OUT */
962 }
964 /* alloc only new desc's if not already available */
967 len++;
968 }
971 /* shorter chain already allocated before */
974 }
977 }
980 /* gen. required number of descriptors and buffers */
982 /* create or determine next desc. */
992 /* first td */
999 }
1004 else
1007 /* short packet ? */
1011 /* short packet */
1013 }
1015 /* link td and assign tx bytes */
1020 /* req->td_data->next = virt_to_phys(td); */
1021 }
1022 /* write tx bytes */
1024 /* first desc */
1028 UDC_DMA_IN_STS_TXBYTES);
1029 /* second desc */
1031 txbytes,
1032 UDC_DMA_IN_STS_TXBYTES);
1033 }
1038 /* last->next = virt_to_phys(td); */
1039 }
1041 /* write tx bytes */
1043 txbytes,
1044 UDC_DMA_IN_STS_TXBYTES);
1045 }
1046 }
1048 }
1049 /* set last bit */
1052 /* last desc. points to itself */
1054 }
1057 }
1059 /* Enabling RX DMA */
1061 {
1062 u32 tmp;
1065 /* stop RDE timer */
1069 }
1070 /* set RDE */
1074 }
1076 /* Queues a request packet, called by gadget driver */
1077 static int
1079 {
1086 u32 tmp;
1088 /* check the inputs */
1105 /* map dma (usually done before) */
1113 PCI_DMA_TODEVICE);
1114 else
1118 PCI_DMA_FROMDEVICE);
1120 }
1131 /* on empty queue just do first transfer */
1133 /* zlp */
1135 /* IN zlp's are handled by hardware */
1138 /*
1139 * if set_config or set_intf is waiting for ack by zlp
1140 * then set CSR_DONE
1141 */
1147 }
1148 /* setup command is ACK'ed now by zlp */
1150 /* clear NAK by writing CNAK in EP0_IN */
1156 UDC_EP0IN_IX);
1158 }
1160 }
1165 /* write desc pointer to enable DMA */
1167 /* set HOST READY */
1170 UDC_DMA_IN_STS_BS_HOST_READY,
1171 UDC_DMA_IN_STS_BS);
1172 }
1174 /* disabled rx dma while descriptor update */
1176 /* stop RDE timer */
1180 }
1181 /* clear RDE */
1187 /*
1188 * if BNA occurred then let BNA dummy desc.
1189 * point to current desc.
1190 */
1196 }
1197 }
1198 /* write desc pointer */
1201 /* clear NAK by writing CNAK */
1208 }
1211 /* enable ep irq */
1215 }
1216 }
1220 /*
1221 * prep_dma not used for OUT ep's, this is not possible
1222 * for PPB modes, because of chain creation reasons
1223 */
1228 }
1229 }
1231 /* add request to ep queue */
1236 /* open rxfifo if out data queued */
1238 /* enable DMA */
1243 }
1244 /* stop OUT naking */
1249 /*
1250 * read pending bytes afer nyet:
1251 * referring to isr
1252 */
1254 /* finish */
1256 }
1259 }
1260 }
1261 }
1263 finished:
1266 }
1268 /* Empty request queue of an endpoint; caller holds spinlock */
1270 {
1277 queue);
1279 }
1280 }
1282 /* Dequeues a request packet, called by gadget driver */
1284 {
1300 /* request in processing or next one */
1306 u32 tmp;
1307 u32 dma_sts;
1308 /* stop potential receive DMA */
1312 /*
1313 * Cancel transfer later in ISR
1314 * if descriptor was touched.
1315 */
1317 UDC_DMA_OUT_STS_BS);
1324 }
1326 }
1327 }
1328 }
1334 }
1336 /* Halt or clear halt of endpoint */
1337 static int
1339 {
1341 u32 tmp;
1357 /* halt or clear halt */
1362 /*
1363 * set STALL
1364 * rxfifo empty not taken into acount
1365 */
1371 /* setup poll timer */
1374 HZ * UDC_POLLSTALL_TIMER_USECONDS
1379 }
1380 }
1381 }
1383 /* ep is halted by set_halt() before */
1386 /* clear stall bit */
1388 /* clear NAK by writing CNAK */
1393 }
1394 }
1397 }
1399 /* gadget interface */
1411 /* fifo ops not implemented */
1412 };
1414 /*-------------------------------------------------------------------------*/
1416 /* Get frame counter (not implemented) */
1418 {
1420 }
1422 /* Remote wakeup gadget interface */
1424 {
1433 }
1435 /* gadget operations */
1439 };
1441 /* Setups endpoint parameters, adds endpoints to linked list */
1443 {
1444 /* make gadget ep lists */
1453 /* fifo config */
1460 }
1462 /* init registers at driver load time */
1464 {
1465 u32 tmp;
1467 /* init controller by soft reset */
1470 /* mask not needed interrupts */
1473 /* put into initial config */
1475 /* link up all endpoints */
1478 /* program speed */
1484 }
1488 }
1490 /* Inits UDC context */
1492 {
1493 u32 tmp;
1499 /* stop RDE timer */
1503 }
1504 /* stop poll stall timer */
1507 }
1508 /* disable DMA */
1514 /* enable dynamic CSR programming */
1517 /* set self powered */
1519 /* set remote wakeupable */
1527 }
1529 /* Sets initial endpoint parameters */
1531 {
1533 u32 tmp;
1534 u32 reg;
1538 /* read enum speed */
1545 }
1547 /* set basic ep parameters */
1553 /* txfifo size is calculated at enable time */
1556 /* fifo size */
1564 }
1566 /*
1567 * ep will be reset only if ep was not enabled before to avoid
1568 * disabling ep interrupts when ENUM interrupt occurs but ep is
1569 * not enabled by gadget driver
1570 */
1573 }
1576 /*
1577 * ep->dma is not really used, just to indicate that
1578 * DMA is active: remove this
1579 * dma regs = dev control regs
1580 */
1583 /* nak OUT endpoints until enable - not for ep0 */
1586 /* set NAK */
1592 }
1593 }
1594 }
1595 /* EP0 max packet */
1599 UDC_FS_EP0OUT_MAX_PKT_SIZE;
1603 }
1605 /*
1606 * with suspend bug workaround, ep0 params for gadget driver
1607 * are set at gadget driver bind() call
1608 */
1613 /* init cfg/alt/int */
1617 }
1619 /* Bringup after Connect event, initial bringup to be ready for ep0 events */
1621 {
1627 /* put into initial config */
1630 /* enable device setup interrupts */
1632 }
1634 /*
1635 * Calls gadget with disconnect event and resets the UDC and makes
1636 * initial bringup to be ready for ep0 events
1637 */
1639 {
1645 /* mask interrupts */
1648 /* REVISIT there doesn't seem to be a point to having this
1649 * talk to a tasklet ... do it directly, we already hold
1650 * the spinlock needed to process the disconnect.
1651 */
1654 }
1656 /* Tasklet for disconnect to be outside of interrupt context */
1658 {
1660 u32 tmp;
1670 /* empty queues */
1673 }
1675 }
1677 /* disable ep0 */
1683 /* init controller by soft reset */
1685 soft_reset_occured++;
1686 }
1688 /* re-enable dev interrupts */
1690 /* back to full speed ? */
1695 }
1698 }
1700 /* Reset the UDC core */
1702 {
1706 /*
1707 * reset possible waiting interrupts, because int.
1708 * status is lost after soft reset,
1709 * ep int. status reset
1710 */
1712 /* device int. status reset */
1720 }
1722 /* RDE timer callback to set RDE bit */
1724 {
1725 u32 tmp;
1730 /*
1731 * open the fifo if fifo was filled on last timer call
1732 * conditionally
1733 */
1735 /* set RDE to receive setup data */
1742 /*
1743 * if fifo empty setup polling, do not just
1744 * open the fifo
1745 */
1749 }
1751 /*
1752 * fifo contains data now, setup timer for opening
1753 * the fifo when timer expires to be able to receive
1754 * setup packets, when data packets gets queued by
1755 * gadget layer then timer will forced to expire with
1756 * set_rde=0 (RDE is set in udc_queue())
1757 */
1758 set_rde++;
1759 /* debug: lhadmot_timer_start = 221070 */
1763 }
1764 }
1772 }
1774 /* Handle halt state, used in stall poll timer */
1776 {
1777 u32 tmp;
1778 /* set stall as long not halted */
1781 /* STALL cleared ? */
1783 /*
1784 * FIXME: MSC spec requires that stall remains
1785 * even on receivng of CLEAR_FEATURE HALT. So
1786 * we would set STALL again here to be compliant.
1787 * But with current mass storage drivers this does
1788 * not work (would produce endless host retries).
1789 * So we clear halt on CLEAR_FEATURE.
1790 *
1791 DBG(ep->dev, "ep %d: set STALL again\n", ep->num);
1792 tmp |= AMD_BIT(UDC_EPCTL_S);
1793 writel(tmp, &ep->regs->ctl);*/
1795 /* clear NAK by writing CNAK */
1800 }
1801 }
1802 }
1804 /* Stall timer callback to poll S bit and set it again after */
1806 {
1811 /*
1812 * only one IN and OUT endpoints are handled
1813 * IN poll stall
1814 */
1819 /* OUT poll stall */
1825 /* setup timer again when still halted */
1828 HZ * UDC_POLLSTALL_TIMER_USECONDS
1831 }
1836 }
1838 /* Inits endpoint 0 so that SETUP packets are processed */
1840 {
1841 u32 tmp;
1845 /* flush fifo */
1850 /* set ep0 directions */
1854 /* set buffer size (tx fifo entries) of EP0_IN */
1858 UDC_EPIN_BUFF_SIZE);
1861 UDC_EPIN_BUFF_SIZE);
1864 /* set max packet size of EP0_IN */
1868 UDC_EP_MAX_PKT_SIZE);
1871 UDC_EP_MAX_PKT_SIZE);
1874 /* set max packet size of EP0_OUT */
1878 UDC_EP_MAX_PKT_SIZE);
1881 UDC_EP_MAX_PKT_SIZE);
1884 /* set max packet size of EP0 in UDC CSR */
1888 UDC_CSR_NE_MAX_PKT);
1891 UDC_CSR_NE_MAX_PKT);
1897 /* write dma desc address */
1902 /* stop RDE timer */
1906 }
1907 /* stop pollstall timer */
1910 }
1911 /* enable DMA */
1920 }
1922 }
1924 /* clear NAK by writing CNAK for EP0IN */
1931 /* clear NAK by writing CNAK for EP0OUT */
1937 }
1939 /* Make endpoint 0 ready for control traffic */
1941 {
1943 /* enable ep0 interrupts */
1945 /* enable device setup interrupts */
1949 }
1951 /* Called by gadget driver to register itself */
1953 {
1956 u32 tmp;
1972 /* Some gadget drivers use both ep0 directions.
1973 * NOTE: to gadget driver, ep0 is just one endpoint...
1974 */
1984 }
1986 /* get ready for ep0 traffic */
1989 /* clear SD */
1997 }
2000 /* shutdown requests and disconnect from gadget */
2001 static void
2005 {
2008 /* empty queues and init hardware */
2012 }
2018 }
2019 /* init */
2021 }
2023 /* Called by gadget driver to unregister itself */
2025 {
2028 u32 tmp;
2043 /* set SD */
2052 }
2056 /* Clear pending NAK bits */
2058 {
2059 u32 tmp;
2060 u32 reg;
2062 /* check epin's */
2067 /* clear NAK by writing CNAK */
2073 }
2074 }
2075 /* ... and ep0out */
2078 /* clear NAK by writing CNAK */
2085 }
2086 }
2088 /* Enabling RX DMA after setup packet */
2090 {
2092 /*
2093 * only enable RXDMA when no data endpoint enabled
2094 * or data is queued
2095 */
2099 /*
2100 * setup timer for enabling RDE (to not enable
2101 * RXFIFO DMA for data endpoints to early)
2102 */
2109 }
2110 }
2111 }
2112 }
2113 }
2116 /* Interrupt handler for data OUT traffic */
2118 {
2120 u32 tmp;
2132 /* BNA event ? */
2136 /* clear BNA */
2140 else
2144 }
2145 }
2146 /* HE event ? */
2150 /* clear HE */
2154 }
2158 /* next request */
2164 }
2166 /* fifo mode */
2169 /* read fifo */
2173 /* finish */
2175 /* next request */
2181 }
2183 /* DMA */
2187 /* check for DMA done */
2190 UDC_DMA_OUT_STS_BS);
2191 /* packet per buffer mode - rx bytes */
2193 /*
2194 * if BNA occurred then recover desc. from
2195 * BNA dummy desc.
2196 */
2203 }
2206 }
2208 /* buffer fill mode - rx bytes */
2210 /* received number bytes */
2212 UDC_DMA_OUT_STS_RXBYTES);
2214 /* packet per buffer mode - rx bytes */
2218 /* received number bytes */
2220 /* every desc. counts bytes */
2223 /* last desc. counts bytes */
2225 UDC_DMA_OUT_STS_RXBYTES);
2228 /*
2229 * on 64k packets the RXBYTES
2230 * field is zero
2231 */
2233 }
2234 }
2236 }
2244 }
2246 }
2249 /* complete request */
2252 /* next request */
2256 queue);
2257 /*
2258 * DMA may be already started by udc_queue()
2259 * called by gadget drivers completion
2260 * routine. This happens when queue
2261 * holds one request only.
2262 */
2264 /* next dma */
2267 /* write desc pointer */
2271 /* enable DMA */
2273 }
2275 /*
2276 * implant BNA dummy descriptor to allow
2277 * RXFIFO opening by RDE
2278 */
2280 /* write desc pointer */
2284 }
2286 /*
2287 * schedule timer for setting RDE if queue
2288 * remains empty to allow ep0 packets pass
2289 * through
2290 */
2294 jiffies
2299 }
2300 }
2303 }
2306 /*
2307 * RX DMA must be reenabled for each desc in PPBDU mode
2308 * and must be enabled for PPBNDU mode in case of BNA
2309 */
2311 }
2316 }
2318 /* check pending CNAKS */
2320 /* CNAk processing when rxfifo empty only */
2323 }
2324 }
2326 /* clear OUT bits in ep status */
2328 finished:
2330 }
2332 /* Interrupt handler for data IN traffic */
2334 {
2336 u32 tmp;
2337 u32 epsts;
2348 /* BNA ? */
2355 /* clear BNA */
2359 }
2360 }
2361 /* HE event ? */
2367 /* clear HE */
2371 }
2373 /* DMA completion */
2381 /*
2382 * length bytes transfered
2383 * check dma done of last desc. in PPBDU mode
2384 */
2388 dma_done =
2390 UDC_DMA_IN_STS_BS);
2391 /* don't care DMA done */
2394 }
2396 /* assume all bytes transferred */
2398 }
2401 /* complete req */
2404 /* further request available ? */
2406 /* disable interrupt */
2412 }
2414 }
2415 }
2416 }
2419 }
2420 /*
2421 * status reg has IN bit set and TDC not set (if TDC was handled,
2422 * IN must not be handled (UDC defect) ?
2423 */
2428 /* next request */
2431 /* FIFO mode */
2433 /* write fifo */
2441 /* complete req */
2443 }
2444 /* DMA */
2452 /*
2453 * unset L bit of first desc.
2454 * for chain
2455 */
2460 UDC_DMA_IN_STS_L);
2461 }
2463 /* write desc pointer */
2466 /* set HOST READY */
2470 UDC_DMA_IN_STS_BS_HOST_READY,
2471 UDC_DMA_IN_STS_BS);
2473 /* set poll demand bit */
2477 }
2478 }
2480 }
2481 }
2482 /* clear status bits */
2485 finished:
2488 }
2490 /* Interrupt handler for Control OUT traffic */
2494 {
2496 u32 tmp;
2498 u32 count;
2505 /* clear irq */
2509 /* check BNA and clear if set */
2517 }
2519 /* type of data: SETUP or DATA 0 bytes */
2523 /* setup data */
2530 /* set NAK for EP0_IN */
2535 /* get setup data */
2538 /* clear OUT bits in ep status */
2546 /* set HOST READY */
2548 UDC_DMA_STP_STS_BS_HOST_READY;
2550 /* read fifo */
2552 }
2554 /* determine direction of control data */
2557 /* enable RDE */
2562 /*
2563 * implant BNA dummy descriptor to allow RXFIFO opening
2564 * by RDE
2565 */
2567 /* write desc pointer */
2571 }
2575 /*
2576 * setup timer for enabling RDE (to not enable
2577 * RXFIFO DMA for data to early)
2578 */
2585 }
2586 }
2587 }
2589 /*
2590 * mass storage reset must be processed here because
2591 * next packet may be a CLEAR_FEATURE HALT which would not
2592 * clear the stall bit when no STALL handshake was received
2593 * before (autostall can cause this)
2594 */
2598 /*
2599 * clear stall bits
2600 * only one IN and OUT endpoints are handled
2601 */
2606 }
2608 /* call gadget with setup data received */
2615 /* ep0 in returns data (not zlp) on IN phase */
2617 UDC_EP0IN_MAXPACKET) {
2618 /* clear NAK by writing CNAK in EP0_IN */
2624 /* if unsupported request then stall */
2632 /* clear NAK by writing CNAK in EP0_OUT */
2639 }
2642 /* clear OUT bits in ep status */
2645 }
2647 /* data packet 0 bytes */
2649 /* clear OUT bits in ep status */
2652 /* get setup data: only 0 packet */
2654 /* no req if 0 packet, just reactivate */
2658 /* set HOST READY */
2662 UDC_DMA_OUT_STS_BS_HOST_READY,
2663 UDC_DMA_OUT_STS_BS);
2664 /* enable RDE */
2669 /* control write */
2671 /* re-program desc. pointer for possible ZLPs */
2674 /* enable RDE */
2676 }
2679 /* received number bytes */
2682 /* out data for fifo mode not working */
2685 /* 0 packet or real data ? */
2689 /* dummy read confirm */
2692 }
2693 }
2694 }
2696 /* check pending CNAKS */
2698 /* CNAk processing when rxfifo empty only */
2701 }
2702 }
2704 finished:
2706 }
2708 /* Interrupt handler for Control IN traffic */
2710 {
2712 u32 tmp;
2719 /* clear irq */
2723 /* DMA completion */
2728 /* clear TDC bit */
2732 /* status reg has IN bit set ? */
2737 /* clear IN bit */
2740 }
2743 /* halt ep0in */
2749 /* next request */
2754 /* write desc pointer */
2756 /* set HOST READY */
2760 UDC_DMA_STP_STS_BS_HOST_READY,
2761 UDC_DMA_STP_STS_BS);
2763 /* set poll demand bit */
2764 tmp =
2770 /* all bytes will be transferred */
2773 /* complete req */
2777 /* write fifo */
2780 /* lengh bytes transfered */
2788 /* complete req */
2790 }
2791 }
2793 }
2794 }
2798 /* clear IN bit */
2801 }
2802 }
2805 }
2808 /* Interrupt handler for global device events */
2812 {
2814 u32 tmp;
2815 u32 cfg;
2817 u16 i;
2818 u8 udc_csr_epix;
2820 /* SET_CONFIG irq ? */
2824 /* read config value */
2831 /* make usb request for gadget driver */
2836 /* programm the NE registers */
2841 /* ep ix in UDC CSR register space */
2845 /* OUT ep */
2847 /* ep ix in UDC CSR register space */
2849 }
2852 /* ep cfg */
2854 UDC_CSR_NE_CFG);
2855 /* write reg */
2858 /* clear stall bits */
2863 }
2864 /* call gadget zero with setup data received */
2874 /* read interface and alt setting values */
2879 /* make usb request for gadget driver */
2889 /* programm the NE registers */
2894 /* ep ix in UDC CSR register space */
2898 /* OUT ep */
2900 /* ep ix in UDC CSR register space */
2902 }
2904 /* UDC CSR reg */
2905 /* set ep values */
2907 /* ep interface */
2909 UDC_CSR_NE_INTF);
2910 /* tmp = AMD_ADDBITS(tmp, 2, UDC_CSR_NE_INTF); */
2911 /* ep alt */
2913 UDC_CSR_NE_ALT);
2914 /* write reg */
2917 /* clear stall bits */
2922 }
2924 /* call gadget zero with setup data received */
2934 /* allow soft reset when suspend occurs */
2940 /* mask not needed interrupts */
2943 /* call gadget to resume and reset configs etc. */
2948 }
2952 /* disable ep0 to empty req queue */
2956 /* soft reset when rxfifo not empty */
2961 soft_reset_after_usbreset_occured++;
2962 }
2964 /*
2965 * DMA reset to kill potential old DMA hw hang,
2966 * POLL bit is already reset by ep_init() through
2967 * disconnect()
2968 */
2974 /* put into initial config */
2977 /* enable device setup interrupts */
2980 /* enable suspend interrupt */
2994 }
3001 /* disable ep0 to empty req queue */
3005 /* link up all endpoints */
3013 }
3015 /* init ep 0 */
3018 /* enable ep0 interrupts */
3020 }
3021 /* session valid change interrupt */
3026 /* check that session is not valid to detect disconnect */
3029 /* disable suspend interrupt */
3034 /* cleanup on disconnect */
3036 }
3038 }
3041 }
3043 /* Interrupt Service Routine, see Linux Kernel Doc for parameters */
3045 {
3047 u32 reg;
3048 u16 i;
3049 u32 ep_irq;
3054 /* check for ep irq */
3062 /*
3063 * data endpoint
3064 * iterate ep's
3065 */
3071 /* clear irq status */
3074 /* irq for out ep ? */
3077 else
3079 }
3081 }
3084 /* check for dev irq */
3087 /* clear irq */
3090 }
3095 }
3097 /* Tears down device */
3099 {
3102 }
3104 /* Cleanup on device remove */
3106 {
3107 /* remove timer */
3108 stop_timer++;
3113 /* remove pollstall timer */
3114 stop_pollstall_timer++;
3120 }
3122 /* Reset all pci context */
3124 {
3129 /* gadget driver must not be registered */
3132 /* dma pool cleanup */
3137 /* cleanup DMA desc's for ep0in */
3146 }
3148 /* reset controller */
3164 }
3166 /* create dma pools on init */
3168 {
3173 /* consistent DMA mode setting ? */
3179 }
3181 /* DMA setup */
3188 }
3190 /* EP0 in dma regs = dev control regs */
3193 /* dma desc for setup data */
3200 }
3201 /* setup */
3207 }
3210 /* data: 0 packets !? */
3216 }
3220 finished:
3222 }
3224 /* Called by pci bus driver to init pci context */
3228 )
3229 {
3235 /* one udc only */
3239 }
3241 /* init */
3246 }
3248 /* pci setup */
3252 }
3255 /* PCI resource allocation */
3263 }
3271 }
3277 }
3283 }
3288 /* chip revision for Hs AMD5536 */
3294 /* init dma pools */
3299 }
3307 /* general probing */
3311 finished:
3315 }
3317 /* general probe */
3319 {
3321 u32 reg;
3324 /* mark timer as not initialized */
3328 /* device struct setup */
3338 /* udc csr registers base */
3340 /* dev registers base */
3342 /* ep registers base */
3344 /* fifo's base */
3348 /* init registers, interrupts, ... */
3363 }
3372 /* timer init */
3376 /* timer pollstall init */
3381 /* set SD */
3386 /* print dev register info */
3391 finished:
3393 }
3395 /* Initiates a remote wakeup */
3397 {
3399 u32 tmp;
3413 }
3415 /* PCI device parameters */
3417 {
3421 },
3422 {},
3423 };
3426 /* PCI functions */
3432 };
3434 /* Inits driver */
3436 {
3438 }
3441 /* Cleans driver */
3443 {
3445 }