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PRCM: OMAP3: Fix to wrongly modified omap2_clk_wait_ready
[linux-ginger.git] / drivers / i2c / busses / i2c-omap.c
blob55779f55ace5c0e8839a52265ccf26c410a1223a
1 /*
2 * TI OMAP I2C master mode driver
3 *
4 * Copyright (C) 2003 MontaVista Software, Inc.
5 * Copyright (C) 2005 Nokia Corporation
6 * Copyright (C) 2004 - 2007 Texas Instruments.
7 *
8 * Originally written by MontaVista Software, Inc.
9 * Additional contributions by:
10 * Tony Lindgren <tony@atomide.com>
11 * Imre Deak <imre.deak@nokia.com>
12 * Juha Yrjölä <juha.yrjola@nokia.com>
13 * Syed Khasim <x0khasim@ti.com>
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29
30 #include <linux/module.h>
31 #include <linux/delay.h>
32 #include <linux/i2c.h>
33 #include <linux/err.h>
34 #include <linux/interrupt.h>
35 #include <linux/completion.h>
36 #include <linux/platform_device.h>
37 #include <linux/clk.h>
38
39 #include <asm/io.h>
40
41 /* Hack to enable zero length transfers and smbus quick until clean fix
42 is available */
43 #define OMAP_HACK
44
45 /* timeout waiting for the controller to respond */
46 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
47
48 #define OMAP_I2C_REV_REG 0x00
49 #define OMAP_I2C_IE_REG 0x04
50 #define OMAP_I2C_STAT_REG 0x08
51 #define OMAP_I2C_IV_REG 0x0c
52 #define OMAP_I2C_SYSS_REG 0x10
53 #define OMAP_I2C_BUF_REG 0x14
54 #define OMAP_I2C_CNT_REG 0x18
55 #define OMAP_I2C_DATA_REG 0x1c
56 #define OMAP_I2C_SYSC_REG 0x20
57 #define OMAP_I2C_CON_REG 0x24
58 #define OMAP_I2C_OA_REG 0x28
59 #define OMAP_I2C_SA_REG 0x2c
60 #define OMAP_I2C_PSC_REG 0x30
61 #define OMAP_I2C_SCLL_REG 0x34
62 #define OMAP_I2C_SCLH_REG 0x38
63 #define OMAP_I2C_SYSTEST_REG 0x3c
64 #define OMAP_I2C_BUFSTAT_REG 0x40
65
66 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
67 #define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer draining int enable */
68 #define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer draining int enable */
69 #define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
70 #define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
71 #define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
72 #define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
73 #define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
74
75 /* I2C Status Register (OMAP_I2C_STAT): */
76 #define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
77 #define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
78 #define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
79 #define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
80 #define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
81 #define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
82 #define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */
83 #define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
84 #define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
85 #define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
86 #define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
87 #define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
88
89 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
90 #define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
91 #define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
92 #define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
93 #define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
94
95 /* I2C Configuration Register (OMAP_I2C_CON): */
96 #define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
97 #define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
98 #define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
99 #define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
100 #define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
101 #define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
102 #define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
103 #define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
104 #define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
105 #define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
106
107 /* I2C SCL time value when Master */
108 #define OMAP_I2C_SCLL_HSSCLL 8
109 #define OMAP_I2C_SCLH_HSSCLH 8
110
111 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
112 #ifdef DEBUG
113 #define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
114 #define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
115 #define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
116 #define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
117 #define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
118 #define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
119 #define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
120 #define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
121 #endif
122
123 /* I2C System Status register (OMAP_I2C_SYSS): */
124 #define OMAP_I2C_SYSS_RDONE (1 << 0) /* Reset Done */
125
126 /* I2C System Configuration Register (OMAP_I2C_SYSC): */
127 #define OMAP_I2C_SYSC_SRST (1 << 1) /* Soft Reset */
128
129 struct omap_i2c_dev {
130 struct device *dev;
131 void __iomem *base; /* virtual */
132 int irq;
133 struct clk *iclk; /* Interface clock */
134 struct clk *fclk; /* Functional clock */
135 struct completion cmd_complete;
136 struct resource *ioarea;
137 u32 speed; /* Speed of bus in Khz */
138 u16 cmd_err;
139 u8 *buf;
140 size_t buf_len;
141 struct i2c_adapter adapter;
142 u8 fifo_size; /* use as flag and value
143 * fifo_size==0 implies no fifo
144 * if set, should be trsh+1
145 */
146 unsigned rev1:1;
147 unsigned b_hw:1; /* bad h/w fixes */
148 unsigned idle:1;
149 u16 iestate; /* Saved interrupt register */
150 };
151
152 static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
153 int reg, u16 val)
154 {
155 __raw_writew(val, i2c_dev->base + reg);
156 }
157
158 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
159 {
160 return __raw_readw(i2c_dev->base + reg);
161 }
162
163 static int omap_i2c_get_clocks(struct omap_i2c_dev *dev)
164 {
165 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
166 dev->iclk = clk_get(dev->dev, "i2c_ick");
167 if (IS_ERR(dev->iclk)) {
168 dev->iclk = NULL;
169 return -ENODEV;
170 }
171 }
172 /* For I2C operations on 2430 we need 96Mhz clock */
173 if (cpu_is_omap2430()) {
174 dev->fclk = clk_get(dev->dev, "i2chs_fck");
175 if (IS_ERR(dev->fclk)) {
176 if (dev->iclk != NULL) {
177 clk_put(dev->iclk);
178 dev->iclk = NULL;
179 }
180 dev->fclk = NULL;
181 return -ENODEV;
182 }
183 } else {
184 dev->fclk = clk_get(dev->dev, "i2c_fck");
185 if (IS_ERR(dev->fclk)) {
186 if (dev->iclk != NULL) {
187 clk_put(dev->iclk);
188 dev->iclk = NULL;
189 }
190 dev->fclk = NULL;
191 return -ENODEV;
192 }
193 }
194 return 0;
195 }
196
197 static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
198 {
199 clk_put(dev->fclk);
200 dev->fclk = NULL;
201 if (dev->iclk != NULL) {
202 clk_put(dev->iclk);
203 dev->iclk = NULL;
204 }
205 }
206
207 static void omap_i2c_unidle(struct omap_i2c_dev *dev)
208 {
209 if (dev->iclk != NULL)
210 clk_enable(dev->iclk);
211 clk_enable(dev->fclk);
212 if (dev->iestate)
213 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
214 dev->idle = 0;
215 }
216
217 static void omap_i2c_idle(struct omap_i2c_dev *dev)
218 {
219 u16 iv;
220
221 dev->idle = 1;
222 dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
223 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
224 if (dev->rev1)
225 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
226 else
227 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
228 clk_disable(dev->fclk);
229 if (dev->iclk != NULL)
230 clk_disable(dev->iclk);
231 }
232
233 static int omap_i2c_init(struct omap_i2c_dev *dev)
234 {
235 u16 psc = 0, scll = 0, sclh = 0;
236 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
237 unsigned long fclk_rate = 12000000;
238 unsigned long timeout;
239 unsigned long internal_clk = 0;
240
241 if (!dev->rev1) {
242 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, OMAP_I2C_SYSC_SRST);
243 /* For some reason we need to set the EN bit before the
244 * reset done bit gets set. */
245 timeout = jiffies + OMAP_I2C_TIMEOUT;
246 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
247 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
248 OMAP_I2C_SYSS_RDONE)) {
249 if (time_after(jiffies, timeout)) {
250 dev_warn(dev->dev, "timeout waiting "
251 "for controller reset\n");
252 return -ETIMEDOUT;
253 }
254 msleep(1);
255 }
256 }
257 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
258
259 if (cpu_class_is_omap1()) {
260 struct clk *armxor_ck;
261
262 armxor_ck = clk_get(NULL, "armxor_ck");
263 if (IS_ERR(armxor_ck))
264 dev_warn(dev->dev, "Could not get armxor_ck\n");
265 else {
266 fclk_rate = clk_get_rate(armxor_ck);
267 clk_put(armxor_ck);
268 }
269 /* TRM for 5912 says the I2C clock must be prescaled to be
270 * between 7 - 12 MHz. The XOR input clock is typically
271 * 12, 13 or 19.2 MHz. So we should have code that produces:
272 *
273 * XOR MHz Divider Prescaler
274 * 12 1 0
275 * 13 2 1
276 * 19.2 2 1
277 */
278 if (fclk_rate > 12000000)
279 psc = fclk_rate / 12000000;
280 }
281
282 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
283
284 /* HSI2C controller internal clk rate should be 19.2 Mhz */
285 internal_clk = 19200;
286 fclk_rate = clk_get_rate(dev->fclk) / 1000;
287
288 /* Compute prescaler divisor */
289 psc = fclk_rate / internal_clk;
290 psc = psc - 1;
291
292 /* If configured for High Speed */
293 if (dev->speed > 400) {
294 /* For first phase of HS mode */
295 fsscll = internal_clk / (400 * 2) - 6;
296 fssclh = internal_clk / (400 * 2) - 6;
297
298 /* For second phase of HS mode */
299 hsscll = fclk_rate / (dev->speed * 2) - 6;
300 hssclh = fclk_rate / (dev->speed * 2) - 6;
301 } else {
302 /* To handle F/S modes */
303 fsscll = internal_clk / (dev->speed * 2) - 6;
304 fssclh = internal_clk / (dev->speed * 2) - 6;
305 }
306 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
307 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
308 } else {
309 /* Program desired operating rate */
310 fclk_rate /= (psc + 1) * 1000;
311 if (psc > 2)
312 psc = 2;
313 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
314 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
315 }
316
317 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
318 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
319
320 /* SCL low and high time values */
321 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
322 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
323
324 if (dev->fifo_size)
325 /* Note: setup required fifo size - 1 */
326 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG,
327 (dev->fifo_size - 1) << 8 | /* RTRSH */
328 OMAP_I2C_BUF_RXFIF_CLR |
329 (dev->fifo_size - 1) | /* XTRSH */
330 OMAP_I2C_BUF_TXFIF_CLR);
331
332 /* Take the I2C module out of reset: */
333 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
334
335 /* Enable interrupts */
336 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG,
337 (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
338 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
339 OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
340 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0));
341 return 0;
342 }
343
344 /*
345 * Waiting on Bus Busy
346 */
347 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
348 {
349 unsigned long timeout;
350
351 timeout = jiffies + OMAP_I2C_TIMEOUT;
352 while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
353 if (time_after(jiffies, timeout)) {
354 dev_warn(dev->dev, "timeout waiting for bus ready\n");
355 return -ETIMEDOUT;
356 }
357 msleep(1);
358 }
359
360 return 0;
361 }
362
363 /*
364 * Low level master read/write transaction.
365 */
366 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
367 struct i2c_msg *msg, int stop)
368 {
369 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
370 #ifdef OMAP_HACK
371 u8 zero_byte = 0;
372 #endif
373 int r;
374 u16 w;
375
376 dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
377 msg->addr, msg->len, msg->flags, stop);
378
379 #ifndef OMAP_HACK
380 if (msg->len == 0)
381 return -EINVAL;
382
383 omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
384
385 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
386 dev->buf = msg->buf;
387 dev->buf_len = msg->len;
388
389 #else
390
391 omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
392 /* REVISIT: Remove this hack when we can get I2C chips from board-*.c
393 * files
394 * Sigh, seems we can't do zero length transactions. Thus, we
395 * can't probe for devices w/o actually sending/receiving at least
396 * a single byte. So we'll set count to 1 for the zero length
397 * transaction case and hope we don't cause grief for some
398 * arbitrary device due to random byte write/read during
399 * probes.
400 */
401 if (msg->len == 0) {
402 dev->buf = &zero_byte;
403 dev->buf_len = 1;
404 } else {
405 dev->buf = msg->buf;
406 dev->buf_len = msg->len;
407 }
408 #endif
409
410 omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
411
412 /* Clear the FIFO Buffers */
413 w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
414 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
415 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
416
417 init_completion(&dev->cmd_complete);
418 dev->cmd_err = 0;
419
420 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
421
422 /* High speed configuration */
423 if (dev->speed > 400)
424 w |= OMAP_I2C_CON_OPMODE_HS;
425
426 if (msg->flags & I2C_M_TEN)
427 w |= OMAP_I2C_CON_XA;
428 if (!(msg->flags & I2C_M_RD))
429 w |= OMAP_I2C_CON_TRX;
430
431 if (!dev->b_hw && stop)
432 w |= OMAP_I2C_CON_STP;
433
434 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
435
436 if (dev->b_hw && stop) {
437 /* H/w behavior: dont write stt and stp together.. */
438 while (omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) & OMAP_I2C_CON_STT) {
439 /* Dont do anything - this will come in a couple of loops at max*/
440 }
441 w |= OMAP_I2C_CON_STP;
442 w &= ~OMAP_I2C_CON_STT;
443 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
444 }
445 r = wait_for_completion_timeout(&dev->cmd_complete,
446 OMAP_I2C_TIMEOUT);
447 dev->buf_len = 0;
448 if (r < 0)
449 return r;
450 if (r == 0) {
451 dev_err(dev->dev, "controller timed out\n");
452 omap_i2c_init(dev);
453 return -ETIMEDOUT;
454 }
455
456 if (likely(!dev->cmd_err))
457 return 0;
458
459 /* We have an error */
460 if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
461 OMAP_I2C_STAT_XUDF)) {
462 omap_i2c_init(dev);
463 return -EIO;
464 }
465
466 if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
467 if (msg->flags & I2C_M_IGNORE_NAK)
468 return 0;
469 if (stop) {
470 w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
471 w |= OMAP_I2C_CON_STP;
472 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
473 }
474 return -EREMOTEIO;
475 }
476 return -EIO;
477 }
478
479
480 /*
481 * Prepare controller for a transaction and call omap_i2c_xfer_msg
482 * to do the work during IRQ processing.
483 */
484 static int
485 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
486 {
487 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
488 int i;
489 int r;
490
491 omap_i2c_unidle(dev);
492
493 if ((r = omap_i2c_wait_for_bb(dev)) < 0)
494 goto out;
495
496 for (i = 0; i < num; i++) {
497 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
498 if (r != 0)
499 break;
500 }
501
502 if (r == 0)
503 r = num;
504 out:
505 omap_i2c_idle(dev);
506 return r;
507 }
508
509 static u32
510 omap_i2c_func(struct i2c_adapter *adap)
511 {
512 #ifndef OMAP_HACK
513 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
514 #else
515 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
516 #endif
517 }
518
519 static inline void
520 omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
521 {
522 dev->cmd_err |= err;
523 complete(&dev->cmd_complete);
524 }
525
526 static inline void
527 omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
528 {
529 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
530 }
531
532 static irqreturn_t
533 omap_i2c_rev1_isr(int this_irq, void *dev_id)
534 {
535 struct omap_i2c_dev *dev = dev_id;
536 u16 iv, w;
537
538 if (dev->idle)
539 return IRQ_NONE;
540
541 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
542 switch (iv) {
543 case 0x00: /* None */
544 break;
545 case 0x01: /* Arbitration lost */
546 dev_err(dev->dev, "Arbitration lost\n");
547 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
548 break;
549 case 0x02: /* No acknowledgement */
550 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
551 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
552 break;
553 case 0x03: /* Register access ready */
554 omap_i2c_complete_cmd(dev, 0);
555 break;
556 case 0x04: /* Receive data ready */
557 if (dev->buf_len) {
558 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
559 *dev->buf++ = w;
560 dev->buf_len--;
561 if (dev->buf_len) {
562 *dev->buf++ = w >> 8;
563 dev->buf_len--;
564 }
565 } else
566 dev_err(dev->dev, "RRDY IRQ while no data requested\n");
567 break;
568 case 0x05: /* Transmit data ready */
569 if (dev->buf_len) {
570 w = *dev->buf++;
571 dev->buf_len--;
572 if (dev->buf_len) {
573 w |= *dev->buf++ << 8;
574 dev->buf_len--;
575 }
576 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
577 } else
578 dev_err(dev->dev, "XRDY IRQ while no data to send\n");
579 break;
580 default:
581 return IRQ_NONE;
582 }
583
584 return IRQ_HANDLED;
585 }
586
587 static irqreturn_t
588 omap_i2c_isr(int this_irq, void *dev_id)
589 {
590 struct omap_i2c_dev *dev = dev_id;
591 u16 bits;
592 u16 stat, w;
593 int err, count = 0;
594
595 if (dev->idle)
596 return IRQ_NONE;
597
598 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
599 while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
600 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
601 if (count++ == 100) {
602 dev_warn(dev->dev, "Too much work in one IRQ\n");
603 break;
604 }
605
606 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
607
608 err = 0;
609 if (stat & OMAP_I2C_STAT_NACK) {
610 err |= OMAP_I2C_STAT_NACK;
611 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
612 OMAP_I2C_CON_STP);
613 }
614 if (stat & OMAP_I2C_STAT_AL) {
615 dev_err(dev->dev, "Arbitration lost\n");
616 err |= OMAP_I2C_STAT_AL;
617 }
618 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
619 OMAP_I2C_STAT_AL))
620 omap_i2c_complete_cmd(dev, err);
621 if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
622 u8 num_bytes = 1;
623 if (dev->fifo_size) {
624 num_bytes = (stat & OMAP_I2C_STAT_RRDY) ? dev->fifo_size :
625 omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG);
626 }
627 while (num_bytes) {
628 num_bytes--;
629 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
630 if (dev->buf_len) {
631 *dev->buf++ = w;
632 dev->buf_len--;
633 /* Data reg from 2430 is 8 bit wide */
634 if (!cpu_is_omap2430() &&
635 !cpu_is_omap34xx()) {
636 if (dev->buf_len) {
637 *dev->buf++ = w >> 8;
638 dev->buf_len--;
639 }
640 }
641 } else {
642 if (stat & OMAP_I2C_STAT_RRDY)
643 dev_err(dev->dev, "RRDY IRQ while no data "
644 "requested\n");
645 if (stat & OMAP_I2C_STAT_RDR)
646 dev_err(dev->dev, "RDR IRQ while no data "
647 "requested\n");
648 break;
649 }
650 }
651 omap_i2c_ack_stat(dev, stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
652 }
653 if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
654 u8 num_bytes = 1;
655 if (dev->fifo_size) {
656 num_bytes = (stat & OMAP_I2C_STAT_XRDY) ? dev->fifo_size :
657 omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG);
658 }
659 while (num_bytes) {
660 num_bytes--;
661 w = 0;
662 if (dev->buf_len) {
663 w = *dev->buf++;
664 dev->buf_len--;
665 /* Data reg from 2430 is 8 bit wide */
666 if (!cpu_is_omap2430() &&
667 !cpu_is_omap34xx()) {
668 if (dev->buf_len) {
669 w |= *dev->buf++ << 8;
670 dev->buf_len--;
671 }
672 }
673 } else {
674 if (stat & OMAP_I2C_STAT_XRDY)
675 dev_err(dev->dev, "XRDY IRQ while no "
676 "data to send\n");
677 if (stat & OMAP_I2C_STAT_XDR)
678 dev_err(dev->dev, "XDR IRQ while no "
679 "data to send\n");
680 break;
681 }
682 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
683 }
684 omap_i2c_ack_stat(dev, stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
685 }
686 if (stat & OMAP_I2C_STAT_ROVR) {
687 dev_err(dev->dev, "Receive overrun\n");
688 dev->cmd_err |= OMAP_I2C_STAT_ROVR;
689 }
690 if (stat & OMAP_I2C_STAT_XUDF) {
691 dev_err(dev->dev, "Transmit overflow\n");
692 dev->cmd_err |= OMAP_I2C_STAT_XUDF;
693 }
694 }
695
696 return count ? IRQ_HANDLED : IRQ_NONE;
697 }
698
699 static const struct i2c_algorithm omap_i2c_algo = {
700 .master_xfer = omap_i2c_xfer,
701 .functionality = omap_i2c_func,
702 };
703
704 static int
705 omap_i2c_probe(struct platform_device *pdev)
706 {
707 struct omap_i2c_dev *dev;
708 struct i2c_adapter *adap;
709 struct resource *mem, *irq, *ioarea;
710 int r;
711 u32 *speed = NULL;
712
713 /* NOTE: driver uses the static register mapping */
714 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
715 if (!mem) {
716 dev_err(&pdev->dev, "no mem resource?\n");
717 return -ENODEV;
718 }
719 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
720 if (!irq) {
721 dev_err(&pdev->dev, "no irq resource?\n");
722 return -ENODEV;
723 }
724
725 ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
726 pdev->name);
727 if (!ioarea) {
728 dev_err(&pdev->dev, "I2C region already claimed\n");
729 return -EBUSY;
730 }
731
732 dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
733 if (!dev) {
734 r = -ENOMEM;
735 goto err_release_region;
736 }
737
738 if (pdev->dev.platform_data != NULL)
739 speed = (u32 *) pdev->dev.platform_data;
740 else
741 *speed = 100; /* Defualt speed */
742
743 dev->speed = *speed;
744 dev->dev = &pdev->dev;
745 dev->irq = irq->start;
746 dev->base = (void __iomem *) IO_ADDRESS(mem->start);
747 platform_set_drvdata(pdev, dev);
748
749 if ((r = omap_i2c_get_clocks(dev)) != 0)
750 goto err_free_mem;
751
752 omap_i2c_unidle(dev);
753
754 if (cpu_is_omap15xx())
755 dev->rev1 = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) < 0x20;
756
757 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
758 /* Set up the fifo size - Get total size */
759 dev->fifo_size = 0x8 <<
760 ((omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3);
761 /*
762 * Set up notification threshold as half the total available size
763 * This is to ensure that we can handle the status on int call back
764 * latencies
765 */
766 dev->fifo_size = (dev->fifo_size / 2);
767 dev->b_hw = 1; /* Enable hardware fixes */
768 }
769
770 /* reset ASAP, clearing any IRQs */
771 omap_i2c_init(dev);
772
773 r = request_irq(dev->irq, dev->rev1 ? omap_i2c_rev1_isr : omap_i2c_isr,
774 0, pdev->name, dev);
775
776 if (r) {
777 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
778 goto err_unuse_clocks;
779 }
780 r = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
781 dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
782 pdev->id, r >> 4, r & 0xf, dev->speed);
783
784 adap = &dev->adapter;
785 i2c_set_adapdata(adap, dev);
786 adap->owner = THIS_MODULE;
787 adap->class = I2C_CLASS_HWMON;
788 strncpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
789 adap->algo = &omap_i2c_algo;
790 adap->dev.parent = &pdev->dev;
791
792 /* i2c device drivers may be active on return from add_adapter() */
793 adap->nr = pdev->id;
794 r = i2c_add_numbered_adapter(adap);
795 if (r) {
796 dev_err(dev->dev, "failure adding adapter\n");
797 goto err_free_irq;
798 }
799
800 omap_i2c_idle(dev);
801
802 return 0;
803
804 err_free_irq:
805 free_irq(dev->irq, dev);
806 err_unuse_clocks:
807 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
808 omap_i2c_idle(dev);
809 omap_i2c_put_clocks(dev);
810 err_free_mem:
811 platform_set_drvdata(pdev, NULL);
812 kfree(dev);
813 err_release_region:
814 release_mem_region(mem->start, (mem->end - mem->start) + 1);
815
816 return r;
817 }
818
819 static int
820 omap_i2c_remove(struct platform_device *pdev)
821 {
822 struct omap_i2c_dev *dev = platform_get_drvdata(pdev);
823 struct resource *mem;
824
825 platform_set_drvdata(pdev, NULL);
826
827 free_irq(dev->irq, dev);
828 i2c_del_adapter(&dev->adapter);
829 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
830 omap_i2c_put_clocks(dev);
831 kfree(dev);
832 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
833 release_mem_region(mem->start, (mem->end - mem->start) + 1);
834 return 0;
835 }
836
837 static struct platform_driver omap_i2c_driver = {
838 .probe = omap_i2c_probe,
839 .remove = omap_i2c_remove,
840 .driver = {
841 .name = "i2c_omap",
842 .owner = THIS_MODULE,
843 },
844 };
845
846 /* I2C may be needed to bring up other drivers */
847 static int __init
848 omap_i2c_init_driver(void)
849 {
850 return platform_driver_register(&omap_i2c_driver);
851 }
852 subsys_initcall(omap_i2c_init_driver);
853
854 static void __exit omap_i2c_exit_driver(void)
855 {
856 platform_driver_unregister(&omap_i2c_driver);
857 }
858 module_exit(omap_i2c_exit_driver);
859
860 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
861 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
862 MODULE_LICENSE("GPL");
863 MODULE_ALIAS("platform:i2c_omap");
Linux for Ginger Game Console