sound/soc/omap/omap-mcbsp.c

   1 /*
   2  * omap-mcbsp.c  --  OMAP ALSA SoC DAI driver using McBSP port
   3  *
   4  * Copyright (C) 2008 Nokia Corporation
   5  *
   6  * Contact: Jarkko Nikula <jarkko.nikula@nokia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but
  13  * WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20  * 02110-1301 USA
  21  *
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/module.h>
  26 #include <linux/device.h>
  27 #include <sound/core.h>
  28 #include <sound/pcm.h>
  29 #include <sound/pcm_params.h>
  30 #include <sound/initval.h>
  31 #include <sound/soc.h>
  32
  33 #include <asm/arch/control.h>
  34 #include <asm/arch/dma.h>
  35 #include <asm/arch/mcbsp.h>
  36 #include "omap-mcbsp.h"
  37 #include "omap-pcm.h"
  38
  39 #define OMAP_MCBSP_RATES        (SNDRV_PCM_RATE_44100 | \
  40                                  SNDRV_PCM_RATE_48000 | \
  41                                  SNDRV_PCM_RATE_KNOT)
  42
  43 struct omap_mcbsp_data {
  44         unsigned int                    bus_id;
  45         struct omap_mcbsp_reg_cfg       regs;
  46         /*
  47          * Flags indicating is the bus already activated and configured by
  48          * another substream
  49          */
  50         int                             active;
  51         int                             configured;
  52 };
  53
  54 #define to_mcbsp(priv)  container_of((priv), struct omap_mcbsp_data, bus_id)
  55
  56 static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];
  57
  58 /*
  59  * Stream DMA parameters. DMA request line and port address are set runtime
  60  * since they are different between OMAP1 and later OMAPs
  61  */
  62 static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2] = {
  63 {
  64         { .name         = "I2S PCM Stereo out", },
  65         { .name         = "I2S PCM Stereo in", },
  66 },
  67 };
  68
  69 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
  70 static const int omap1_dma_reqs[][2] = {
  71         { OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX },
  72         { OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX },
  73         { OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX },
  74 };
  75 static const unsigned long omap1_mcbsp_port[][2] = {
  76         { OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
  77           OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
  78         { OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
  79           OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
  80         { OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1,
  81           OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 },
  82 };
  83 #else
  84 static const int omap1_dma_reqs[][2] = {};
  85 static const unsigned long omap1_mcbsp_port[][2] = {};
  86 #endif
  87 #if defined(CONFIG_ARCH_OMAP2420)
  88 static const int omap2420_dma_reqs[][2] = {
  89         { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
  90         { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
  91 };
  92 static const unsigned long omap2420_mcbsp_port[][2] = {
  93         { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
  94           OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
  95         { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
  96           OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
  97 };
  98 #else
  99 static const int omap2420_dma_reqs[][2] = {};
 100 static const unsigned long omap2420_mcbsp_port[][2] = {};
 101 #endif
 102
 103 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream)
 104 {
 105         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 106         struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
 107         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 108         int err = 0;
 109
 110         if (!cpu_dai->active)
 111                 err = omap_mcbsp_request(mcbsp_data->bus_id);
 112
 113         return err;
 114 }
 115
 116 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream)
 117 {
 118         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 119         struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
 120         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 121
 122         if (!cpu_dai->active) {
 123                 omap_mcbsp_free(mcbsp_data->bus_id);
 124                 mcbsp_data->configured = 0;
 125         }
 126 }
 127
 128 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd)
 129 {
 130         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 131         struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
 132         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 133         int err = 0;
 134
 135         switch (cmd) {
 136         case SNDRV_PCM_TRIGGER_START:
 137         case SNDRV_PCM_TRIGGER_RESUME:
 138         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 139                 if (!mcbsp_data->active++)
 140                         omap_mcbsp_start(mcbsp_data->bus_id);
 141                 break;
 142
 143         case SNDRV_PCM_TRIGGER_STOP:
 144         case SNDRV_PCM_TRIGGER_SUSPEND:
 145         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 146                 if (!--mcbsp_data->active)
 147                         omap_mcbsp_stop(mcbsp_data->bus_id);
 148                 break;
 149         default:
 150                 err = -EINVAL;
 151         }
 152
 153         return err;
 154 }
 155
 156 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
 157                                     struct snd_pcm_hw_params *params)
 158 {
 159         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 160         struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
 161         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 162         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 163         int dma, bus_id = mcbsp_data->bus_id, id = cpu_dai->id;
 164         unsigned long port;
 165
 166         if (cpu_class_is_omap1()) {
 167                 dma = omap1_dma_reqs[bus_id][substream->stream];
 168                 port = omap1_mcbsp_port[bus_id][substream->stream];
 169         } else if (cpu_is_omap2420()) {
 170                 dma = omap2420_dma_reqs[bus_id][substream->stream];
 171                 port = omap2420_mcbsp_port[bus_id][substream->stream];
 172         } else {
 173                 /*
 174                  * TODO: Add support for 2430 and 3430
 175                  */
 176                 return -ENODEV;
 177         }
 178         omap_mcbsp_dai_dma_params[id][substream->stream].dma_req = dma;
 179         omap_mcbsp_dai_dma_params[id][substream->stream].port_addr = port;
 180         cpu_dai->dma_data = &omap_mcbsp_dai_dma_params[id][substream->stream];
 181
 182         if (mcbsp_data->configured) {
 183                 /* McBSP already configured by another stream */
 184                 return 0;
 185         }
 186
 187         switch (params_channels(params)) {
 188         case 2:
 189                 /* Set 1 word per (McBPSP) frame and use dual-phase frames */
 190                 regs->rcr2      |= RFRLEN2(1 - 1) | RPHASE;
 191                 regs->rcr1      |= RFRLEN1(1 - 1);
 192                 regs->xcr2      |= XFRLEN2(1 - 1) | XPHASE;
 193                 regs->xcr1      |= XFRLEN1(1 - 1);
 194                 break;
 195         default:
 196                 /* Unsupported number of channels */
 197                 return -EINVAL;
 198         }
 199
 200         switch (params_format(params)) {
 201         case SNDRV_PCM_FORMAT_S16_LE:
 202                 /* Set word lengths */
 203                 regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_16);
 204                 regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_16);
 205                 regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_16);
 206                 regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_16);
 207                 /* Set FS period and length in terms of bit clock periods */
 208                 regs->srgr2     |= FPER(16 * 2 - 1);
 209                 regs->srgr1     |= FWID(16 - 1);
 210                 break;
 211         default:
 212                 /* Unsupported PCM format */
 213                 return -EINVAL;
 214         }
 215
 216         omap_mcbsp_config(bus_id, &mcbsp_data->regs);
 217         mcbsp_data->configured = 1;
 218
 219         return 0;
 220 }
 221
 222 /*
 223  * This must be called before _set_clkdiv and _set_sysclk since McBSP register
 224  * cache is initialized here
 225  */
 226 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_cpu_dai *cpu_dai,
 227                                       unsigned int fmt)
 228 {
 229         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 230         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 231
 232         if (mcbsp_data->configured)
 233                 return 0;
 234
 235         memset(regs, 0, sizeof(*regs));
 236         /* Generic McBSP register settings */
 237         regs->spcr2     |= XINTM(3) | FREE;
 238         regs->spcr1     |= RINTM(3);
 239         regs->rcr2      |= RFIG;
 240         regs->xcr2      |= XFIG;
 241
 242         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 243         case SND_SOC_DAIFMT_I2S:
 244                 /* 1-bit data delay */
 245                 regs->rcr2      |= RDATDLY(1);
 246                 regs->xcr2      |= XDATDLY(1);
 247                 break;
 248         default:
 249                 /* Unsupported data format */
 250                 return -EINVAL;
 251         }
 252
 253         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 254         case SND_SOC_DAIFMT_CBS_CFS:
 255                 /* McBSP master. Set FS and bit clocks as outputs */
 256                 regs->pcr0      |= FSXM | FSRM |
 257                                    CLKXM | CLKRM;
 258                 /* Sample rate generator drives the FS */
 259                 regs->srgr2     |= FSGM;
 260                 break;
 261         case SND_SOC_DAIFMT_CBM_CFM:
 262                 /* McBSP slave */
 263                 break;
 264         default:
 265                 /* Unsupported master/slave configuration */
 266                 return -EINVAL;
 267         }
 268
 269         /* Set bit clock (CLKX/CLKR) and FS polarities */
 270         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 271         case SND_SOC_DAIFMT_NB_NF:
 272                 /*
 273                  * Normal BCLK + FS.
 274                  * FS active low. TX data driven on falling edge of bit clock
 275                  * and RX data sampled on rising edge of bit clock.
 276                  */
 277                 regs->pcr0      |= FSXP | FSRP |
 278                                    CLKXP | CLKRP;
 279                 break;
 280         case SND_SOC_DAIFMT_NB_IF:
 281                 regs->pcr0      |= CLKXP | CLKRP;
 282                 break;
 283         case SND_SOC_DAIFMT_IB_NF:
 284                 regs->pcr0      |= FSXP | FSRP;
 285                 break;
 286         case SND_SOC_DAIFMT_IB_IF:
 287                 break;
 288         default:
 289                 return -EINVAL;
 290         }
 291
 292         return 0;
 293 }
 294
 295 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_cpu_dai *cpu_dai,
 296                                      int div_id, int div)
 297 {
 298         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 299         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 300
 301         if (div_id != OMAP_MCBSP_CLKGDV)
 302                 return -ENODEV;
 303
 304         regs->srgr1     |= CLKGDV(div - 1);
 305
 306         return 0;
 307 }
 308
 309 static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data *mcbsp_data,
 310                                        int clk_id)
 311 {
 312         int sel_bit;
 313         u16 reg;
 314
 315         if (cpu_class_is_omap1()) {
 316                 /* OMAP1's can use only external source clock */
 317                 if (unlikely(clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK))
 318                         return -EINVAL;
 319                 else
 320                         return 0;
 321         }
 322
 323         switch (mcbsp_data->bus_id) {
 324         case 0:
 325                 reg = OMAP2_CONTROL_DEVCONF0;
 326                 sel_bit = 2;
 327                 break;
 328         case 1:
 329                 reg = OMAP2_CONTROL_DEVCONF0;
 330                 sel_bit = 6;
 331                 break;
 332         /* TODO: Support for ports 3 - 5 in OMAP2430 and OMAP34xx */
 333         default:
 334                 return -EINVAL;
 335         }
 336
 337         if (cpu_class_is_omap2()) {
 338                 if (clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK) {
 339                         omap_ctrl_writel(omap_ctrl_readl(reg) &
 340                                          ~(1 << sel_bit), reg);
 341                 } else {
 342                         omap_ctrl_writel(omap_ctrl_readl(reg) |
 343                                          (1 << sel_bit), reg);
 344                 }
 345         }
 346
 347         return 0;
 348 }
 349
 350 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_cpu_dai *cpu_dai,
 351                                          int clk_id, unsigned int freq,
 352                                          int dir)
 353 {
 354         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 355         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 356         int err = 0;
 357
 358         switch (clk_id) {
 359         case OMAP_MCBSP_SYSCLK_CLK:
 360                 regs->srgr2     |= CLKSM;
 361                 break;
 362         case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
 363         case OMAP_MCBSP_SYSCLK_CLKS_EXT:
 364                 err = omap_mcbsp_dai_set_clks_src(mcbsp_data, clk_id);
 365                 break;
 366
 367         case OMAP_MCBSP_SYSCLK_CLKX_EXT:
 368                 regs->srgr2     |= CLKSM;
 369         case OMAP_MCBSP_SYSCLK_CLKR_EXT:
 370                 regs->pcr0      |= SCLKME;
 371                 break;
 372         default:
 373                 err = -ENODEV;
 374         }
 375
 376         return err;
 377 }
 378
 379 struct snd_soc_cpu_dai omap_mcbsp_dai[NUM_LINKS] = {
 380 {
 381         .name = "omap-mcbsp-dai",
 382         .id = 0,
 383         .type = SND_SOC_DAI_I2S,
 384         .playback = {
 385                 .channels_min = 2,
 386                 .channels_max = 2,
 387                 .rates = OMAP_MCBSP_RATES,
 388                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 389         },
 390         .capture = {
 391                 .channels_min = 2,
 392                 .channels_max = 2,
 393                 .rates = OMAP_MCBSP_RATES,
 394                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 395         },
 396         .ops = {
 397                 .startup = omap_mcbsp_dai_startup,
 398                 .shutdown = omap_mcbsp_dai_shutdown,
 399                 .trigger = omap_mcbsp_dai_trigger,
 400                 .hw_params = omap_mcbsp_dai_hw_params,
 401         },
 402         .dai_ops = {
 403                 .set_fmt = omap_mcbsp_dai_set_dai_fmt,
 404                 .set_clkdiv = omap_mcbsp_dai_set_clkdiv,
 405                 .set_sysclk = omap_mcbsp_dai_set_dai_sysclk,
 406         },
 407         .private_data = &mcbsp_data[0].bus_id,
 408 },
 409 };
 410 EXPORT_SYMBOL_GPL(omap_mcbsp_dai);
 411
 412 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@nokia.com>");
 413 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
 414 MODULE_LICENSE("GPL");