arch/sparc/kernel/sun4c_irq.c

   1 /*  sun4c_irq.c
   2  *  arch/sparc/kernel/sun4c_irq.c:
   3  *
   4  *  djhr: Hacked out of irq.c into a CPU dependent version.
   5  *
   6  *  Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   7  *  Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
   8  *  Copyright (C) 1995 Pete A. Zaitcev (zaitcev@yahoo.com)
   9  *  Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk)
  10  */
  11
  12 #include <linux/errno.h>
  13 #include <linux/linkage.h>
  14 #include <linux/kernel_stat.h>
  15 #include <linux/signal.h>
  16 #include <linux/sched.h>
  17 #include <linux/ptrace.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/slab.h>
  20 #include <linux/init.h>
  21 #include "irq.h"
  22
  23 #include <asm/ptrace.h>
  24 #include <asm/processor.h>
  25 #include <asm/system.h>
  26 #include <asm/psr.h>
  27 #include <asm/vaddrs.h>
  28 #include <asm/timer.h>
  29 #include <asm/openprom.h>
  30 #include <asm/oplib.h>
  31 #include <asm/traps.h>
  32 #include <asm/irq.h>
  33 #include <asm/io.h>
  34 #include <asm/sun4paddr.h>
  35 #include <asm/idprom.h>
  36 #include <asm/machines.h>
  37 #include <asm/sbus.h>
  38
  39 #if 0
  40 static struct resource sun4c_timer_eb = { "sun4c_timer" };
  41 static struct resource sun4c_intr_eb = { "sun4c_intr" };
  42 #endif
  43
  44 /*
  45  * Bit field defines for the interrupt registers on various
  46  * Sparc machines.
  47  */
  48
  49 /* The sun4c interrupt register. */
  50 #define SUN4C_INT_ENABLE  0x01     /* Allow interrupts. */
  51 #define SUN4C_INT_E14     0x80     /* Enable level 14 IRQ. */
  52 #define SUN4C_INT_E10     0x20     /* Enable level 10 IRQ. */
  53 #define SUN4C_INT_E8      0x10     /* Enable level 8 IRQ. */
  54 #define SUN4C_INT_E6      0x08     /* Enable level 6 IRQ. */
  55 #define SUN4C_INT_E4      0x04     /* Enable level 4 IRQ. */
  56 #define SUN4C_INT_E1      0x02     /* Enable level 1 IRQ. */
  57
  58 /* Pointer to the interrupt enable byte
  59  *
  60  * Dave Redman (djhr@tadpole.co.uk)
  61  * What you may not be aware of is that entry.S requires this variable.
  62  *
  63  *  --- linux_trap_nmi_sun4c --
  64  *
  65  * so don't go making it static, like I tried. sigh.
  66  */
  67 unsigned char *interrupt_enable = NULL;
  68
  69 static int sun4c_pil_map[] = { 0, 1, 2, 3, 5, 7, 8, 9 };
  70
  71 unsigned int sun4c_sbint_to_irq(struct sbus_dev *sdev, unsigned int sbint)
  72 {
  73         if (sbint >= sizeof(sun4c_pil_map)) {
  74                 printk(KERN_ERR "%s: bogus SBINT %d\n", sdev->prom_name, sbint);
  75                 BUG();
  76         }
  77         return sun4c_pil_map[sbint];
  78 }
  79
  80 static void sun4c_disable_irq(unsigned int irq_nr)
  81 {
  82         unsigned long flags;
  83         unsigned char current_mask, new_mask;
  84
  85         local_irq_save(flags);
  86         irq_nr &= (NR_IRQS - 1);
  87         current_mask = *interrupt_enable;
  88         switch(irq_nr) {
  89         case 1:
  90                 new_mask = ((current_mask) & (~(SUN4C_INT_E1)));
  91                 break;
  92         case 8:
  93                 new_mask = ((current_mask) & (~(SUN4C_INT_E8)));
  94                 break;
  95         case 10:
  96                 new_mask = ((current_mask) & (~(SUN4C_INT_E10)));
  97                 break;
  98         case 14:
  99                 new_mask = ((current_mask) & (~(SUN4C_INT_E14)));
 100                 break;
 101         default:
 102                 local_irq_restore(flags);
 103                 return;
 104         }
 105         *interrupt_enable = new_mask;
 106         local_irq_restore(flags);
 107 }
 108
 109 static void sun4c_enable_irq(unsigned int irq_nr)
 110 {
 111         unsigned long flags;
 112         unsigned char current_mask, new_mask;
 113
 114         local_irq_save(flags);
 115         irq_nr &= (NR_IRQS - 1);
 116         current_mask = *interrupt_enable;
 117         switch(irq_nr) {
 118         case 1:
 119                 new_mask = ((current_mask) | SUN4C_INT_E1);
 120                 break;
 121         case 8:
 122                 new_mask = ((current_mask) | SUN4C_INT_E8);
 123                 break;
 124         case 10:
 125                 new_mask = ((current_mask) | SUN4C_INT_E10);
 126                 break;
 127         case 14:
 128                 new_mask = ((current_mask) | SUN4C_INT_E14);
 129                 break;
 130         default:
 131                 local_irq_restore(flags);
 132                 return;
 133         }
 134         *interrupt_enable = new_mask;
 135         local_irq_restore(flags);
 136 }
 137
 138 #define TIMER_IRQ       10    /* Also at level 14, but we ignore that one. */
 139 #define PROFILE_IRQ     14    /* Level14 ticker.. used by OBP for polling */
 140
 141 volatile struct sun4c_timer_info *sun4c_timers;
 142
 143 #ifdef CONFIG_SUN4
 144 /* This is an ugly hack to work around the
 145    current timer code, and make it work with
 146    the sun4/260 intersil
 147    */
 148 volatile struct sun4c_timer_info sun4_timer;
 149 #endif
 150
 151 static void sun4c_clear_clock_irq(void)
 152 {
 153         volatile unsigned int clear_intr;
 154 #ifdef CONFIG_SUN4
 155         if (idprom->id_machtype == (SM_SUN4 | SM_4_260))
 156           clear_intr = sun4_timer.timer_limit10;
 157         else
 158 #endif
 159         clear_intr = sun4c_timers->timer_limit10;
 160 }
 161
 162 static void sun4c_clear_profile_irq(int cpu)
 163 {
 164         /* Errm.. not sure how to do this.. */
 165 }
 166
 167 static void sun4c_load_profile_irq(int cpu, unsigned int limit)
 168 {
 169         /* Errm.. not sure how to do this.. */
 170 }
 171
 172 static void __init sun4c_init_timers(irq_handler_t counter_fn)
 173 {
 174         int irq;
 175
 176         /* Map the Timer chip, this is implemented in hardware inside
 177          * the cache chip on the sun4c.
 178          */
 179 #ifdef CONFIG_SUN4
 180         if (idprom->id_machtype == (SM_SUN4 | SM_4_260))
 181                 sun4c_timers = &sun4_timer;
 182         else
 183 #endif
 184         sun4c_timers = ioremap(SUN_TIMER_PHYSADDR,
 185             sizeof(struct sun4c_timer_info));
 186
 187         /* Have the level 10 timer tick at 100HZ.  We don't touch the
 188          * level 14 timer limit since we are letting the prom handle
 189          * them until we have a real console driver so L1-A works.
 190          */
 191         sun4c_timers->timer_limit10 = (((1000000/HZ) + 1) << 10);
 192         master_l10_counter = &sun4c_timers->cur_count10;
 193         master_l10_limit = &sun4c_timers->timer_limit10;
 194
 195         irq = request_irq(TIMER_IRQ,
 196                           counter_fn,
 197                           (IRQF_DISABLED | SA_STATIC_ALLOC),
 198                           "timer", NULL);
 199         if (irq) {
 200                 prom_printf("time_init: unable to attach IRQ%d\n",TIMER_IRQ);
 201                 prom_halt();
 202         }
 203
 204 #if 0
 205         /* This does not work on 4/330 */
 206         sun4c_enable_irq(10);
 207 #endif
 208         claim_ticker14(NULL, PROFILE_IRQ, 0);
 209 }
 210
 211 #ifdef CONFIG_SMP
 212 static void sun4c_nop(void) {}
 213 #endif
 214
 215 void __init sun4c_init_IRQ(void)
 216 {
 217         struct linux_prom_registers int_regs[2];
 218         int ie_node;
 219
 220         if (ARCH_SUN4) {
 221                 interrupt_enable = (char *)
 222                     ioremap(sun4_ie_physaddr, PAGE_SIZE);
 223         } else {
 224                 struct resource phyres;
 225
 226                 ie_node = prom_searchsiblings (prom_getchild(prom_root_node),
 227                                         "interrupt-enable");
 228                 if(ie_node == 0)
 229                         panic("Cannot find /interrupt-enable node");
 230
 231                 /* Depending on the "address" property is bad news... */
 232                 interrupt_enable = NULL;
 233                 if (prom_getproperty(ie_node, "reg", (char *) int_regs,
 234                                      sizeof(int_regs)) != -1) {
 235                         memset(&phyres, 0, sizeof(struct resource));
 236                         phyres.flags = int_regs[0].which_io;
 237                         phyres.start = int_regs[0].phys_addr;
 238                         interrupt_enable = (char *) sbus_ioremap(&phyres, 0,
 239                             int_regs[0].reg_size, "sun4c_intr");
 240                 }
 241         }
 242         if (!interrupt_enable)
 243                 panic("Cannot map interrupt_enable");
 244
 245         BTFIXUPSET_CALL(sbint_to_irq, sun4c_sbint_to_irq, BTFIXUPCALL_NORM);
 246         BTFIXUPSET_CALL(enable_irq, sun4c_enable_irq, BTFIXUPCALL_NORM);
 247         BTFIXUPSET_CALL(disable_irq, sun4c_disable_irq, BTFIXUPCALL_NORM);
 248         BTFIXUPSET_CALL(enable_pil_irq, sun4c_enable_irq, BTFIXUPCALL_NORM);
 249         BTFIXUPSET_CALL(disable_pil_irq, sun4c_disable_irq, BTFIXUPCALL_NORM);
 250         BTFIXUPSET_CALL(clear_clock_irq, sun4c_clear_clock_irq, BTFIXUPCALL_NORM);
 251         BTFIXUPSET_CALL(clear_profile_irq, sun4c_clear_profile_irq, BTFIXUPCALL_NOP);
 252         BTFIXUPSET_CALL(load_profile_irq, sun4c_load_profile_irq, BTFIXUPCALL_NOP);
 253         sparc_init_timers = sun4c_init_timers;
 254 #ifdef CONFIG_SMP
 255         BTFIXUPSET_CALL(set_cpu_int, sun4c_nop, BTFIXUPCALL_NOP);
 256         BTFIXUPSET_CALL(clear_cpu_int, sun4c_nop, BTFIXUPCALL_NOP);
 257         BTFIXUPSET_CALL(set_irq_udt, sun4c_nop, BTFIXUPCALL_NOP);
 258 #endif
 259         *interrupt_enable = (SUN4C_INT_ENABLE);
 260         /* Cannot enable interrupts until OBP ticker is disabled. */
 261 }