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OMAP3: GPIO: Enable debounce clock only when debounce is enabled v3.
[linux-ginger.git] / arch / arm / plat-omap / gpio.c
blob2d630230fcffe290d17ee623edba275880859159
1 /*
2 * linux/arch/arm/plat-omap/gpio.c
3 *
4 * Support functions for OMAP GPIO
5 *
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/sysdev.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
20 #include <linux/io.h>
21
22 #include <mach/hardware.h>
23 #include <asm/irq.h>
24 #include <mach/irqs.h>
25 #include <mach/gpio.h>
26 #include <asm/mach/irq.h>
27
28 /*
29 * OMAP1510 GPIO registers
30 */
31 #define OMAP1510_GPIO_BASE IO_ADDRESS(0xfffce000)
32 #define OMAP1510_GPIO_DATA_INPUT 0x00
33 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
34 #define OMAP1510_GPIO_DIR_CONTROL 0x08
35 #define OMAP1510_GPIO_INT_CONTROL 0x0c
36 #define OMAP1510_GPIO_INT_MASK 0x10
37 #define OMAP1510_GPIO_INT_STATUS 0x14
38 #define OMAP1510_GPIO_PIN_CONTROL 0x18
39
40 #define OMAP1510_IH_GPIO_BASE 64
41
42 /*
43 * OMAP1610 specific GPIO registers
44 */
45 #define OMAP1610_GPIO1_BASE IO_ADDRESS(0xfffbe400)
46 #define OMAP1610_GPIO2_BASE IO_ADDRESS(0xfffbec00)
47 #define OMAP1610_GPIO3_BASE IO_ADDRESS(0xfffbb400)
48 #define OMAP1610_GPIO4_BASE IO_ADDRESS(0xfffbbc00)
49 #define OMAP1610_GPIO_REVISION 0x0000
50 #define OMAP1610_GPIO_SYSCONFIG 0x0010
51 #define OMAP1610_GPIO_SYSSTATUS 0x0014
52 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
53 #define OMAP1610_GPIO_IRQENABLE1 0x001c
54 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
55 #define OMAP1610_GPIO_DATAIN 0x002c
56 #define OMAP1610_GPIO_DATAOUT 0x0030
57 #define OMAP1610_GPIO_DIRECTION 0x0034
58 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
59 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
60 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
61 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
62 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
63 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
64 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
65 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
66
67 /*
68 * OMAP730 specific GPIO registers
69 */
70 #define OMAP730_GPIO1_BASE IO_ADDRESS(0xfffbc000)
71 #define OMAP730_GPIO2_BASE IO_ADDRESS(0xfffbc800)
72 #define OMAP730_GPIO3_BASE IO_ADDRESS(0xfffbd000)
73 #define OMAP730_GPIO4_BASE IO_ADDRESS(0xfffbd800)
74 #define OMAP730_GPIO5_BASE IO_ADDRESS(0xfffbe000)
75 #define OMAP730_GPIO6_BASE IO_ADDRESS(0xfffbe800)
76 #define OMAP730_GPIO_DATA_INPUT 0x00
77 #define OMAP730_GPIO_DATA_OUTPUT 0x04
78 #define OMAP730_GPIO_DIR_CONTROL 0x08
79 #define OMAP730_GPIO_INT_CONTROL 0x0c
80 #define OMAP730_GPIO_INT_MASK 0x10
81 #define OMAP730_GPIO_INT_STATUS 0x14
82
83 /*
84 * omap24xx specific GPIO registers
85 */
86 #define OMAP242X_GPIO1_BASE IO_ADDRESS(0x48018000)
87 #define OMAP242X_GPIO2_BASE IO_ADDRESS(0x4801a000)
88 #define OMAP242X_GPIO3_BASE IO_ADDRESS(0x4801c000)
89 #define OMAP242X_GPIO4_BASE IO_ADDRESS(0x4801e000)
90
91 #define OMAP243X_GPIO1_BASE IO_ADDRESS(0x4900C000)
92 #define OMAP243X_GPIO2_BASE IO_ADDRESS(0x4900E000)
93 #define OMAP243X_GPIO3_BASE IO_ADDRESS(0x49010000)
94 #define OMAP243X_GPIO4_BASE IO_ADDRESS(0x49012000)
95 #define OMAP243X_GPIO5_BASE IO_ADDRESS(0x480B6000)
96
97 #define OMAP24XX_GPIO_REVISION 0x0000
98 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
99 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
100 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
101 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
102 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
103 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
104 #define OMAP24XX_GPIO_CTRL 0x0030
105 #define OMAP24XX_GPIO_OE 0x0034
106 #define OMAP24XX_GPIO_DATAIN 0x0038
107 #define OMAP24XX_GPIO_DATAOUT 0x003c
108 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
109 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
110 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
111 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
112 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
113 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
114 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
115 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
116 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
117 #define OMAP24XX_GPIO_SETWKUENA 0x0084
118 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
119 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
120
121 /*
122 * omap34xx specific GPIO registers
123 */
124
125 #define OMAP34XX_GPIO1_BASE IO_ADDRESS(0x48310000)
126 #define OMAP34XX_GPIO2_BASE IO_ADDRESS(0x49050000)
127 #define OMAP34XX_GPIO3_BASE IO_ADDRESS(0x49052000)
128 #define OMAP34XX_GPIO4_BASE IO_ADDRESS(0x49054000)
129 #define OMAP34XX_GPIO5_BASE IO_ADDRESS(0x49056000)
130 #define OMAP34XX_GPIO6_BASE IO_ADDRESS(0x49058000)
131
132 #define OMAP_MPUIO_VBASE IO_ADDRESS(OMAP_MPUIO_BASE)
133
134 struct gpio_bank {
135 void __iomem *base;
136 u16 irq;
137 u16 virtual_irq_start;
138 int method;
139 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
140 u32 suspend_wakeup;
141 u32 saved_wakeup;
142 #endif
143 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
144 u32 non_wakeup_gpios;
145 u32 enabled_non_wakeup_gpios;
146
147 u32 saved_datain;
148 u32 saved_fallingdetect;
149 u32 saved_risingdetect;
150 #endif
151 u32 level_mask;
152 spinlock_t lock;
153 struct gpio_chip chip;
154 struct clk *dbck;
155 };
156
157 #define METHOD_MPUIO 0
158 #define METHOD_GPIO_1510 1
159 #define METHOD_GPIO_1610 2
160 #define METHOD_GPIO_730 3
161 #define METHOD_GPIO_24XX 4
162
163 #ifdef CONFIG_ARCH_OMAP16XX
164 static struct gpio_bank gpio_bank_1610[5] = {
165 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
166 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
167 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
168 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
169 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
170 };
171 #endif
172
173 #ifdef CONFIG_ARCH_OMAP15XX
174 static struct gpio_bank gpio_bank_1510[2] = {
175 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
176 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
177 };
178 #endif
179
180 #ifdef CONFIG_ARCH_OMAP730
181 static struct gpio_bank gpio_bank_730[7] = {
182 { OMAP_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
183 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
184 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
185 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
186 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
187 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
188 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
189 };
190 #endif
191
192 #ifdef CONFIG_ARCH_OMAP24XX
193
194 static struct gpio_bank gpio_bank_242x[4] = {
195 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
196 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
197 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
198 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
199 };
200
201 static struct gpio_bank gpio_bank_243x[5] = {
202 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
203 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
204 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
205 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
206 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
207 };
208
209 #endif
210
211 #ifdef CONFIG_ARCH_OMAP34XX
212 static struct gpio_bank gpio_bank_34xx[6] = {
213 { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
214 { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
215 { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
216 { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
217 { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
218 { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
219 };
220
221 #endif
222
223 static struct gpio_bank *gpio_bank;
224 static int gpio_bank_count;
225
226 static inline struct gpio_bank *get_gpio_bank(int gpio)
227 {
228 if (cpu_is_omap15xx()) {
229 if (OMAP_GPIO_IS_MPUIO(gpio))
230 return &gpio_bank[0];
231 return &gpio_bank[1];
232 }
233 if (cpu_is_omap16xx()) {
234 if (OMAP_GPIO_IS_MPUIO(gpio))
235 return &gpio_bank[0];
236 return &gpio_bank[1 + (gpio >> 4)];
237 }
238 if (cpu_is_omap730()) {
239 if (OMAP_GPIO_IS_MPUIO(gpio))
240 return &gpio_bank[0];
241 return &gpio_bank[1 + (gpio >> 5)];
242 }
243 if (cpu_is_omap24xx())
244 return &gpio_bank[gpio >> 5];
245 if (cpu_is_omap34xx())
246 return &gpio_bank[gpio >> 5];
247 }
248
249 static inline int get_gpio_index(int gpio)
250 {
251 if (cpu_is_omap730())
252 return gpio & 0x1f;
253 if (cpu_is_omap24xx())
254 return gpio & 0x1f;
255 if (cpu_is_omap34xx())
256 return gpio & 0x1f;
257 return gpio & 0x0f;
258 }
259
260 static inline int gpio_valid(int gpio)
261 {
262 if (gpio < 0)
263 return -1;
264 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
265 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
266 return -1;
267 return 0;
268 }
269 if (cpu_is_omap15xx() && gpio < 16)
270 return 0;
271 if ((cpu_is_omap16xx()) && gpio < 64)
272 return 0;
273 if (cpu_is_omap730() && gpio < 192)
274 return 0;
275 if (cpu_is_omap24xx() && gpio < 128)
276 return 0;
277 if (cpu_is_omap34xx() && gpio < 160)
278 return 0;
279 return -1;
280 }
281
282 static int check_gpio(int gpio)
283 {
284 if (unlikely(gpio_valid(gpio)) < 0) {
285 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
286 dump_stack();
287 return -1;
288 }
289 return 0;
290 }
291
292 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
293 {
294 void __iomem *reg = bank->base;
295 u32 l;
296
297 switch (bank->method) {
298 #ifdef CONFIG_ARCH_OMAP1
299 case METHOD_MPUIO:
300 reg += OMAP_MPUIO_IO_CNTL;
301 break;
302 #endif
303 #ifdef CONFIG_ARCH_OMAP15XX
304 case METHOD_GPIO_1510:
305 reg += OMAP1510_GPIO_DIR_CONTROL;
306 break;
307 #endif
308 #ifdef CONFIG_ARCH_OMAP16XX
309 case METHOD_GPIO_1610:
310 reg += OMAP1610_GPIO_DIRECTION;
311 break;
312 #endif
313 #ifdef CONFIG_ARCH_OMAP730
314 case METHOD_GPIO_730:
315 reg += OMAP730_GPIO_DIR_CONTROL;
316 break;
317 #endif
318 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
319 case METHOD_GPIO_24XX:
320 reg += OMAP24XX_GPIO_OE;
321 break;
322 #endif
323 default:
324 WARN_ON(1);
325 return;
326 }
327 l = __raw_readl(reg);
328 if (is_input)
329 l |= 1 << gpio;
330 else
331 l &= ~(1 << gpio);
332 __raw_writel(l, reg);
333 }
334
335 void omap_set_gpio_direction(int gpio, int is_input)
336 {
337 struct gpio_bank *bank;
338 unsigned long flags;
339
340 if (check_gpio(gpio) < 0)
341 return;
342 bank = get_gpio_bank(gpio);
343 spin_lock_irqsave(&bank->lock, flags);
344 _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
345 spin_unlock_irqrestore(&bank->lock, flags);
346 }
347
348 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
349 {
350 void __iomem *reg = bank->base;
351 u32 l = 0;
352
353 switch (bank->method) {
354 #ifdef CONFIG_ARCH_OMAP1
355 case METHOD_MPUIO:
356 reg += OMAP_MPUIO_OUTPUT;
357 l = __raw_readl(reg);
358 if (enable)
359 l |= 1 << gpio;
360 else
361 l &= ~(1 << gpio);
362 break;
363 #endif
364 #ifdef CONFIG_ARCH_OMAP15XX
365 case METHOD_GPIO_1510:
366 reg += OMAP1510_GPIO_DATA_OUTPUT;
367 l = __raw_readl(reg);
368 if (enable)
369 l |= 1 << gpio;
370 else
371 l &= ~(1 << gpio);
372 break;
373 #endif
374 #ifdef CONFIG_ARCH_OMAP16XX
375 case METHOD_GPIO_1610:
376 if (enable)
377 reg += OMAP1610_GPIO_SET_DATAOUT;
378 else
379 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
380 l = 1 << gpio;
381 break;
382 #endif
383 #ifdef CONFIG_ARCH_OMAP730
384 case METHOD_GPIO_730:
385 reg += OMAP730_GPIO_DATA_OUTPUT;
386 l = __raw_readl(reg);
387 if (enable)
388 l |= 1 << gpio;
389 else
390 l &= ~(1 << gpio);
391 break;
392 #endif
393 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
394 case METHOD_GPIO_24XX:
395 if (enable)
396 reg += OMAP24XX_GPIO_SETDATAOUT;
397 else
398 reg += OMAP24XX_GPIO_CLEARDATAOUT;
399 l = 1 << gpio;
400 break;
401 #endif
402 default:
403 WARN_ON(1);
404 return;
405 }
406 __raw_writel(l, reg);
407 }
408
409 void omap_set_gpio_dataout(int gpio, int enable)
410 {
411 struct gpio_bank *bank;
412 unsigned long flags;
413
414 if (check_gpio(gpio) < 0)
415 return;
416 bank = get_gpio_bank(gpio);
417 spin_lock_irqsave(&bank->lock, flags);
418 _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
419 spin_unlock_irqrestore(&bank->lock, flags);
420 }
421
422 int omap_get_gpio_datain(int gpio)
423 {
424 struct gpio_bank *bank;
425 void __iomem *reg;
426
427 if (check_gpio(gpio) < 0)
428 return -EINVAL;
429 bank = get_gpio_bank(gpio);
430 reg = bank->base;
431 switch (bank->method) {
432 #ifdef CONFIG_ARCH_OMAP1
433 case METHOD_MPUIO:
434 reg += OMAP_MPUIO_INPUT_LATCH;
435 break;
436 #endif
437 #ifdef CONFIG_ARCH_OMAP15XX
438 case METHOD_GPIO_1510:
439 reg += OMAP1510_GPIO_DATA_INPUT;
440 break;
441 #endif
442 #ifdef CONFIG_ARCH_OMAP16XX
443 case METHOD_GPIO_1610:
444 reg += OMAP1610_GPIO_DATAIN;
445 break;
446 #endif
447 #ifdef CONFIG_ARCH_OMAP730
448 case METHOD_GPIO_730:
449 reg += OMAP730_GPIO_DATA_INPUT;
450 break;
451 #endif
452 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
453 case METHOD_GPIO_24XX:
454 reg += OMAP24XX_GPIO_DATAIN;
455 break;
456 #endif
457 default:
458 return -EINVAL;
459 }
460 return (__raw_readl(reg)
461 & (1 << get_gpio_index(gpio))) != 0;
462 }
463
464 #define MOD_REG_BIT(reg, bit_mask, set) \
465 do { \
466 int l = __raw_readl(base + reg); \
467 if (set) l |= bit_mask; \
468 else l &= ~bit_mask; \
469 __raw_writel(l, base + reg); \
470 } while(0)
471
472 void omap_set_gpio_debounce(int gpio, int enable)
473 {
474 struct gpio_bank *bank;
475 void __iomem *reg;
476 u32 val, l = 1 << get_gpio_index(gpio);
477
478 if (cpu_class_is_omap1())
479 return;
480
481 bank = get_gpio_bank(gpio);
482 reg = bank->base;
483
484 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
485 val = __raw_readl(reg);
486
487 if (enable && !(val & l))
488 val |= l;
489 else if (!enable && val & l)
490 val &= ~l;
491 else
492 return;
493
494 if (cpu_is_omap34xx())
495 enable ? clk_enable(bank->dbck) : clk_disable(bank->dbck);
496
497 __raw_writel(val, reg);
498 }
499 EXPORT_SYMBOL(omap_set_gpio_debounce);
500
501 void omap_set_gpio_debounce_time(int gpio, int enc_time)
502 {
503 struct gpio_bank *bank;
504 void __iomem *reg;
505
506 if (cpu_class_is_omap1())
507 return;
508
509 bank = get_gpio_bank(gpio);
510 reg = bank->base;
511
512 enc_time &= 0xff;
513 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
514 __raw_writel(enc_time, reg);
515 }
516 EXPORT_SYMBOL(omap_set_gpio_debounce_time);
517
518 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
519 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
520 int trigger)
521 {
522 void __iomem *base = bank->base;
523 u32 gpio_bit = 1 << gpio;
524
525 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
526 trigger & IRQ_TYPE_LEVEL_LOW);
527 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
528 trigger & IRQ_TYPE_LEVEL_HIGH);
529 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
530 trigger & IRQ_TYPE_EDGE_RISING);
531 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
532 trigger & IRQ_TYPE_EDGE_FALLING);
533
534 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
535 if (trigger != 0)
536 __raw_writel(1 << gpio, bank->base
537 + OMAP24XX_GPIO_SETWKUENA);
538 else
539 __raw_writel(1 << gpio, bank->base
540 + OMAP24XX_GPIO_CLEARWKUENA);
541 } else {
542 if (trigger != 0)
543 bank->enabled_non_wakeup_gpios |= gpio_bit;
544 else
545 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
546 }
547
548 bank->level_mask =
549 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
550 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
551 }
552 #endif
553
554 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
555 {
556 void __iomem *reg = bank->base;
557 u32 l = 0;
558
559 switch (bank->method) {
560 #ifdef CONFIG_ARCH_OMAP1
561 case METHOD_MPUIO:
562 reg += OMAP_MPUIO_GPIO_INT_EDGE;
563 l = __raw_readl(reg);
564 if (trigger & IRQ_TYPE_EDGE_RISING)
565 l |= 1 << gpio;
566 else if (trigger & IRQ_TYPE_EDGE_FALLING)
567 l &= ~(1 << gpio);
568 else
569 goto bad;
570 break;
571 #endif
572 #ifdef CONFIG_ARCH_OMAP15XX
573 case METHOD_GPIO_1510:
574 reg += OMAP1510_GPIO_INT_CONTROL;
575 l = __raw_readl(reg);
576 if (trigger & IRQ_TYPE_EDGE_RISING)
577 l |= 1 << gpio;
578 else if (trigger & IRQ_TYPE_EDGE_FALLING)
579 l &= ~(1 << gpio);
580 else
581 goto bad;
582 break;
583 #endif
584 #ifdef CONFIG_ARCH_OMAP16XX
585 case METHOD_GPIO_1610:
586 if (gpio & 0x08)
587 reg += OMAP1610_GPIO_EDGE_CTRL2;
588 else
589 reg += OMAP1610_GPIO_EDGE_CTRL1;
590 gpio &= 0x07;
591 l = __raw_readl(reg);
592 l &= ~(3 << (gpio << 1));
593 if (trigger & IRQ_TYPE_EDGE_RISING)
594 l |= 2 << (gpio << 1);
595 if (trigger & IRQ_TYPE_EDGE_FALLING)
596 l |= 1 << (gpio << 1);
597 if (trigger)
598 /* Enable wake-up during idle for dynamic tick */
599 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
600 else
601 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
602 break;
603 #endif
604 #ifdef CONFIG_ARCH_OMAP730
605 case METHOD_GPIO_730:
606 reg += OMAP730_GPIO_INT_CONTROL;
607 l = __raw_readl(reg);
608 if (trigger & IRQ_TYPE_EDGE_RISING)
609 l |= 1 << gpio;
610 else if (trigger & IRQ_TYPE_EDGE_FALLING)
611 l &= ~(1 << gpio);
612 else
613 goto bad;
614 break;
615 #endif
616 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
617 case METHOD_GPIO_24XX:
618 set_24xx_gpio_triggering(bank, gpio, trigger);
619 break;
620 #endif
621 default:
622 goto bad;
623 }
624 __raw_writel(l, reg);
625 return 0;
626 bad:
627 return -EINVAL;
628 }
629
630 static int gpio_irq_type(unsigned irq, unsigned type)
631 {
632 struct gpio_bank *bank;
633 unsigned gpio;
634 int retval;
635 unsigned long flags;
636
637 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
638 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
639 else
640 gpio = irq - IH_GPIO_BASE;
641
642 if (check_gpio(gpio) < 0)
643 return -EINVAL;
644
645 if (type & ~IRQ_TYPE_SENSE_MASK)
646 return -EINVAL;
647
648 /* OMAP1 allows only only edge triggering */
649 if (!cpu_class_is_omap2()
650 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
651 return -EINVAL;
652
653 bank = get_irq_chip_data(irq);
654 spin_lock_irqsave(&bank->lock, flags);
655 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
656 if (retval == 0) {
657 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
658 irq_desc[irq].status |= type;
659 }
660 spin_unlock_irqrestore(&bank->lock, flags);
661
662 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
663 __set_irq_handler_unlocked(irq, handle_level_irq);
664 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
665 __set_irq_handler_unlocked(irq, handle_edge_irq);
666
667 return retval;
668 }
669
670 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
671 {
672 void __iomem *reg = bank->base;
673
674 switch (bank->method) {
675 #ifdef CONFIG_ARCH_OMAP1
676 case METHOD_MPUIO:
677 /* MPUIO irqstatus is reset by reading the status register,
678 * so do nothing here */
679 return;
680 #endif
681 #ifdef CONFIG_ARCH_OMAP15XX
682 case METHOD_GPIO_1510:
683 reg += OMAP1510_GPIO_INT_STATUS;
684 break;
685 #endif
686 #ifdef CONFIG_ARCH_OMAP16XX
687 case METHOD_GPIO_1610:
688 reg += OMAP1610_GPIO_IRQSTATUS1;
689 break;
690 #endif
691 #ifdef CONFIG_ARCH_OMAP730
692 case METHOD_GPIO_730:
693 reg += OMAP730_GPIO_INT_STATUS;
694 break;
695 #endif
696 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
697 case METHOD_GPIO_24XX:
698 reg += OMAP24XX_GPIO_IRQSTATUS1;
699 break;
700 #endif
701 default:
702 WARN_ON(1);
703 return;
704 }
705 __raw_writel(gpio_mask, reg);
706
707 /* Workaround for clearing DSP GPIO interrupts to allow retention */
708 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
709 if (cpu_is_omap24xx() || cpu_is_omap34xx())
710 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
711 #endif
712 }
713
714 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
715 {
716 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
717 }
718
719 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
720 {
721 void __iomem *reg = bank->base;
722 int inv = 0;
723 u32 l;
724 u32 mask;
725
726 switch (bank->method) {
727 #ifdef CONFIG_ARCH_OMAP1
728 case METHOD_MPUIO:
729 reg += OMAP_MPUIO_GPIO_MASKIT;
730 mask = 0xffff;
731 inv = 1;
732 break;
733 #endif
734 #ifdef CONFIG_ARCH_OMAP15XX
735 case METHOD_GPIO_1510:
736 reg += OMAP1510_GPIO_INT_MASK;
737 mask = 0xffff;
738 inv = 1;
739 break;
740 #endif
741 #ifdef CONFIG_ARCH_OMAP16XX
742 case METHOD_GPIO_1610:
743 reg += OMAP1610_GPIO_IRQENABLE1;
744 mask = 0xffff;
745 break;
746 #endif
747 #ifdef CONFIG_ARCH_OMAP730
748 case METHOD_GPIO_730:
749 reg += OMAP730_GPIO_INT_MASK;
750 mask = 0xffffffff;
751 inv = 1;
752 break;
753 #endif
754 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
755 case METHOD_GPIO_24XX:
756 reg += OMAP24XX_GPIO_IRQENABLE1;
757 mask = 0xffffffff;
758 break;
759 #endif
760 default:
761 WARN_ON(1);
762 return 0;
763 }
764
765 l = __raw_readl(reg);
766 if (inv)
767 l = ~l;
768 l &= mask;
769 return l;
770 }
771
772 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
773 {
774 void __iomem *reg = bank->base;
775 u32 l;
776
777 switch (bank->method) {
778 #ifdef CONFIG_ARCH_OMAP1
779 case METHOD_MPUIO:
780 reg += OMAP_MPUIO_GPIO_MASKIT;
781 l = __raw_readl(reg);
782 if (enable)
783 l &= ~(gpio_mask);
784 else
785 l |= gpio_mask;
786 break;
787 #endif
788 #ifdef CONFIG_ARCH_OMAP15XX
789 case METHOD_GPIO_1510:
790 reg += OMAP1510_GPIO_INT_MASK;
791 l = __raw_readl(reg);
792 if (enable)
793 l &= ~(gpio_mask);
794 else
795 l |= gpio_mask;
796 break;
797 #endif
798 #ifdef CONFIG_ARCH_OMAP16XX
799 case METHOD_GPIO_1610:
800 if (enable)
801 reg += OMAP1610_GPIO_SET_IRQENABLE1;
802 else
803 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
804 l = gpio_mask;
805 break;
806 #endif
807 #ifdef CONFIG_ARCH_OMAP730
808 case METHOD_GPIO_730:
809 reg += OMAP730_GPIO_INT_MASK;
810 l = __raw_readl(reg);
811 if (enable)
812 l &= ~(gpio_mask);
813 else
814 l |= gpio_mask;
815 break;
816 #endif
817 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
818 case METHOD_GPIO_24XX:
819 if (enable)
820 reg += OMAP24XX_GPIO_SETIRQENABLE1;
821 else
822 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
823 l = gpio_mask;
824 break;
825 #endif
826 default:
827 WARN_ON(1);
828 return;
829 }
830 __raw_writel(l, reg);
831 }
832
833 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
834 {
835 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
836 }
837
838 /*
839 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
840 * 1510 does not seem to have a wake-up register. If JTAG is connected
841 * to the target, system will wake up always on GPIO events. While
842 * system is running all registered GPIO interrupts need to have wake-up
843 * enabled. When system is suspended, only selected GPIO interrupts need
844 * to have wake-up enabled.
845 */
846 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
847 {
848 unsigned long flags;
849
850 switch (bank->method) {
851 #ifdef CONFIG_ARCH_OMAP16XX
852 case METHOD_MPUIO:
853 case METHOD_GPIO_1610:
854 spin_lock_irqsave(&bank->lock, flags);
855 if (enable) {
856 bank->suspend_wakeup |= (1 << gpio);
857 enable_irq_wake(bank->irq);
858 } else {
859 disable_irq_wake(bank->irq);
860 bank->suspend_wakeup &= ~(1 << gpio);
861 }
862 spin_unlock_irqrestore(&bank->lock, flags);
863 return 0;
864 #endif
865 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
866 case METHOD_GPIO_24XX:
867 if (bank->non_wakeup_gpios & (1 << gpio)) {
868 printk(KERN_ERR "Unable to modify wakeup on "
869 "non-wakeup GPIO%d\n",
870 (bank - gpio_bank) * 32 + gpio);
871 return -EINVAL;
872 }
873 spin_lock_irqsave(&bank->lock, flags);
874 if (enable) {
875 bank->suspend_wakeup |= (1 << gpio);
876 enable_irq_wake(bank->irq);
877 } else {
878 disable_irq_wake(bank->irq);
879 bank->suspend_wakeup &= ~(1 << gpio);
880 }
881 spin_unlock_irqrestore(&bank->lock, flags);
882 return 0;
883 #endif
884 default:
885 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
886 bank->method);
887 return -EINVAL;
888 }
889 }
890
891 static void _reset_gpio(struct gpio_bank *bank, int gpio)
892 {
893 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
894 _set_gpio_irqenable(bank, gpio, 0);
895 _clear_gpio_irqstatus(bank, gpio);
896 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
897 }
898
899 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
900 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
901 {
902 unsigned int gpio = irq - IH_GPIO_BASE;
903 struct gpio_bank *bank;
904 int retval;
905
906 if (check_gpio(gpio) < 0)
907 return -ENODEV;
908 bank = get_irq_chip_data(irq);
909 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
910
911 return retval;
912 }
913
914 int omap_request_gpio(int gpio)
915 {
916 struct gpio_bank *bank;
917 unsigned long flags;
918 int status;
919
920 if (check_gpio(gpio) < 0)
921 return -EINVAL;
922
923 status = gpio_request(gpio, NULL);
924 if (status < 0)
925 return status;
926
927 bank = get_gpio_bank(gpio);
928 spin_lock_irqsave(&bank->lock, flags);
929
930 /* Set trigger to none. You need to enable the desired trigger with
931 * request_irq() or set_irq_type().
932 */
933 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
934
935 #ifdef CONFIG_ARCH_OMAP15XX
936 if (bank->method == METHOD_GPIO_1510) {
937 void __iomem *reg;
938
939 /* Claim the pin for MPU */
940 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
941 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
942 }
943 #endif
944 spin_unlock_irqrestore(&bank->lock, flags);
945
946 return 0;
947 }
948
949 void omap_free_gpio(int gpio)
950 {
951 struct gpio_bank *bank;
952 unsigned long flags;
953
954 if (check_gpio(gpio) < 0)
955 return;
956 bank = get_gpio_bank(gpio);
957 spin_lock_irqsave(&bank->lock, flags);
958 if (unlikely(!gpiochip_is_requested(&bank->chip,
959 get_gpio_index(gpio)))) {
960 spin_unlock_irqrestore(&bank->lock, flags);
961 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
962 dump_stack();
963 return;
964 }
965 #ifdef CONFIG_ARCH_OMAP16XX
966 if (bank->method == METHOD_GPIO_1610) {
967 /* Disable wake-up during idle for dynamic tick */
968 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
969 __raw_writel(1 << get_gpio_index(gpio), reg);
970 }
971 #endif
972 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
973 if (bank->method == METHOD_GPIO_24XX) {
974 /* Disable wake-up during idle for dynamic tick */
975 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
976 __raw_writel(1 << get_gpio_index(gpio), reg);
977 }
978 #endif
979 _reset_gpio(bank, gpio);
980 spin_unlock_irqrestore(&bank->lock, flags);
981 gpio_free(gpio);
982 }
983
984 /*
985 * We need to unmask the GPIO bank interrupt as soon as possible to
986 * avoid missing GPIO interrupts for other lines in the bank.
987 * Then we need to mask-read-clear-unmask the triggered GPIO lines
988 * in the bank to avoid missing nested interrupts for a GPIO line.
989 * If we wait to unmask individual GPIO lines in the bank after the
990 * line's interrupt handler has been run, we may miss some nested
991 * interrupts.
992 */
993 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
994 {
995 void __iomem *isr_reg = NULL;
996 u32 isr;
997 unsigned int gpio_irq;
998 struct gpio_bank *bank;
999 u32 retrigger = 0;
1000 int unmasked = 0;
1001
1002 desc->chip->ack(irq);
1003
1004 bank = get_irq_data(irq);
1005 #ifdef CONFIG_ARCH_OMAP1
1006 if (bank->method == METHOD_MPUIO)
1007 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
1008 #endif
1009 #ifdef CONFIG_ARCH_OMAP15XX
1010 if (bank->method == METHOD_GPIO_1510)
1011 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1012 #endif
1013 #if defined(CONFIG_ARCH_OMAP16XX)
1014 if (bank->method == METHOD_GPIO_1610)
1015 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1016 #endif
1017 #ifdef CONFIG_ARCH_OMAP730
1018 if (bank->method == METHOD_GPIO_730)
1019 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
1020 #endif
1021 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1022 if (bank->method == METHOD_GPIO_24XX)
1023 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1024 #endif
1025 while(1) {
1026 u32 isr_saved, level_mask = 0;
1027 u32 enabled;
1028
1029 enabled = _get_gpio_irqbank_mask(bank);
1030 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1031
1032 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1033 isr &= 0x0000ffff;
1034
1035 if (cpu_class_is_omap2()) {
1036 level_mask = bank->level_mask & enabled;
1037 }
1038
1039 /* clear edge sensitive interrupts before handler(s) are
1040 called so that we don't miss any interrupt occurred while
1041 executing them */
1042 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1043 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1044 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1045
1046 /* if there is only edge sensitive GPIO pin interrupts
1047 configured, we could unmask GPIO bank interrupt immediately */
1048 if (!level_mask && !unmasked) {
1049 unmasked = 1;
1050 desc->chip->unmask(irq);
1051 }
1052
1053 isr |= retrigger;
1054 retrigger = 0;
1055 if (!isr)
1056 break;
1057
1058 gpio_irq = bank->virtual_irq_start;
1059 for (; isr != 0; isr >>= 1, gpio_irq++) {
1060 struct irq_desc *d;
1061
1062 if (!(isr & 1))
1063 continue;
1064 d = irq_desc + gpio_irq;
1065
1066 desc_handle_irq(gpio_irq, d);
1067 }
1068 }
1069 /* if bank has any level sensitive GPIO pin interrupt
1070 configured, we must unmask the bank interrupt only after
1071 handler(s) are executed in order to avoid spurious bank
1072 interrupt */
1073 if (!unmasked)
1074 desc->chip->unmask(irq);
1075
1076 }
1077
1078 static void gpio_irq_shutdown(unsigned int irq)
1079 {
1080 unsigned int gpio = irq - IH_GPIO_BASE;
1081 struct gpio_bank *bank = get_irq_chip_data(irq);
1082
1083 _reset_gpio(bank, gpio);
1084 }
1085
1086 static void gpio_ack_irq(unsigned int irq)
1087 {
1088 unsigned int gpio = irq - IH_GPIO_BASE;
1089 struct gpio_bank *bank = get_irq_chip_data(irq);
1090
1091 _clear_gpio_irqstatus(bank, gpio);
1092 }
1093
1094 static void gpio_mask_irq(unsigned int irq)
1095 {
1096 unsigned int gpio = irq - IH_GPIO_BASE;
1097 struct gpio_bank *bank = get_irq_chip_data(irq);
1098
1099 _set_gpio_irqenable(bank, gpio, 0);
1100 }
1101
1102 static void gpio_unmask_irq(unsigned int irq)
1103 {
1104 unsigned int gpio = irq - IH_GPIO_BASE;
1105 struct gpio_bank *bank = get_irq_chip_data(irq);
1106 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1107
1108 /* For level-triggered GPIOs, the clearing must be done after
1109 * the HW source is cleared, thus after the handler has run */
1110 if (bank->level_mask & irq_mask) {
1111 _set_gpio_irqenable(bank, gpio, 0);
1112 _clear_gpio_irqstatus(bank, gpio);
1113 }
1114
1115 _set_gpio_irqenable(bank, gpio, 1);
1116 }
1117
1118 static struct irq_chip gpio_irq_chip = {
1119 .name = "GPIO",
1120 .shutdown = gpio_irq_shutdown,
1121 .ack = gpio_ack_irq,
1122 .mask = gpio_mask_irq,
1123 .unmask = gpio_unmask_irq,
1124 .set_type = gpio_irq_type,
1125 .set_wake = gpio_wake_enable,
1126 };
1127
1128 /*---------------------------------------------------------------------*/
1129
1130 #ifdef CONFIG_ARCH_OMAP1
1131
1132 /* MPUIO uses the always-on 32k clock */
1133
1134 static void mpuio_ack_irq(unsigned int irq)
1135 {
1136 /* The ISR is reset automatically, so do nothing here. */
1137 }
1138
1139 static void mpuio_mask_irq(unsigned int irq)
1140 {
1141 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1142 struct gpio_bank *bank = get_irq_chip_data(irq);
1143
1144 _set_gpio_irqenable(bank, gpio, 0);
1145 }
1146
1147 static void mpuio_unmask_irq(unsigned int irq)
1148 {
1149 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1150 struct gpio_bank *bank = get_irq_chip_data(irq);
1151
1152 _set_gpio_irqenable(bank, gpio, 1);
1153 }
1154
1155 static struct irq_chip mpuio_irq_chip = {
1156 .name = "MPUIO",
1157 .ack = mpuio_ack_irq,
1158 .mask = mpuio_mask_irq,
1159 .unmask = mpuio_unmask_irq,
1160 .set_type = gpio_irq_type,
1161 #ifdef CONFIG_ARCH_OMAP16XX
1162 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1163 .set_wake = gpio_wake_enable,
1164 #endif
1165 };
1166
1167
1168 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1169
1170
1171 #ifdef CONFIG_ARCH_OMAP16XX
1172
1173 #include <linux/platform_device.h>
1174
1175 static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
1176 {
1177 struct gpio_bank *bank = platform_get_drvdata(pdev);
1178 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1179 unsigned long flags;
1180
1181 spin_lock_irqsave(&bank->lock, flags);
1182 bank->saved_wakeup = __raw_readl(mask_reg);
1183 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1184 spin_unlock_irqrestore(&bank->lock, flags);
1185
1186 return 0;
1187 }
1188
1189 static int omap_mpuio_resume_early(struct platform_device *pdev)
1190 {
1191 struct gpio_bank *bank = platform_get_drvdata(pdev);
1192 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1193 unsigned long flags;
1194
1195 spin_lock_irqsave(&bank->lock, flags);
1196 __raw_writel(bank->saved_wakeup, mask_reg);
1197 spin_unlock_irqrestore(&bank->lock, flags);
1198
1199 return 0;
1200 }
1201
1202 /* use platform_driver for this, now that there's no longer any
1203 * point to sys_device (other than not disturbing old code).
1204 */
1205 static struct platform_driver omap_mpuio_driver = {
1206 .suspend_late = omap_mpuio_suspend_late,
1207 .resume_early = omap_mpuio_resume_early,
1208 .driver = {
1209 .name = "mpuio",
1210 },
1211 };
1212
1213 static struct platform_device omap_mpuio_device = {
1214 .name = "mpuio",
1215 .id = -1,
1216 .dev = {
1217 .driver = &omap_mpuio_driver.driver,
1218 }
1219 /* could list the /proc/iomem resources */
1220 };
1221
1222 static inline void mpuio_init(void)
1223 {
1224 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1225
1226 if (platform_driver_register(&omap_mpuio_driver) == 0)
1227 (void) platform_device_register(&omap_mpuio_device);
1228 }
1229
1230 #else
1231 static inline void mpuio_init(void) {}
1232 #endif /* 16xx */
1233
1234 #else
1235
1236 extern struct irq_chip mpuio_irq_chip;
1237
1238 #define bank_is_mpuio(bank) 0
1239 static inline void mpuio_init(void) {}
1240
1241 #endif
1242
1243 /*---------------------------------------------------------------------*/
1244
1245 /* REVISIT these are stupid implementations! replace by ones that
1246 * don't switch on METHOD_* and which mostly avoid spinlocks
1247 */
1248
1249 static int gpio_input(struct gpio_chip *chip, unsigned offset)
1250 {
1251 struct gpio_bank *bank;
1252 unsigned long flags;
1253
1254 bank = container_of(chip, struct gpio_bank, chip);
1255 spin_lock_irqsave(&bank->lock, flags);
1256 _set_gpio_direction(bank, offset, 1);
1257 spin_unlock_irqrestore(&bank->lock, flags);
1258 return 0;
1259 }
1260
1261 static int gpio_get(struct gpio_chip *chip, unsigned offset)
1262 {
1263 return omap_get_gpio_datain(chip->base + offset);
1264 }
1265
1266 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1267 {
1268 struct gpio_bank *bank;
1269 unsigned long flags;
1270
1271 bank = container_of(chip, struct gpio_bank, chip);
1272 spin_lock_irqsave(&bank->lock, flags);
1273 _set_gpio_dataout(bank, offset, value);
1274 _set_gpio_direction(bank, offset, 0);
1275 spin_unlock_irqrestore(&bank->lock, flags);
1276 return 0;
1277 }
1278
1279 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1280 {
1281 struct gpio_bank *bank;
1282 unsigned long flags;
1283
1284 bank = container_of(chip, struct gpio_bank, chip);
1285 spin_lock_irqsave(&bank->lock, flags);
1286 _set_gpio_dataout(bank, offset, value);
1287 spin_unlock_irqrestore(&bank->lock, flags);
1288 }
1289
1290 /*---------------------------------------------------------------------*/
1291
1292 static int initialized;
1293 #if !defined(CONFIG_ARCH_OMAP3)
1294 static struct clk * gpio_ick;
1295 #endif
1296
1297 #if defined(CONFIG_ARCH_OMAP2)
1298 static struct clk * gpio_fck;
1299 #endif
1300
1301 #if defined(CONFIG_ARCH_OMAP2430)
1302 static struct clk * gpio5_ick;
1303 static struct clk * gpio5_fck;
1304 #endif
1305
1306 #if defined(CONFIG_ARCH_OMAP3)
1307 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1308 #endif
1309
1310 /* This lock class tells lockdep that GPIO irqs are in a different
1311 * category than their parents, so it won't report false recursion.
1312 */
1313 static struct lock_class_key gpio_lock_class;
1314
1315 static int __init _omap_gpio_init(void)
1316 {
1317 int i;
1318 int gpio = 0;
1319 struct gpio_bank *bank;
1320 char clk_name[11];
1321
1322 initialized = 1;
1323
1324 #if defined(CONFIG_ARCH_OMAP1)
1325 if (cpu_is_omap15xx()) {
1326 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1327 if (IS_ERR(gpio_ick))
1328 printk("Could not get arm_gpio_ck\n");
1329 else
1330 clk_enable(gpio_ick);
1331 }
1332 #endif
1333 #if defined(CONFIG_ARCH_OMAP2)
1334 if (cpu_class_is_omap2()) {
1335 gpio_ick = clk_get(NULL, "gpios_ick");
1336 if (IS_ERR(gpio_ick))
1337 printk("Could not get gpios_ick\n");
1338 else
1339 clk_enable(gpio_ick);
1340 gpio_fck = clk_get(NULL, "gpios_fck");
1341 if (IS_ERR(gpio_fck))
1342 printk("Could not get gpios_fck\n");
1343 else
1344 clk_enable(gpio_fck);
1345
1346 /*
1347 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1348 */
1349 #if defined(CONFIG_ARCH_OMAP2430)
1350 if (cpu_is_omap2430()) {
1351 gpio5_ick = clk_get(NULL, "gpio5_ick");
1352 if (IS_ERR(gpio5_ick))
1353 printk("Could not get gpio5_ick\n");
1354 else
1355 clk_enable(gpio5_ick);
1356 gpio5_fck = clk_get(NULL, "gpio5_fck");
1357 if (IS_ERR(gpio5_fck))
1358 printk("Could not get gpio5_fck\n");
1359 else
1360 clk_enable(gpio5_fck);
1361 }
1362 #endif
1363 }
1364 #endif
1365
1366 #if defined(CONFIG_ARCH_OMAP3)
1367 if (cpu_is_omap34xx()) {
1368 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1369 sprintf(clk_name, "gpio%d_ick", i + 1);
1370 gpio_iclks[i] = clk_get(NULL, clk_name);
1371 if (IS_ERR(gpio_iclks[i]))
1372 printk(KERN_ERR "Could not get %s\n", clk_name);
1373 else
1374 clk_enable(gpio_iclks[i]);
1375 }
1376 }
1377 #endif
1378
1379
1380 #ifdef CONFIG_ARCH_OMAP15XX
1381 if (cpu_is_omap15xx()) {
1382 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1383 gpio_bank_count = 2;
1384 gpio_bank = gpio_bank_1510;
1385 }
1386 #endif
1387 #if defined(CONFIG_ARCH_OMAP16XX)
1388 if (cpu_is_omap16xx()) {
1389 u32 rev;
1390
1391 gpio_bank_count = 5;
1392 gpio_bank = gpio_bank_1610;
1393 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1394 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1395 (rev >> 4) & 0x0f, rev & 0x0f);
1396 }
1397 #endif
1398 #ifdef CONFIG_ARCH_OMAP730
1399 if (cpu_is_omap730()) {
1400 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1401 gpio_bank_count = 7;
1402 gpio_bank = gpio_bank_730;
1403 }
1404 #endif
1405
1406 #ifdef CONFIG_ARCH_OMAP24XX
1407 if (cpu_is_omap242x()) {
1408 int rev;
1409
1410 gpio_bank_count = 4;
1411 gpio_bank = gpio_bank_242x;
1412 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1413 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1414 (rev >> 4) & 0x0f, rev & 0x0f);
1415 }
1416 if (cpu_is_omap243x()) {
1417 int rev;
1418
1419 gpio_bank_count = 5;
1420 gpio_bank = gpio_bank_243x;
1421 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1422 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
1423 (rev >> 4) & 0x0f, rev & 0x0f);
1424 }
1425 #endif
1426 #ifdef CONFIG_ARCH_OMAP34XX
1427 if (cpu_is_omap34xx()) {
1428 int rev;
1429
1430 gpio_bank_count = OMAP34XX_NR_GPIOS;
1431 gpio_bank = gpio_bank_34xx;
1432 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1433 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1434 (rev >> 4) & 0x0f, rev & 0x0f);
1435 }
1436 #endif
1437 for (i = 0; i < gpio_bank_count; i++) {
1438 int j, gpio_count = 16;
1439
1440 bank = &gpio_bank[i];
1441 spin_lock_init(&bank->lock);
1442 if (bank_is_mpuio(bank))
1443 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
1444 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1445 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1446 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1447 }
1448 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1449 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1450 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1451 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1452 }
1453 if (cpu_is_omap730() && bank->method == METHOD_GPIO_730) {
1454 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1455 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1456
1457 gpio_count = 32; /* 730 has 32-bit GPIOs */
1458 }
1459
1460 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1461 if (bank->method == METHOD_GPIO_24XX) {
1462 static const u32 non_wakeup_gpios[] = {
1463 0xe203ffc0, 0x08700040
1464 };
1465
1466 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1467 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1468 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1469
1470 /* Initialize interface clock ungated, module enabled */
1471 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1472 if (i < ARRAY_SIZE(non_wakeup_gpios))
1473 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1474 gpio_count = 32;
1475 }
1476 #endif
1477
1478 /* REVISIT eventually switch from OMAP-specific gpio structs
1479 * over to the generic ones
1480 */
1481 bank->chip.direction_input = gpio_input;
1482 bank->chip.get = gpio_get;
1483 bank->chip.direction_output = gpio_output;
1484 bank->chip.set = gpio_set;
1485 if (bank_is_mpuio(bank)) {
1486 bank->chip.label = "mpuio";
1487 #ifdef CONFIG_ARCH_OMAP16XX
1488 bank->chip.dev = &omap_mpuio_device.dev;
1489 #endif
1490 bank->chip.base = OMAP_MPUIO(0);
1491 } else {
1492 bank->chip.label = "gpio";
1493 bank->chip.base = gpio;
1494 gpio += gpio_count;
1495 }
1496 bank->chip.ngpio = gpio_count;
1497
1498 gpiochip_add(&bank->chip);
1499
1500 for (j = bank->virtual_irq_start;
1501 j < bank->virtual_irq_start + gpio_count; j++) {
1502 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
1503 set_irq_chip_data(j, bank);
1504 if (bank_is_mpuio(bank))
1505 set_irq_chip(j, &mpuio_irq_chip);
1506 else
1507 set_irq_chip(j, &gpio_irq_chip);
1508 set_irq_handler(j, handle_simple_irq);
1509 set_irq_flags(j, IRQF_VALID);
1510 }
1511 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1512 set_irq_data(bank->irq, bank);
1513
1514 if (cpu_is_omap34xx()) {
1515 sprintf(clk_name, "gpio%d_dbck", i + 1);
1516 bank->dbck = clk_get(NULL, clk_name);
1517 if (IS_ERR(bank->dbck))
1518 printk(KERN_ERR "Could not get %s\n", clk_name);
1519 }
1520 }
1521
1522 /* Enable system clock for GPIO module.
1523 * The CAM_CLK_CTRL *is* really the right place. */
1524 if (cpu_is_omap16xx())
1525 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1526
1527 /* Enable autoidle for the OCP interface */
1528 if (cpu_is_omap24xx())
1529 omap_writel(1 << 0, 0x48019010);
1530 if (cpu_is_omap34xx())
1531 omap_writel(1 << 0, 0x48306814);
1532
1533 return 0;
1534 }
1535
1536 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1537 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1538 {
1539 int i;
1540
1541 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1542 return 0;
1543
1544 for (i = 0; i < gpio_bank_count; i++) {
1545 struct gpio_bank *bank = &gpio_bank[i];
1546 void __iomem *wake_status;
1547 void __iomem *wake_clear;
1548 void __iomem *wake_set;
1549 unsigned long flags;
1550
1551 switch (bank->method) {
1552 #ifdef CONFIG_ARCH_OMAP16XX
1553 case METHOD_GPIO_1610:
1554 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1555 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1556 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1557 break;
1558 #endif
1559 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1560 case METHOD_GPIO_24XX:
1561 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
1562 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1563 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1564 break;
1565 #endif
1566 default:
1567 continue;
1568 }
1569
1570 spin_lock_irqsave(&bank->lock, flags);
1571 bank->saved_wakeup = __raw_readl(wake_status);
1572 __raw_writel(0xffffffff, wake_clear);
1573 __raw_writel(bank->suspend_wakeup, wake_set);
1574 spin_unlock_irqrestore(&bank->lock, flags);
1575 }
1576
1577 return 0;
1578 }
1579
1580 static int omap_gpio_resume(struct sys_device *dev)
1581 {
1582 int i;
1583
1584 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1585 return 0;
1586
1587 for (i = 0; i < gpio_bank_count; i++) {
1588 struct gpio_bank *bank = &gpio_bank[i];
1589 void __iomem *wake_clear;
1590 void __iomem *wake_set;
1591 unsigned long flags;
1592
1593 switch (bank->method) {
1594 #ifdef CONFIG_ARCH_OMAP16XX
1595 case METHOD_GPIO_1610:
1596 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1597 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1598 break;
1599 #endif
1600 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1601 case METHOD_GPIO_24XX:
1602 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1603 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1604 break;
1605 #endif
1606 default:
1607 continue;
1608 }
1609
1610 spin_lock_irqsave(&bank->lock, flags);
1611 __raw_writel(0xffffffff, wake_clear);
1612 __raw_writel(bank->saved_wakeup, wake_set);
1613 spin_unlock_irqrestore(&bank->lock, flags);
1614 }
1615
1616 return 0;
1617 }
1618
1619 static struct sysdev_class omap_gpio_sysclass = {
1620 .name = "gpio",
1621 .suspend = omap_gpio_suspend,
1622 .resume = omap_gpio_resume,
1623 };
1624
1625 static struct sys_device omap_gpio_device = {
1626 .id = 0,
1627 .cls = &omap_gpio_sysclass,
1628 };
1629
1630 #endif
1631
1632 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1633
1634 static int workaround_enabled;
1635
1636 void omap2_gpio_prepare_for_retention(void)
1637 {
1638 int i, c = 0;
1639
1640 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1641 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1642 for (i = 0; i < gpio_bank_count; i++) {
1643 struct gpio_bank *bank = &gpio_bank[i];
1644 u32 l1, l2;
1645
1646 if (!(bank->enabled_non_wakeup_gpios))
1647 continue;
1648 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1649 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1650 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1651 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1652 #endif
1653 bank->saved_fallingdetect = l1;
1654 bank->saved_risingdetect = l2;
1655 l1 &= ~bank->enabled_non_wakeup_gpios;
1656 l2 &= ~bank->enabled_non_wakeup_gpios;
1657 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1658 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1659 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1660 #endif
1661 c++;
1662 }
1663 if (!c) {
1664 workaround_enabled = 0;
1665 return;
1666 }
1667 workaround_enabled = 1;
1668 }
1669
1670 void omap2_gpio_resume_after_retention(void)
1671 {
1672 int i;
1673
1674 if (!workaround_enabled)
1675 return;
1676 for (i = 0; i < gpio_bank_count; i++) {
1677 struct gpio_bank *bank = &gpio_bank[i];
1678 u32 l;
1679
1680 if (!(bank->enabled_non_wakeup_gpios))
1681 continue;
1682 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1683 __raw_writel(bank->saved_fallingdetect,
1684 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1685 __raw_writel(bank->saved_risingdetect,
1686 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1687 #endif
1688 /* Check if any of the non-wakeup interrupt GPIOs have changed
1689 * state. If so, generate an IRQ by software. This is
1690 * horribly racy, but it's the best we can do to work around
1691 * this silicon bug. */
1692 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1693 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1694 #endif
1695 l ^= bank->saved_datain;
1696 l &= bank->non_wakeup_gpios;
1697 if (l) {
1698 u32 old0, old1;
1699 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1700 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1701 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1702 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1703 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1704 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1705 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1706 #endif
1707 }
1708 }
1709
1710 }
1711
1712 #endif
1713
1714 /*
1715 * This may get called early from board specific init
1716 * for boards that have interrupts routed via FPGA.
1717 */
1718 int __init omap_gpio_init(void)
1719 {
1720 if (!initialized)
1721 return _omap_gpio_init();
1722 else
1723 return 0;
1724 }
1725
1726 static int __init omap_gpio_sysinit(void)
1727 {
1728 int ret = 0;
1729
1730 if (!initialized)
1731 ret = _omap_gpio_init();
1732
1733 mpuio_init();
1734
1735 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1736 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
1737 if (ret == 0) {
1738 ret = sysdev_class_register(&omap_gpio_sysclass);
1739 if (ret == 0)
1740 ret = sysdev_register(&omap_gpio_device);
1741 }
1742 }
1743 #endif
1744
1745 return ret;
1746 }
1747
1748 EXPORT_SYMBOL(omap_request_gpio);
1749 EXPORT_SYMBOL(omap_free_gpio);
1750 EXPORT_SYMBOL(omap_set_gpio_direction);
1751 EXPORT_SYMBOL(omap_set_gpio_dataout);
1752 EXPORT_SYMBOL(omap_get_gpio_datain);
1753
1754 arch_initcall(omap_gpio_sysinit);
1755
1756
1757 #ifdef CONFIG_DEBUG_FS
1758
1759 #include <linux/debugfs.h>
1760 #include <linux/seq_file.h>
1761
1762 static int gpio_is_input(struct gpio_bank *bank, int mask)
1763 {
1764 void __iomem *reg = bank->base;
1765
1766 switch (bank->method) {
1767 case METHOD_MPUIO:
1768 reg += OMAP_MPUIO_IO_CNTL;
1769 break;
1770 case METHOD_GPIO_1510:
1771 reg += OMAP1510_GPIO_DIR_CONTROL;
1772 break;
1773 case METHOD_GPIO_1610:
1774 reg += OMAP1610_GPIO_DIRECTION;
1775 break;
1776 case METHOD_GPIO_730:
1777 reg += OMAP730_GPIO_DIR_CONTROL;
1778 break;
1779 case METHOD_GPIO_24XX:
1780 reg += OMAP24XX_GPIO_OE;
1781 break;
1782 }
1783 return __raw_readl(reg) & mask;
1784 }
1785
1786
1787 static int dbg_gpio_show(struct seq_file *s, void *unused)
1788 {
1789 unsigned i, j, gpio;
1790
1791 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
1792 struct gpio_bank *bank = gpio_bank + i;
1793 unsigned bankwidth = 16;
1794 u32 mask = 1;
1795
1796 if (bank_is_mpuio(bank))
1797 gpio = OMAP_MPUIO(0);
1798 else if (cpu_class_is_omap2() || cpu_is_omap730())
1799 bankwidth = 32;
1800
1801 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
1802 unsigned irq, value, is_in, irqstat;
1803 const char *label;
1804
1805 label = gpiochip_is_requested(&bank->chip, j);
1806 if (!label)
1807 continue;
1808
1809 irq = bank->virtual_irq_start + j;
1810 value = omap_get_gpio_datain(gpio);
1811 is_in = gpio_is_input(bank, mask);
1812
1813 if (bank_is_mpuio(bank))
1814 seq_printf(s, "MPUIO %2d ", j);
1815 else
1816 seq_printf(s, "GPIO %3d ", gpio);
1817 seq_printf(s, "(%10s): %s %s",
1818 label,
1819 is_in ? "in " : "out",
1820 value ? "hi" : "lo");
1821
1822 /* FIXME for at least omap2, show pullup/pulldown state */
1823
1824 irqstat = irq_desc[irq].status;
1825 if (is_in && ((bank->suspend_wakeup & mask)
1826 || irqstat & IRQ_TYPE_SENSE_MASK)) {
1827 char *trigger = NULL;
1828
1829 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
1830 case IRQ_TYPE_EDGE_FALLING:
1831 trigger = "falling";
1832 break;
1833 case IRQ_TYPE_EDGE_RISING:
1834 trigger = "rising";
1835 break;
1836 case IRQ_TYPE_EDGE_BOTH:
1837 trigger = "bothedge";
1838 break;
1839 case IRQ_TYPE_LEVEL_LOW:
1840 trigger = "low";
1841 break;
1842 case IRQ_TYPE_LEVEL_HIGH:
1843 trigger = "high";
1844 break;
1845 case IRQ_TYPE_NONE:
1846 trigger = "(?)";
1847 break;
1848 }
1849 seq_printf(s, ", irq-%d %-8s%s",
1850 irq, trigger,
1851 (bank->suspend_wakeup & mask)
1852 ? " wakeup" : "");
1853 }
1854 seq_printf(s, "\n");
1855 }
1856
1857 if (bank_is_mpuio(bank)) {
1858 seq_printf(s, "\n");
1859 gpio = 0;
1860 }
1861 }
1862 return 0;
1863 }
1864
1865 static int dbg_gpio_open(struct inode *inode, struct file *file)
1866 {
1867 return single_open(file, dbg_gpio_show, &inode->i_private);
1868 }
1869
1870 static const struct file_operations debug_fops = {
1871 .open = dbg_gpio_open,
1872 .read = seq_read,
1873 .llseek = seq_lseek,
1874 .release = single_release,
1875 };
1876
1877 static int __init omap_gpio_debuginit(void)
1878 {
1879 (void) debugfs_create_file("omap_gpio", S_IRUGO,
1880 NULL, NULL, &debug_fops);
1881 return 0;
1882 }
1883 late_initcall(omap_gpio_debuginit);
1884 #endif
Linux for Ginger Game Console