2 * Author: Andy Fleming <afleming@freescale.com>
3 * Kumar Gala <galak@kernel.crashing.org>
5 * Copyright 2006-2008, 2011-2012, 2015 Freescale Semiconductor Inc.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
13 #include <linux/stddef.h>
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
18 #include <linux/kexec.h>
19 #include <linux/highmem.h>
20 #include <linux/cpu.h>
21 #include <linux/fsl/guts.h>
23 #include <asm/machdep.h>
24 #include <asm/pgtable.h>
27 #include <asm/cacheflush.h>
28 #include <asm/dbell.h>
29 #include <asm/code-patching.h>
30 #include <asm/cputhreads.h>
31 #include <asm/fsl_pm.h>
33 #include <sysdev/fsl_soc.h>
34 #include <sysdev/mpic.h>
37 struct epapr_spin_table
{
46 #ifdef CONFIG_HOTPLUG_CPU
51 static void mpc85xx_give_timebase(void)
55 local_irq_save(flags
);
62 qoriq_pm_ops
->freeze_time_base(true);
65 * e5500/e6500 have a workaround for erratum A-006958 in place
66 * that will reread the timebase until TBL is non-zero.
67 * That would be a bad thing when the timebase is frozen.
69 * Thus, we read it manually, and instead of checking that
70 * TBL is non-zero, we ensure that TB does not change. We don't
71 * do that for the main mftb implementation, because it requires
77 asm volatile("mfspr %0, %1" : "=r" (timebase
) :
82 asm volatile("mfspr %0, %1" : "=r" (timebase
) :
84 } while (prev
!= timebase
);
95 qoriq_pm_ops
->freeze_time_base(false);
97 local_irq_restore(flags
);
100 static void mpc85xx_take_timebase(void)
104 local_irq_save(flags
);
111 set_tb(timebase
>> 32, timebase
& 0xffffffff);
115 local_irq_restore(flags
);
118 static void smp_85xx_mach_cpu_die(void)
120 unsigned int cpu
= smp_processor_id();
124 /* mask all irqs to prevent cpu wakeup */
125 qoriq_pm_ops
->irq_mask(cpu
);
130 mtspr(SPRN_TSR
, mfspr(SPRN_TSR
));
132 generic_set_cpu_dead(cpu
);
134 cur_cpu_spec
->cpu_down_flush();
136 qoriq_pm_ops
->cpu_die(cpu
);
142 static void qoriq_cpu_kill(unsigned int cpu
)
146 for (i
= 0; i
< 500; i
++) {
147 if (is_cpu_dead(cpu
)) {
149 paca
[cpu
].cpu_start
= 0;
155 pr_err("CPU%d didn't die...\n", cpu
);
160 * To keep it compatible with old boot program which uses
161 * cache-inhibit spin table, we need to flush the cache
162 * before accessing spin table to invalidate any staled data.
163 * We also need to flush the cache after writing to spin
164 * table to push data out.
166 static inline void flush_spin_table(void *spin_table
)
168 flush_dcache_range((ulong
)spin_table
,
169 (ulong
)spin_table
+ sizeof(struct epapr_spin_table
));
172 static inline u32
read_spin_table_addr_l(void *spin_table
)
174 flush_dcache_range((ulong
)spin_table
,
175 (ulong
)spin_table
+ sizeof(struct epapr_spin_table
));
176 return in_be32(&((struct epapr_spin_table
*)spin_table
)->addr_l
);
180 static void wake_hw_thread(void *info
)
182 void fsl_secondary_thread_init(void);
184 int cpu
= *(const int *)info
;
186 inia
= *(unsigned long *)fsl_secondary_thread_init
;
187 book3e_start_thread(cpu_thread_in_core(cpu
), inia
);
191 static int smp_85xx_start_cpu(int cpu
)
194 struct device_node
*np
;
195 const u64
*cpu_rel_addr
;
198 int hw_cpu
= get_hard_smp_processor_id(cpu
);
199 struct epapr_spin_table __iomem
*spin_table
;
201 np
= of_get_cpu_node(cpu
, NULL
);
202 cpu_rel_addr
= of_get_property(np
, "cpu-release-addr", NULL
);
204 pr_err("No cpu-release-addr for cpu %d\n", cpu
);
209 * A secondary core could be in a spinloop in the bootpage
210 * (0xfffff000), somewhere in highmem, or somewhere in lowmem.
211 * The bootpage and highmem can be accessed via ioremap(), but
212 * we need to directly access the spinloop if its in lowmem.
214 ioremappable
= *cpu_rel_addr
> virt_to_phys(high_memory
);
216 /* Map the spin table */
218 spin_table
= ioremap_prot(*cpu_rel_addr
,
219 sizeof(struct epapr_spin_table
), _PAGE_COHERENT
);
221 spin_table
= phys_to_virt(*cpu_rel_addr
);
223 local_irq_save(flags
);
227 qoriq_pm_ops
->cpu_up_prepare(cpu
);
229 /* if cpu is not spinning, reset it */
230 if (read_spin_table_addr_l(spin_table
) != 1) {
232 * We don't set the BPTR register here since it already points
233 * to the boot page properly.
235 mpic_reset_core(cpu
);
238 * wait until core is ready...
239 * We need to invalidate the stale data, in case the boot
240 * loader uses a cache-inhibited spin table.
242 if (!spin_event_timeout(
243 read_spin_table_addr_l(spin_table
) == 1,
245 pr_err("timeout waiting for cpu %d to reset\n",
252 flush_spin_table(spin_table
);
253 out_be32(&spin_table
->pir
, hw_cpu
);
255 out_be64((u64
*)(&spin_table
->addr_h
),
256 __pa(ppc_function_entry(generic_secondary_smp_init
)));
258 out_be32(&spin_table
->addr_l
, __pa(__early_start
));
260 flush_spin_table(spin_table
);
262 local_irq_restore(flags
);
270 static int smp_85xx_kick_cpu(int nr
)
277 WARN_ON(nr
< 0 || nr
>= num_possible_cpus());
279 pr_debug("kick CPU #%d\n", nr
);
282 if (threads_per_core
== 2) {
283 if (WARN_ON_ONCE(!cpu_has_feature(CPU_FTR_SMT
)))
286 booting_thread_hwid
= cpu_thread_in_core(nr
);
287 primary
= cpu_first_thread_sibling(nr
);
290 qoriq_pm_ops
->cpu_up_prepare(nr
);
293 * If either thread in the core is online, use it to start
296 if (cpu_online(primary
)) {
297 smp_call_function_single(primary
,
298 wake_hw_thread
, &nr
, 1);
300 } else if (cpu_online(primary
+ 1)) {
301 smp_call_function_single(primary
+ 1,
302 wake_hw_thread
, &nr
, 1);
307 * If getting here, it means both threads in the core are
308 * offline. So start the primary thread, then it will start
309 * the thread specified in booting_thread_hwid, the one
310 * corresponding to nr.
313 } else if (threads_per_core
== 1) {
315 * If one core has only one thread, set booting_thread_hwid to
318 booting_thread_hwid
= INVALID_THREAD_HWID
;
320 } else if (threads_per_core
> 2) {
321 pr_err("Do not support more than 2 threads per CPU.");
325 ret
= smp_85xx_start_cpu(primary
);
330 paca
[nr
].cpu_start
= 1;
331 generic_set_cpu_up(nr
);
335 ret
= smp_85xx_start_cpu(nr
);
339 generic_set_cpu_up(nr
);
345 struct smp_ops_t smp_85xx_ops
= {
346 .kick_cpu
= smp_85xx_kick_cpu
,
347 .cpu_bootable
= smp_generic_cpu_bootable
,
348 #ifdef CONFIG_HOTPLUG_CPU
349 .cpu_disable
= generic_cpu_disable
,
350 .cpu_die
= generic_cpu_die
,
352 #if defined(CONFIG_KEXEC) && !defined(CONFIG_PPC64)
353 .give_timebase
= smp_generic_give_timebase
,
354 .take_timebase
= smp_generic_take_timebase
,
360 atomic_t kexec_down_cpus
= ATOMIC_INIT(0);
362 void mpc85xx_smp_kexec_cpu_down(int crash_shutdown
, int secondary
)
367 cur_cpu_spec
->cpu_down_flush();
368 atomic_inc(&kexec_down_cpus
);
374 static void mpc85xx_smp_kexec_down(void *arg
)
376 if (ppc_md
.kexec_cpu_down
)
377 ppc_md
.kexec_cpu_down(0,1);
380 void mpc85xx_smp_kexec_cpu_down(int crash_shutdown
, int secondary
)
382 int cpu
= smp_processor_id();
383 int sibling
= cpu_last_thread_sibling(cpu
);
384 bool notified
= false;
386 int disable_threadbit
= 0;
392 mpic_teardown_this_cpu(secondary
);
394 if (cpu
== crashing_cpu
&& cpu_thread_in_core(cpu
) != 0) {
396 * We enter the crash kernel on whatever cpu crashed,
397 * even if it's a secondary thread. If that's the case,
398 * disable the corresponding primary thread.
400 disable_threadbit
= 1;
401 disable_cpu
= cpu_first_thread_sibling(cpu
);
402 } else if (sibling
!= crashing_cpu
&&
403 cpu_thread_in_core(cpu
) == 0 &&
404 cpu_thread_in_core(sibling
) != 0) {
405 disable_threadbit
= 2;
406 disable_cpu
= sibling
;
409 if (disable_threadbit
) {
410 while (paca
[disable_cpu
].kexec_state
< KEXEC_STATE_REAL_MODE
) {
413 if (!notified
&& now
- start
> 1000000) {
414 pr_info("%s/%d: waiting for cpu %d to enter KEXEC_STATE_REAL_MODE (%d)\n",
415 __func__
, smp_processor_id(),
417 paca
[disable_cpu
].kexec_state
);
423 pr_info("%s: cpu %d done waiting\n",
424 __func__
, disable_cpu
);
427 mtspr(SPRN_TENC
, disable_threadbit
);
428 while (mfspr(SPRN_TENSR
) & disable_threadbit
)
434 static void mpc85xx_smp_machine_kexec(struct kimage
*image
)
437 int timeout
= INT_MAX
;
438 int i
, num_cpus
= num_present_cpus();
440 if (image
->type
== KEXEC_TYPE_DEFAULT
)
441 smp_call_function(mpc85xx_smp_kexec_down
, NULL
, 0);
443 while ( (atomic_read(&kexec_down_cpus
) != (num_cpus
- 1)) &&
450 printk(KERN_ERR
"Unable to bring down secondary cpu(s)");
452 for_each_online_cpu(i
)
454 if ( i
== smp_processor_id() ) continue;
459 default_machine_kexec(image
);
461 #endif /* CONFIG_KEXEC */
463 static void smp_85xx_basic_setup(int cpu_nr
)
465 if (cpu_has_feature(CPU_FTR_DBELL
))
466 doorbell_setup_this_cpu();
469 static void smp_85xx_setup_cpu(int cpu_nr
)
471 mpic_setup_this_cpu();
472 smp_85xx_basic_setup(cpu_nr
);
475 void __init
mpc85xx_smp_init(void)
477 struct device_node
*np
;
480 np
= of_find_node_by_type(NULL
, "open-pic");
482 smp_85xx_ops
.probe
= smp_mpic_probe
;
483 smp_85xx_ops
.setup_cpu
= smp_85xx_setup_cpu
;
484 smp_85xx_ops
.message_pass
= smp_mpic_message_pass
;
486 smp_85xx_ops
.setup_cpu
= smp_85xx_basic_setup
;
488 if (cpu_has_feature(CPU_FTR_DBELL
)) {
490 * If left NULL, .message_pass defaults to
491 * smp_muxed_ipi_message_pass
493 smp_85xx_ops
.message_pass
= NULL
;
494 smp_85xx_ops
.cause_ipi
= doorbell_cause_ipi
;
495 smp_85xx_ops
.probe
= NULL
;
498 #ifdef CONFIG_HOTPLUG_CPU
499 #ifdef CONFIG_FSL_CORENET_RCPM
503 #ifdef CONFIG_FSL_PMC
507 smp_85xx_ops
.give_timebase
= mpc85xx_give_timebase
;
508 smp_85xx_ops
.take_timebase
= mpc85xx_take_timebase
;
509 ppc_md
.cpu_die
= smp_85xx_mach_cpu_die
;
510 smp_85xx_ops
.cpu_die
= qoriq_cpu_kill
;
513 smp_ops
= &smp_85xx_ops
;
516 ppc_md
.kexec_cpu_down
= mpc85xx_smp_kexec_cpu_down
;
517 ppc_md
.machine_kexec
= mpc85xx_smp_machine_kexec
;