1 ########################################################################
2 # Implement fast SHA-512 with AVX instructions. (x86_64)
4 # Copyright (C) 2013 Intel Corporation.
7 # James Guilford <james.guilford@intel.com>
8 # Kirk Yap <kirk.s.yap@intel.com>
9 # David Cote <david.m.cote@intel.com>
10 # Tim Chen <tim.c.chen@linux.intel.com>
12 # This software is available to you under a choice of one of two
13 # licenses. You may choose to be licensed under the terms of the GNU
14 # General Public License (GPL) Version 2, available from the file
15 # COPYING in the main directory of this source tree, or the
16 # OpenIB.org BSD license below:
18 # Redistribution and use in source and binary forms, with or
19 # without modification, are permitted provided that the following
22 # - Redistributions of source code must retain the above
23 # copyright notice, this list of conditions and the following
26 # - Redistributions in binary form must reproduce the above
27 # copyright notice, this list of conditions and the following
28 # disclaimer in the documentation and/or other materials
29 # provided with the distribution.
31 # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 # EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
33 # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 # NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
35 # BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
36 # ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
37 # CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
40 ########################################################################
42 # This code is described in an Intel White-Paper:
43 # "Fast SHA-512 Implementations on Intel Architecture Processors"
45 # To find it, surf to http://www.intel.com/p/en_US/embedded
46 # and search for that title.
48 ########################################################################
51 #include <linux/linkage.h>
74 # Local variables (stack frame)
78 # W[t] + K[t] | W[t+1] + K[t+1]
84 frame_WK = frame_W + W_SIZE
85 frame_RSPSAVE = frame_WK + WK_SIZE
86 frame_GPRSAVE = frame_RSPSAVE + RSPSAVE_SIZE
87 frame_size = frame_GPRSAVE + GPRSAVE_SIZE
89 # Useful QWORD "arrays" for simpler memory references
90 # MSG, DIGEST, K_t, W_t are arrays
91 # WK_2(t) points to 1 of 2 qwords at frame.WK depdending on t being odd/even
93 # Input message (arg1)
94 #define MSG(i) 8*i(msg)
96 # Output Digest (arg2)
97 #define DIGEST(i) 8*i(digest)
99 # SHA Constants (static mem)
100 #define K_t(i) 8*i+K512(%rip)
102 # Message Schedule (stack frame)
103 #define W_t(i) 8*i+frame_W(%rsp)
105 # W[t]+K[t] (stack frame)
106 #define WK_2(i) 8*((i%2))+frame_WK(%rsp)
109 # Rotate symbols a..h right
122 # shld is faster than ror on Sandybridge
123 shld $(64-\p2), \p1, \p1
126 .macro SHA512_Round rnd
128 mov f_64, T1 # T1 = f
129 mov e_64, tmp0 # tmp = e
130 xor g_64, T1 # T1 = f ^ g
131 RORQ tmp0, 23 # 41 # tmp = e ror 23
132 and e_64, T1 # T1 = (f ^ g) & e
133 xor e_64, tmp0 # tmp = (e ror 23) ^ e
134 xor g_64, T1 # T1 = ((f ^ g) & e) ^ g = CH(e,f,g)
136 add WK_2(idx), T1 # W[t] + K[t] from message scheduler
137 RORQ tmp0, 4 # 18 # tmp = ((e ror 23) ^ e) ror 4
138 xor e_64, tmp0 # tmp = (((e ror 23) ^ e) ror 4) ^ e
139 mov a_64, T2 # T2 = a
140 add h_64, T1 # T1 = CH(e,f,g) + W[t] + K[t] + h
141 RORQ tmp0, 14 # 14 # tmp = ((((e ror23)^e)ror4)^e)ror14 = S1(e)
142 add tmp0, T1 # T1 = CH(e,f,g) + W[t] + K[t] + S1(e)
143 mov a_64, tmp0 # tmp = a
144 xor c_64, T2 # T2 = a ^ c
145 and c_64, tmp0 # tmp = a & c
146 and b_64, T2 # T2 = (a ^ c) & b
147 xor tmp0, T2 # T2 = ((a ^ c) & b) ^ (a & c) = Maj(a,b,c)
148 mov a_64, tmp0 # tmp = a
149 RORQ tmp0, 5 # 39 # tmp = a ror 5
150 xor a_64, tmp0 # tmp = (a ror 5) ^ a
151 add T1, d_64 # e(next_state) = d + T1
152 RORQ tmp0, 6 # 34 # tmp = ((a ror 5) ^ a) ror 6
153 xor a_64, tmp0 # tmp = (((a ror 5) ^ a) ror 6) ^ a
154 lea (T1, T2), h_64 # a(next_state) = T1 + Maj(a,b,c)
155 RORQ tmp0, 28 # 28 # tmp = ((((a ror5)^a)ror6)^a)ror28 = S0(a)
156 add tmp0, h_64 # a(next_state) = T1 + Maj(a,b,c) S0(a)
160 .macro SHA512_2Sched_2Round_avx rnd
161 # Compute rounds t-2 and t-1
162 # Compute message schedule QWORDS t and t+1
164 # Two rounds are computed based on the values for K[t-2]+W[t-2] and
165 # K[t-1]+W[t-1] which were previously stored at WK_2 by the message
167 # The two new schedule QWORDS are stored at [W_t(t)] and [W_t(t+1)].
168 # They are then added to their respective SHA512 constants at
169 # [K_t(t)] and [K_t(t+1)] and stored at dqword [WK_2(t)]
170 # For brievity, the comments following vectored instructions only refer to
171 # the first of a pair of QWORDS.
172 # Eg. XMM4=W[t-2] really means XMM4={W[t-2]|W[t-1]}
173 # The computation of the message schedule and the rounds are tightly
174 # stitched to take advantage of instruction-level parallelism.
177 vmovdqa W_t(idx), %xmm4 # XMM4 = W[t-2]
179 vmovdqu W_t(idx), %xmm5 # XMM5 = W[t-15]
181 vpsrlq $61, %xmm4, %xmm0 # XMM0 = W[t-2]>>61
183 vpsrlq $1, %xmm5, %xmm6 # XMM6 = W[t-15]>>1
186 vpsrlq $19, %xmm4, %xmm1 # XMM1 = W[t-2]>>19
189 vpxor %xmm1, %xmm0, %xmm0 # XMM0 = W[t-2]>>61 ^ W[t-2]>>19
193 vpsrlq $8, %xmm5, %xmm7 # XMM7 = W[t-15]>>8
195 vpsrlq $6, %xmm4, %xmm2 # XMM2 = W[t-2]>>6
199 vpxor %xmm7, %xmm6, %xmm6 # XMM6 = W[t-15]>>1 ^ W[t-15]>>8
202 vpsrlq $7, %xmm5, %xmm8 # XMM8 = W[t-15]>>7
205 vpsllq $(64-61), %xmm4, %xmm3 # XMM3 = W[t-2]<<3
208 vpxor %xmm3, %xmm2, %xmm2 # XMM2 = W[t-2]>>6 ^ W[t-2]<<3
211 vpsllq $(64-1), %xmm5, %xmm9 # XMM9 = W[t-15]<<63
213 vpxor %xmm9, %xmm8, %xmm8 # XMM8 = W[t-15]>>7 ^ W[t-15]<<63
218 vpxor %xmm8, %xmm6, %xmm6 # XMM6 = W[t-15]>>1 ^ W[t-15]>>8 ^
219 # W[t-15]>>7 ^ W[t-15]<<63
222 vpsllq $(64-19), %xmm4, %xmm4 # XMM4 = W[t-2]<<25
225 vpxor %xmm4, %xmm0, %xmm0 # XMM0 = W[t-2]>>61 ^ W[t-2]>>19 ^
228 vpxor %xmm2, %xmm0, %xmm0 # XMM0 = s1(W[t-2])
232 vpaddq W_t(idx), %xmm0, %xmm0 # XMM0 = s1(W[t-2]) + W[t-16]
234 vmovdqu W_t(idx), %xmm1 # XMM1 = W[t-7]
239 vpsllq $(64-8), %xmm5, %xmm5 # XMM5 = W[t-15]<<56
242 vpxor %xmm5, %xmm6, %xmm6 # XMM6 = s0(W[t-15])
244 vpaddq %xmm6, %xmm0, %xmm0 # XMM0 = s1(W[t-2]) + W[t-16] + s0(W[t-15])
246 vpaddq %xmm1, %xmm0, %xmm0 # XMM0 = W[t] = s1(W[t-2]) + W[t-7] +
247 # s0(W[t-15]) + W[t-16]
253 vmovdqa %xmm0, W_t(idx) # Store W[t]
254 vpaddq K_t(idx), %xmm0, %xmm0 # Compute W[t]+K[t]
255 vmovdqa %xmm0, WK_2(idx) # Store W[t]+K[t] for next rounds
273 ########################################################################
274 # void sha512_transform_avx(void* D, const void* M, u64 L)
275 # Purpose: Updates the SHA512 digest stored at D with the message stored in M.
276 # The size of the message pointed to by M must be an integer multiple of SHA512
278 # L is the message length in SHA512 blocks
279 ########################################################################
280 ENTRY(sha512_transform_avx)
284 # Allocate Stack Space
286 sub $frame_size, %rsp
287 and $~(0x20 - 1), %rsp
288 mov %rax, frame_RSPSAVE(%rsp)
291 mov %rbx, frame_GPRSAVE(%rsp)
292 mov %r12, frame_GPRSAVE +8*1(%rsp)
293 mov %r13, frame_GPRSAVE +8*2(%rsp)
294 mov %r14, frame_GPRSAVE +8*3(%rsp)
295 mov %r15, frame_GPRSAVE +8*4(%rsp)
299 # Load state variables
311 # (80 rounds) / (2 rounds/iteration) + (1 iteration)
312 # +1 iteration because the scheduler leads hashing by 1 iteration
315 vmovdqa XMM_QWORD_BSWAP(%rip), %xmm1
316 vmovdqu MSG(t), %xmm0
317 vpshufb %xmm1, %xmm0, %xmm0 # BSWAP
318 vmovdqa %xmm0, W_t(t) # Store Scheduled Pair
319 vpaddq K_t(t), %xmm0, %xmm0 # Compute W[t]+K[t]
320 vmovdqa %xmm0, WK_2(t) # Store into WK for rounds
322 # BSWAP 2 QWORDS# Compute 2 Rounds
323 vmovdqu MSG(t), %xmm0
324 vpshufb %xmm1, %xmm0, %xmm0 # BSWAP
325 SHA512_Round t-2 # Round t-2
326 vmovdqa %xmm0, W_t(t) # Store Scheduled Pair
327 vpaddq K_t(t), %xmm0, %xmm0 # Compute W[t]+K[t]
328 SHA512_Round t-1 # Round t-1
329 vmovdqa %xmm0, WK_2(t)# Store W[t]+K[t] into WK
331 # Schedule 2 QWORDS# Compute 2 Rounds
332 SHA512_2Sched_2Round_avx t
351 # Advance to next message block
357 mov frame_GPRSAVE(%rsp), %rbx
358 mov frame_GPRSAVE +8*1(%rsp), %r12
359 mov frame_GPRSAVE +8*2(%rsp), %r13
360 mov frame_GPRSAVE +8*3(%rsp), %r14
361 mov frame_GPRSAVE +8*4(%rsp), %r15
363 # Restore Stack Pointer
364 mov frame_RSPSAVE(%rsp), %rsp
368 ENDPROC(sha512_transform_avx)
370 ########################################################################
377 # Mask for byte-swapping a couple of qwords in an XMM register using (v)pshufb.
379 .octa 0x08090a0b0c0d0e0f0001020304050607
381 # K[t] used in SHA512 hashing
383 .quad 0x428a2f98d728ae22,0x7137449123ef65cd
384 .quad 0xb5c0fbcfec4d3b2f,0xe9b5dba58189dbbc
385 .quad 0x3956c25bf348b538,0x59f111f1b605d019
386 .quad 0x923f82a4af194f9b,0xab1c5ed5da6d8118
387 .quad 0xd807aa98a3030242,0x12835b0145706fbe
388 .quad 0x243185be4ee4b28c,0x550c7dc3d5ffb4e2
389 .quad 0x72be5d74f27b896f,0x80deb1fe3b1696b1
390 .quad 0x9bdc06a725c71235,0xc19bf174cf692694
391 .quad 0xe49b69c19ef14ad2,0xefbe4786384f25e3
392 .quad 0x0fc19dc68b8cd5b5,0x240ca1cc77ac9c65
393 .quad 0x2de92c6f592b0275,0x4a7484aa6ea6e483
394 .quad 0x5cb0a9dcbd41fbd4,0x76f988da831153b5
395 .quad 0x983e5152ee66dfab,0xa831c66d2db43210
396 .quad 0xb00327c898fb213f,0xbf597fc7beef0ee4
397 .quad 0xc6e00bf33da88fc2,0xd5a79147930aa725
398 .quad 0x06ca6351e003826f,0x142929670a0e6e70
399 .quad 0x27b70a8546d22ffc,0x2e1b21385c26c926
400 .quad 0x4d2c6dfc5ac42aed,0x53380d139d95b3df
401 .quad 0x650a73548baf63de,0x766a0abb3c77b2a8
402 .quad 0x81c2c92e47edaee6,0x92722c851482353b
403 .quad 0xa2bfe8a14cf10364,0xa81a664bbc423001
404 .quad 0xc24b8b70d0f89791,0xc76c51a30654be30
405 .quad 0xd192e819d6ef5218,0xd69906245565a910
406 .quad 0xf40e35855771202a,0x106aa07032bbd1b8
407 .quad 0x19a4c116b8d2d0c8,0x1e376c085141ab53
408 .quad 0x2748774cdf8eeb99,0x34b0bcb5e19b48a8
409 .quad 0x391c0cb3c5c95a63,0x4ed8aa4ae3418acb
410 .quad 0x5b9cca4f7763e373,0x682e6ff3d6b2b8a3
411 .quad 0x748f82ee5defb2fc,0x78a5636f43172f60
412 .quad 0x84c87814a1f0ab72,0x8cc702081a6439ec
413 .quad 0x90befffa23631e28,0xa4506cebde82bde9
414 .quad 0xbef9a3f7b2c67915,0xc67178f2e372532b
415 .quad 0xca273eceea26619c,0xd186b8c721c0c207
416 .quad 0xeada7dd6cde0eb1e,0xf57d4f7fee6ed178
417 .quad 0x06f067aa72176fba,0x0a637dc5a2c898a6
418 .quad 0x113f9804bef90dae,0x1b710b35131c471b
419 .quad 0x28db77f523047d84,0x32caab7b40c72493
420 .quad 0x3c9ebe0a15c9bebc,0x431d67c49c100d4c
421 .quad 0x4cc5d4becb3e42b6,0x597f299cfc657e2a
422 .quad 0x5fcb6fab3ad6faec,0x6c44198c4a475817