2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
16 * Copyright (C) 2007 Alan Stern
17 * Copyright (C) 2009 IBM Corporation
18 * Copyright (C) 2009 Frederic Weisbecker <fweisbec@gmail.com>
20 * Authors: Alan Stern <stern@rowland.harvard.edu>
21 * K.Prasad <prasad@linux.vnet.ibm.com>
22 * Frederic Weisbecker <fweisbec@gmail.com>
26 * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
27 * using the CPU's debug registers.
30 #include <linux/perf_event.h>
31 #include <linux/hw_breakpoint.h>
32 #include <linux/irqflags.h>
33 #include <linux/notifier.h>
34 #include <linux/kallsyms.h>
35 #include <linux/kprobes.h>
36 #include <linux/percpu.h>
37 #include <linux/kdebug.h>
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/sched.h>
41 #include <linux/smp.h>
43 #include <asm/hw_breakpoint.h>
44 #include <asm/processor.h>
45 #include <asm/debugreg.h>
47 /* Per cpu debug control register value */
48 DEFINE_PER_CPU(unsigned long, cpu_dr7
);
49 EXPORT_PER_CPU_SYMBOL(cpu_dr7
);
51 /* Per cpu debug address registers values */
52 static DEFINE_PER_CPU(unsigned long, cpu_debugreg
[HBP_NUM
]);
55 * Stores the breakpoints currently in use on each breakpoint address
56 * register for each cpus
58 static DEFINE_PER_CPU(struct perf_event
*, bp_per_reg
[HBP_NUM
]);
61 static inline unsigned long
62 __encode_dr7(int drnum
, unsigned int len
, unsigned int type
)
64 unsigned long bp_info
;
66 bp_info
= (len
| type
) & 0xf;
67 bp_info
<<= (DR_CONTROL_SHIFT
+ drnum
* DR_CONTROL_SIZE
);
68 bp_info
|= (DR_GLOBAL_ENABLE
<< (drnum
* DR_ENABLE_SIZE
));
74 * Encode the length, type, Exact, and Enable bits for a particular breakpoint
75 * as stored in debug register 7.
77 unsigned long encode_dr7(int drnum
, unsigned int len
, unsigned int type
)
79 return __encode_dr7(drnum
, len
, type
) | DR_GLOBAL_SLOWDOWN
;
83 * Decode the length and type bits for a particular breakpoint as
84 * stored in debug register 7. Return the "enabled" status.
86 int decode_dr7(unsigned long dr7
, int bpnum
, unsigned *len
, unsigned *type
)
88 int bp_info
= dr7
>> (DR_CONTROL_SHIFT
+ bpnum
* DR_CONTROL_SIZE
);
90 *len
= (bp_info
& 0xc) | 0x40;
91 *type
= (bp_info
& 0x3) | 0x80;
93 return (dr7
>> (bpnum
* DR_ENABLE_SIZE
)) & 0x3;
97 * Install a perf counter breakpoint.
99 * We seek a free debug address register and use it for this
100 * breakpoint. Eventually we enable it in the debug control register.
102 * Atomic: we hold the counter->ctx->lock and we only handle variables
103 * and registers local to this cpu.
105 int arch_install_hw_breakpoint(struct perf_event
*bp
)
107 struct arch_hw_breakpoint
*info
= counter_arch_bp(bp
);
111 for (i
= 0; i
< HBP_NUM
; i
++) {
112 struct perf_event
**slot
= this_cpu_ptr(&bp_per_reg
[i
]);
120 if (WARN_ONCE(i
== HBP_NUM
, "Can't find any breakpoint slot"))
123 set_debugreg(info
->address
, i
);
124 __this_cpu_write(cpu_debugreg
[i
], info
->address
);
126 dr7
= this_cpu_ptr(&cpu_dr7
);
127 *dr7
|= encode_dr7(i
, info
->len
, info
->type
);
129 set_debugreg(*dr7
, 7);
131 set_dr_addr_mask(info
->mask
, i
);
137 * Uninstall the breakpoint contained in the given counter.
139 * First we search the debug address register it uses and then we disable
142 * Atomic: we hold the counter->ctx->lock and we only handle variables
143 * and registers local to this cpu.
145 void arch_uninstall_hw_breakpoint(struct perf_event
*bp
)
147 struct arch_hw_breakpoint
*info
= counter_arch_bp(bp
);
151 for (i
= 0; i
< HBP_NUM
; i
++) {
152 struct perf_event
**slot
= this_cpu_ptr(&bp_per_reg
[i
]);
160 if (WARN_ONCE(i
== HBP_NUM
, "Can't find any breakpoint slot"))
163 dr7
= this_cpu_ptr(&cpu_dr7
);
164 *dr7
&= ~__encode_dr7(i
, info
->len
, info
->type
);
166 set_debugreg(*dr7
, 7);
168 set_dr_addr_mask(0, i
);
172 * Check for virtual address in kernel space.
174 int arch_check_bp_in_kernelspace(struct perf_event
*bp
)
178 struct arch_hw_breakpoint
*info
= counter_arch_bp(bp
);
181 len
= bp
->attr
.bp_len
;
184 * We don't need to worry about va + len - 1 overflowing:
185 * we already require that va is aligned to a multiple of len.
187 return (va
>= TASK_SIZE_MAX
) || ((va
+ len
- 1) >= TASK_SIZE_MAX
);
190 int arch_bp_generic_fields(int x86_len
, int x86_type
,
191 int *gen_len
, int *gen_type
)
195 case X86_BREAKPOINT_EXECUTE
:
196 if (x86_len
!= X86_BREAKPOINT_LEN_X
)
199 *gen_type
= HW_BREAKPOINT_X
;
200 *gen_len
= sizeof(long);
202 case X86_BREAKPOINT_WRITE
:
203 *gen_type
= HW_BREAKPOINT_W
;
205 case X86_BREAKPOINT_RW
:
206 *gen_type
= HW_BREAKPOINT_W
| HW_BREAKPOINT_R
;
214 case X86_BREAKPOINT_LEN_1
:
215 *gen_len
= HW_BREAKPOINT_LEN_1
;
217 case X86_BREAKPOINT_LEN_2
:
218 *gen_len
= HW_BREAKPOINT_LEN_2
;
220 case X86_BREAKPOINT_LEN_4
:
221 *gen_len
= HW_BREAKPOINT_LEN_4
;
224 case X86_BREAKPOINT_LEN_8
:
225 *gen_len
= HW_BREAKPOINT_LEN_8
;
236 static int arch_build_bp_info(struct perf_event
*bp
)
238 struct arch_hw_breakpoint
*info
= counter_arch_bp(bp
);
240 info
->address
= bp
->attr
.bp_addr
;
243 switch (bp
->attr
.bp_type
) {
244 case HW_BREAKPOINT_W
:
245 info
->type
= X86_BREAKPOINT_WRITE
;
247 case HW_BREAKPOINT_W
| HW_BREAKPOINT_R
:
248 info
->type
= X86_BREAKPOINT_RW
;
250 case HW_BREAKPOINT_X
:
252 * We don't allow kernel breakpoints in places that are not
253 * acceptable for kprobes. On non-kprobes kernels, we don't
254 * allow kernel breakpoints at all.
256 if (bp
->attr
.bp_addr
>= TASK_SIZE_MAX
) {
257 #ifdef CONFIG_KPROBES
258 if (within_kprobe_blacklist(bp
->attr
.bp_addr
))
265 info
->type
= X86_BREAKPOINT_EXECUTE
;
267 * x86 inst breakpoints need to have a specific undefined len.
268 * But we still need to check userspace is not trying to setup
269 * an unsupported length, to get a range breakpoint for example.
271 if (bp
->attr
.bp_len
== sizeof(long)) {
272 info
->len
= X86_BREAKPOINT_LEN_X
;
282 switch (bp
->attr
.bp_len
) {
283 case HW_BREAKPOINT_LEN_1
:
284 info
->len
= X86_BREAKPOINT_LEN_1
;
286 case HW_BREAKPOINT_LEN_2
:
287 info
->len
= X86_BREAKPOINT_LEN_2
;
289 case HW_BREAKPOINT_LEN_4
:
290 info
->len
= X86_BREAKPOINT_LEN_4
;
293 case HW_BREAKPOINT_LEN_8
:
294 info
->len
= X86_BREAKPOINT_LEN_8
;
298 /* AMD range breakpoint */
299 if (!is_power_of_2(bp
->attr
.bp_len
))
301 if (bp
->attr
.bp_addr
& (bp
->attr
.bp_len
- 1))
304 if (!boot_cpu_has(X86_FEATURE_BPEXT
))
308 * It's impossible to use a range breakpoint to fake out
309 * user vs kernel detection because bp_len - 1 can't
310 * have the high bit set. If we ever allow range instruction
311 * breakpoints, then we'll have to check for kprobe-blacklisted
312 * addresses anywhere in the range.
314 info
->mask
= bp
->attr
.bp_len
- 1;
315 info
->len
= X86_BREAKPOINT_LEN_1
;
322 * Validate the arch-specific HW Breakpoint register settings
324 int arch_validate_hwbkpt_settings(struct perf_event
*bp
)
326 struct arch_hw_breakpoint
*info
= counter_arch_bp(bp
);
331 ret
= arch_build_bp_info(bp
);
336 case X86_BREAKPOINT_LEN_1
:
341 case X86_BREAKPOINT_LEN_2
:
344 case X86_BREAKPOINT_LEN_4
:
348 case X86_BREAKPOINT_LEN_8
:
357 * Check that the low-order bits of the address are appropriate
358 * for the alignment implied by len.
360 if (info
->address
& align
)
367 * Dump the debug register contents to the user.
368 * We can't dump our per cpu values because it
369 * may contain cpu wide breakpoint, something that
370 * doesn't belong to the current task.
372 * TODO: include non-ptrace user breakpoints (perf)
374 void aout_dump_debugregs(struct user
*dump
)
378 struct perf_event
*bp
;
379 struct arch_hw_breakpoint
*info
;
380 struct thread_struct
*thread
= ¤t
->thread
;
382 for (i
= 0; i
< HBP_NUM
; i
++) {
383 bp
= thread
->ptrace_bps
[i
];
385 if (bp
&& !bp
->attr
.disabled
) {
386 dump
->u_debugreg
[i
] = bp
->attr
.bp_addr
;
387 info
= counter_arch_bp(bp
);
388 dr7
|= encode_dr7(i
, info
->len
, info
->type
);
390 dump
->u_debugreg
[i
] = 0;
394 dump
->u_debugreg
[4] = 0;
395 dump
->u_debugreg
[5] = 0;
396 dump
->u_debugreg
[6] = current
->thread
.debugreg6
;
398 dump
->u_debugreg
[7] = dr7
;
400 EXPORT_SYMBOL_GPL(aout_dump_debugregs
);
403 * Release the user breakpoints used by ptrace
405 void flush_ptrace_hw_breakpoint(struct task_struct
*tsk
)
408 struct thread_struct
*t
= &tsk
->thread
;
410 for (i
= 0; i
< HBP_NUM
; i
++) {
411 unregister_hw_breakpoint(t
->ptrace_bps
[i
]);
412 t
->ptrace_bps
[i
] = NULL
;
419 void hw_breakpoint_restore(void)
421 set_debugreg(__this_cpu_read(cpu_debugreg
[0]), 0);
422 set_debugreg(__this_cpu_read(cpu_debugreg
[1]), 1);
423 set_debugreg(__this_cpu_read(cpu_debugreg
[2]), 2);
424 set_debugreg(__this_cpu_read(cpu_debugreg
[3]), 3);
425 set_debugreg(current
->thread
.debugreg6
, 6);
426 set_debugreg(__this_cpu_read(cpu_dr7
), 7);
428 EXPORT_SYMBOL_GPL(hw_breakpoint_restore
);
431 * Handle debug exception notifications.
433 * Return value is either NOTIFY_STOP or NOTIFY_DONE as explained below.
435 * NOTIFY_DONE returned if one of the following conditions is true.
436 * i) When the causative address is from user-space and the exception
437 * is a valid one, i.e. not triggered as a result of lazy debug register
439 * ii) When there are more bits than trap<n> set in DR6 register (such
440 * as BD, BS or BT) indicating that more than one debug condition is
441 * met and requires some more action in do_debug().
443 * NOTIFY_STOP returned for all other cases
446 static int hw_breakpoint_handler(struct die_args
*args
)
448 int i
, cpu
, rc
= NOTIFY_STOP
;
449 struct perf_event
*bp
;
450 unsigned long dr7
, dr6
;
451 unsigned long *dr6_p
;
453 /* The DR6 value is pointed by args->err */
454 dr6_p
= (unsigned long *)ERR_PTR(args
->err
);
457 /* If it's a single step, TRAP bits are random */
461 /* Do an early return if no trap bits are set in DR6 */
462 if ((dr6
& DR_TRAP_BITS
) == 0)
465 get_debugreg(dr7
, 7);
466 /* Disable breakpoints during exception handling */
467 set_debugreg(0UL, 7);
469 * Assert that local interrupts are disabled
470 * Reset the DRn bits in the virtualized register value.
471 * The ptrace trigger routine will add in whatever is needed.
473 current
->thread
.debugreg6
&= ~DR_TRAP_BITS
;
476 /* Handle all the breakpoints that were triggered */
477 for (i
= 0; i
< HBP_NUM
; ++i
) {
478 if (likely(!(dr6
& (DR_TRAP0
<< i
))))
482 * The counter may be concurrently released but that can only
483 * occur from a call_rcu() path. We can then safely fetch
484 * the breakpoint, use its callback, touch its counter
485 * while we are in an rcu_read_lock() path.
489 bp
= per_cpu(bp_per_reg
[i
], cpu
);
491 * Reset the 'i'th TRAP bit in dr6 to denote completion of
494 (*dr6_p
) &= ~(DR_TRAP0
<< i
);
496 * bp can be NULL due to lazy debug register switching
497 * or due to concurrent perf counter removing.
504 perf_bp_event(bp
, args
->regs
);
507 * Set up resume flag to avoid breakpoint recursion when
508 * returning back to origin.
510 if (bp
->hw
.info
.type
== X86_BREAKPOINT_EXECUTE
)
511 args
->regs
->flags
|= X86_EFLAGS_RF
;
516 * Further processing in do_debug() is needed for a) user-space
517 * breakpoints (to generate signals) and b) when the system has
518 * taken exception due to multiple causes
520 if ((current
->thread
.debugreg6
& DR_TRAP_BITS
) ||
521 (dr6
& (~DR_TRAP_BITS
)))
524 set_debugreg(dr7
, 7);
531 * Handle debug exception notifications.
533 int hw_breakpoint_exceptions_notify(
534 struct notifier_block
*unused
, unsigned long val
, void *data
)
536 if (val
!= DIE_DEBUG
)
539 return hw_breakpoint_handler(data
);
542 void hw_breakpoint_pmu_read(struct perf_event
*bp
)