include/kvm/arm_vgic.h

   1 /*
   2  * Copyright (C) 2015, 2016 ARM Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16 #ifndef __KVM_ARM_VGIC_H
  17 #define __KVM_ARM_VGIC_H
  18
  19 #include <linux/kernel.h>
  20 #include <linux/kvm.h>
  21 #include <linux/irqreturn.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/static_key.h>
  24 #include <linux/types.h>
  25 #include <kvm/iodev.h>
  26 #include <linux/list.h>
  27 #include <linux/jump_label.h>
  28
  29 #include <linux/irqchip/arm-gic-v4.h>
  30
  31 #define VGIC_V3_MAX_CPUS        512
  32 #define VGIC_V2_MAX_CPUS        8
  33 #define VGIC_NR_IRQS_LEGACY     256
  34 #define VGIC_NR_SGIS            16
  35 #define VGIC_NR_PPIS            16
  36 #define VGIC_NR_PRIVATE_IRQS    (VGIC_NR_SGIS + VGIC_NR_PPIS)
  37 #define VGIC_MAX_PRIVATE        (VGIC_NR_PRIVATE_IRQS - 1)
  38 #define VGIC_MAX_SPI            1019
  39 #define VGIC_MAX_RESERVED       1023
  40 #define VGIC_MIN_LPI            8192
  41 #define KVM_IRQCHIP_NUM_PINS    (1020 - 32)
  42
  43 #define irq_is_ppi(irq) ((irq) >= VGIC_NR_SGIS && (irq) < VGIC_NR_PRIVATE_IRQS)
  44 #define irq_is_spi(irq) ((irq) >= VGIC_NR_PRIVATE_IRQS && \
  45                          (irq) <= VGIC_MAX_SPI)
  46
  47 enum vgic_type {
  48         VGIC_V2,                /* Good ol' GICv2 */
  49         VGIC_V3,                /* New fancy GICv3 */
  50 };
  51
  52 /* same for all guests, as depending only on the _host's_ GIC model */
  53 struct vgic_global {
  54         /* type of the host GIC */
  55         enum vgic_type          type;
  56
  57         /* Physical address of vgic virtual cpu interface */
  58         phys_addr_t             vcpu_base;
  59
  60         /* GICV mapping, kernel VA */
  61         void __iomem            *vcpu_base_va;
  62         /* GICV mapping, HYP VA */
  63         void __iomem            *vcpu_hyp_va;
  64
  65         /* virtual control interface mapping, kernel VA */
  66         void __iomem            *vctrl_base;
  67         /* virtual control interface mapping, HYP VA */
  68         void __iomem            *vctrl_hyp;
  69
  70         /* Number of implemented list registers */
  71         int                     nr_lr;
  72
  73         /* Maintenance IRQ number */
  74         unsigned int            maint_irq;
  75
  76         /* maximum number of VCPUs allowed (GICv2 limits us to 8) */
  77         int                     max_gic_vcpus;
  78
  79         /* Only needed for the legacy KVM_CREATE_IRQCHIP */
  80         bool                    can_emulate_gicv2;
  81
  82         /* Hardware has GICv4? */
  83         bool                    has_gicv4;
  84
  85         /* GIC system register CPU interface */
  86         struct static_key_false gicv3_cpuif;
  87
  88         u32                     ich_vtr_el2;
  89 };
  90
  91 extern struct vgic_global kvm_vgic_global_state;
  92
  93 #define VGIC_V2_MAX_LRS         (1 << 6)
  94 #define VGIC_V3_MAX_LRS         16
  95 #define VGIC_V3_LR_INDEX(lr)    (VGIC_V3_MAX_LRS - 1 - lr)
  96
  97 enum vgic_irq_config {
  98         VGIC_CONFIG_EDGE = 0,
  99         VGIC_CONFIG_LEVEL
 100 };
 101
 102 struct vgic_irq {
 103         spinlock_t irq_lock;            /* Protects the content of the struct */
 104         struct list_head lpi_list;      /* Used to link all LPIs together */
 105         struct list_head ap_list;
 106
 107         struct kvm_vcpu *vcpu;          /* SGIs and PPIs: The VCPU
 108                                          * SPIs and LPIs: The VCPU whose ap_list
 109                                          * this is queued on.
 110                                          */
 111
 112         struct kvm_vcpu *target_vcpu;   /* The VCPU that this interrupt should
 113                                          * be sent to, as a result of the
 114                                          * targets reg (v2) or the
 115                                          * affinity reg (v3).
 116                                          */
 117
 118         u32 intid;                      /* Guest visible INTID */
 119         bool line_level;                /* Level only */
 120         bool pending_latch;             /* The pending latch state used to calculate
 121                                          * the pending state for both level
 122                                          * and edge triggered IRQs. */
 123         bool active;                    /* not used for LPIs */
 124         bool enabled;
 125         bool hw;                        /* Tied to HW IRQ */
 126         struct kref refcount;           /* Used for LPIs */
 127         u32 hwintid;                    /* HW INTID number */
 128         unsigned int host_irq;          /* linux irq corresponding to hwintid */
 129         union {
 130                 u8 targets;                     /* GICv2 target VCPUs mask */
 131                 u32 mpidr;                      /* GICv3 target VCPU */
 132         };
 133         u8 source;                      /* GICv2 SGIs only */
 134         u8 active_source;               /* GICv2 SGIs only */
 135         u8 priority;
 136         enum vgic_irq_config config;    /* Level or edge */
 137
 138         /*
 139          * Callback function pointer to in-kernel devices that can tell us the
 140          * state of the input level of mapped level-triggered IRQ faster than
 141          * peaking into the physical GIC.
 142          *
 143          * Always called in non-preemptible section and the functions can use
 144          * kvm_arm_get_running_vcpu() to get the vcpu pointer for private
 145          * IRQs.
 146          */
 147         bool (*get_input_level)(int vintid);
 148
 149         void *owner;                    /* Opaque pointer to reserve an interrupt
 150                                            for in-kernel devices. */
 151 };
 152
 153 struct vgic_register_region;
 154 struct vgic_its;
 155
 156 enum iodev_type {
 157         IODEV_CPUIF,
 158         IODEV_DIST,
 159         IODEV_REDIST,
 160         IODEV_ITS
 161 };
 162
 163 struct vgic_io_device {
 164         gpa_t base_addr;
 165         union {
 166                 struct kvm_vcpu *redist_vcpu;
 167                 struct vgic_its *its;
 168         };
 169         const struct vgic_register_region *regions;
 170         enum iodev_type iodev_type;
 171         int nr_regions;
 172         struct kvm_io_device dev;
 173 };
 174
 175 struct vgic_its {
 176         /* The base address of the ITS control register frame */
 177         gpa_t                   vgic_its_base;
 178
 179         bool                    enabled;
 180         struct vgic_io_device   iodev;
 181         struct kvm_device       *dev;
 182
 183         /* These registers correspond to GITS_BASER{0,1} */
 184         u64                     baser_device_table;
 185         u64                     baser_coll_table;
 186
 187         /* Protects the command queue */
 188         struct mutex            cmd_lock;
 189         u64                     cbaser;
 190         u32                     creadr;
 191         u32                     cwriter;
 192
 193         /* migration ABI revision in use */
 194         u32                     abi_rev;
 195
 196         /* Protects the device and collection lists */
 197         struct mutex            its_lock;
 198         struct list_head        device_list;
 199         struct list_head        collection_list;
 200 };
 201
 202 struct vgic_state_iter;
 203
 204 struct vgic_redist_region {
 205         u32 index;
 206         gpa_t base;
 207         u32 count; /* number of redistributors or 0 if single region */
 208         u32 free_index; /* index of the next free redistributor */
 209         struct list_head list;
 210 };
 211
 212 struct vgic_dist {
 213         bool                    in_kernel;
 214         bool                    ready;
 215         bool                    initialized;
 216
 217         /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
 218         u32                     vgic_model;
 219
 220         /* Do injected MSIs require an additional device ID? */
 221         bool                    msis_require_devid;
 222
 223         int                     nr_spis;
 224
 225         /* base addresses in guest physical address space: */
 226         gpa_t                   vgic_dist_base;         /* distributor */
 227         union {
 228                 /* either a GICv2 CPU interface */
 229                 gpa_t                   vgic_cpu_base;
 230                 /* or a number of GICv3 redistributor regions */
 231                 struct list_head rd_regions;
 232         };
 233
 234         /* distributor enabled */
 235         bool                    enabled;
 236
 237         struct vgic_irq         *spis;
 238
 239         struct vgic_io_device   dist_iodev;
 240
 241         bool                    has_its;
 242
 243         /*
 244          * Contains the attributes and gpa of the LPI configuration table.
 245          * Since we report GICR_TYPER.CommonLPIAff as 0b00, we can share
 246          * one address across all redistributors.
 247          * GICv3 spec: 6.1.2 "LPI Configuration tables"
 248          */
 249         u64                     propbaser;
 250
 251         /* Protects the lpi_list and the count value below. */
 252         spinlock_t              lpi_list_lock;
 253         struct list_head        lpi_list_head;
 254         int                     lpi_list_count;
 255
 256         /* used by vgic-debug */
 257         struct vgic_state_iter *iter;
 258
 259         /*
 260          * GICv4 ITS per-VM data, containing the IRQ domain, the VPE
 261          * array, the property table pointer as well as allocation
 262          * data. This essentially ties the Linux IRQ core and ITS
 263          * together, and avoids leaking KVM's data structures anywhere
 264          * else.
 265          */
 266         struct its_vm           its_vm;
 267 };
 268
 269 struct vgic_v2_cpu_if {
 270         u32             vgic_hcr;
 271         u32             vgic_vmcr;
 272         u32             vgic_apr;
 273         u32             vgic_lr[VGIC_V2_MAX_LRS];
 274 };
 275
 276 struct vgic_v3_cpu_if {
 277         u32             vgic_hcr;
 278         u32             vgic_vmcr;
 279         u32             vgic_sre;       /* Restored only, change ignored */
 280         u32             vgic_ap0r[4];
 281         u32             vgic_ap1r[4];
 282         u64             vgic_lr[VGIC_V3_MAX_LRS];
 283
 284         /*
 285          * GICv4 ITS per-VPE data, containing the doorbell IRQ, the
 286          * pending table pointer, the its_vm pointer and a few other
 287          * HW specific things. As for the its_vm structure, this is
 288          * linking the Linux IRQ subsystem and the ITS together.
 289          */
 290         struct its_vpe  its_vpe;
 291 };
 292
 293 struct vgic_cpu {
 294         /* CPU vif control registers for world switch */
 295         union {
 296                 struct vgic_v2_cpu_if   vgic_v2;
 297                 struct vgic_v3_cpu_if   vgic_v3;
 298         };
 299
 300         unsigned int used_lrs;
 301         struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS];
 302
 303         spinlock_t ap_list_lock;        /* Protects the ap_list */
 304
 305         /*
 306          * List of IRQs that this VCPU should consider because they are either
 307          * Active or Pending (hence the name; AP list), or because they recently
 308          * were one of the two and need to be migrated off this list to another
 309          * VCPU.
 310          */
 311         struct list_head ap_list_head;
 312
 313         /*
 314          * Members below are used with GICv3 emulation only and represent
 315          * parts of the redistributor.
 316          */
 317         struct vgic_io_device   rd_iodev;
 318         struct vgic_io_device   sgi_iodev;
 319         struct vgic_redist_region *rdreg;
 320
 321         /* Contains the attributes and gpa of the LPI pending tables. */
 322         u64 pendbaser;
 323
 324         bool lpis_enabled;
 325
 326         /* Cache guest priority bits */
 327         u32 num_pri_bits;
 328
 329         /* Cache guest interrupt ID bits */
 330         u32 num_id_bits;
 331 };
 332
 333 extern struct static_key_false vgic_v2_cpuif_trap;
 334 extern struct static_key_false vgic_v3_cpuif_trap;
 335
 336 int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
 337 void kvm_vgic_early_init(struct kvm *kvm);
 338 int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu);
 339 int kvm_vgic_create(struct kvm *kvm, u32 type);
 340 void kvm_vgic_destroy(struct kvm *kvm);
 341 void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
 342 int kvm_vgic_map_resources(struct kvm *kvm);
 343 int kvm_vgic_hyp_init(void);
 344 void kvm_vgic_init_cpu_hardware(void);
 345
 346 int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
 347                         bool level, void *owner);
 348 int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, unsigned int host_irq,
 349                           u32 vintid, bool (*get_input_level)(int vindid));
 350 int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int vintid);
 351 bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int vintid);
 352
 353 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
 354
 355 void kvm_vgic_load(struct kvm_vcpu *vcpu);
 356 void kvm_vgic_put(struct kvm_vcpu *vcpu);
 357
 358 #define irqchip_in_kernel(k)    (!!((k)->arch.vgic.in_kernel))
 359 #define vgic_initialized(k)     ((k)->arch.vgic.initialized)
 360 #define vgic_ready(k)           ((k)->arch.vgic.ready)
 361 #define vgic_valid_spi(k, i)    (((i) >= VGIC_NR_PRIVATE_IRQS) && \
 362                         ((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS))
 363
 364 bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu);
 365 void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
 366 void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
 367 void kvm_vgic_reset_mapped_irq(struct kvm_vcpu *vcpu, u32 vintid);
 368
 369 void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg);
 370
 371 /**
 372  * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
 373  *
 374  * The host's GIC naturally limits the maximum amount of VCPUs a guest
 375  * can use.
 376  */
 377 static inline int kvm_vgic_get_max_vcpus(void)
 378 {
 379         return kvm_vgic_global_state.max_gic_vcpus;
 380 }
 381
 382 int kvm_send_userspace_msi(struct kvm *kvm, struct kvm_msi *msi);
 383
 384 /**
 385  * kvm_vgic_setup_default_irq_routing:
 386  * Setup a default flat gsi routing table mapping all SPIs
 387  */
 388 int kvm_vgic_setup_default_irq_routing(struct kvm *kvm);
 389
 390 int kvm_vgic_set_owner(struct kvm_vcpu *vcpu, unsigned int intid, void *owner);
 391
 392 struct kvm_kernel_irq_routing_entry;
 393
 394 int kvm_vgic_v4_set_forwarding(struct kvm *kvm, int irq,
 395                                struct kvm_kernel_irq_routing_entry *irq_entry);
 396
 397 int kvm_vgic_v4_unset_forwarding(struct kvm *kvm, int irq,
 398                                  struct kvm_kernel_irq_routing_entry *irq_entry);
 399
 400 void kvm_vgic_v4_enable_doorbell(struct kvm_vcpu *vcpu);
 401 void kvm_vgic_v4_disable_doorbell(struct kvm_vcpu *vcpu);
 402
 403 #endif /* __KVM_ARM_VGIC_H */