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Linux 4.8-rc8
[linux/fpc-iii.git] / arch / sparc / mm / init_64.c
blob65457c9f1365f07b0b9d9337c897983234d85652
1 /*
2 * arch/sparc64/mm/init.c
3 *
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8 #include <linux/module.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/string.h>
12 #include <linux/init.h>
13 #include <linux/bootmem.h>
14 #include <linux/mm.h>
15 #include <linux/hugetlb.h>
16 #include <linux/initrd.h>
17 #include <linux/swap.h>
18 #include <linux/pagemap.h>
19 #include <linux/poison.h>
20 #include <linux/fs.h>
21 #include <linux/seq_file.h>
22 #include <linux/kprobes.h>
23 #include <linux/cache.h>
24 #include <linux/sort.h>
25 #include <linux/ioport.h>
26 #include <linux/percpu.h>
27 #include <linux/memblock.h>
28 #include <linux/mmzone.h>
29 #include <linux/gfp.h>
30
31 #include <asm/head.h>
32 #include <asm/page.h>
33 #include <asm/pgalloc.h>
34 #include <asm/pgtable.h>
35 #include <asm/oplib.h>
36 #include <asm/iommu.h>
37 #include <asm/io.h>
38 #include <asm/uaccess.h>
39 #include <asm/mmu_context.h>
40 #include <asm/tlbflush.h>
41 #include <asm/dma.h>
42 #include <asm/starfire.h>
43 #include <asm/tlb.h>
44 #include <asm/spitfire.h>
45 #include <asm/sections.h>
46 #include <asm/tsb.h>
47 #include <asm/hypervisor.h>
48 #include <asm/prom.h>
49 #include <asm/mdesc.h>
50 #include <asm/cpudata.h>
51 #include <asm/setup.h>
52 #include <asm/irq.h>
53
54 #include "init_64.h"
55
56 unsigned long kern_linear_pte_xor[4] __read_mostly;
57 static unsigned long page_cache4v_flag;
58
59 /* A bitmap, two bits for every 256MB of physical memory. These two
60 * bits determine what page size we use for kernel linear
61 * translations. They form an index into kern_linear_pte_xor[]. The
62 * value in the indexed slot is XOR'd with the TLB miss virtual
63 * address to form the resulting TTE. The mapping is:
64 *
65 * 0 ==> 4MB
66 * 1 ==> 256MB
67 * 2 ==> 2GB
68 * 3 ==> 16GB
69 *
70 * All sun4v chips support 256MB pages. Only SPARC-T4 and later
71 * support 2GB pages, and hopefully future cpus will support the 16GB
72 * pages as well. For slots 2 and 3, we encode a 256MB TTE xor there
73 * if these larger page sizes are not supported by the cpu.
74 *
75 * It would be nice to determine this from the machine description
76 * 'cpu' properties, but we need to have this table setup before the
77 * MDESC is initialized.
78 */
79
80 #ifndef CONFIG_DEBUG_PAGEALLOC
81 /* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings.
82 * Space is allocated for this right after the trap table in
83 * arch/sparc64/kernel/head.S
84 */
85 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
86 #endif
87 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
88
89 static unsigned long cpu_pgsz_mask;
90
91 #define MAX_BANKS 1024
92
93 static struct linux_prom64_registers pavail[MAX_BANKS];
94 static int pavail_ents;
95
96 u64 numa_latency[MAX_NUMNODES][MAX_NUMNODES];
97
98 static int cmp_p64(const void *a, const void *b)
99 {
100 const struct linux_prom64_registers *x = a, *y = b;
101
102 if (x->phys_addr > y->phys_addr)
103 return 1;
104 if (x->phys_addr < y->phys_addr)
105 return -1;
106 return 0;
107 }
108
109 static void __init read_obp_memory(const char *property,
110 struct linux_prom64_registers *regs,
111 int *num_ents)
112 {
113 phandle node = prom_finddevice("/memory");
114 int prop_size = prom_getproplen(node, property);
115 int ents, ret, i;
116
117 ents = prop_size / sizeof(struct linux_prom64_registers);
118 if (ents > MAX_BANKS) {
119 prom_printf("The machine has more %s property entries than "
120 "this kernel can support (%d).\n",
121 property, MAX_BANKS);
122 prom_halt();
123 }
124
125 ret = prom_getproperty(node, property, (char *) regs, prop_size);
126 if (ret == -1) {
127 prom_printf("Couldn't get %s property from /memory.\n",
128 property);
129 prom_halt();
130 }
131
132 /* Sanitize what we got from the firmware, by page aligning
133 * everything.
134 */
135 for (i = 0; i < ents; i++) {
136 unsigned long base, size;
137
138 base = regs[i].phys_addr;
139 size = regs[i].reg_size;
140
141 size &= PAGE_MASK;
142 if (base & ~PAGE_MASK) {
143 unsigned long new_base = PAGE_ALIGN(base);
144
145 size -= new_base - base;
146 if ((long) size < 0L)
147 size = 0UL;
148 base = new_base;
149 }
150 if (size == 0UL) {
151 /* If it is empty, simply get rid of it.
152 * This simplifies the logic of the other
153 * functions that process these arrays.
154 */
155 memmove(&regs[i], &regs[i + 1],
156 (ents - i - 1) * sizeof(regs[0]));
157 i--;
158 ents--;
159 continue;
160 }
161 regs[i].phys_addr = base;
162 regs[i].reg_size = size;
163 }
164
165 *num_ents = ents;
166
167 sort(regs, ents, sizeof(struct linux_prom64_registers),
168 cmp_p64, NULL);
169 }
170
171 /* Kernel physical address base and size in bytes. */
172 unsigned long kern_base __read_mostly;
173 unsigned long kern_size __read_mostly;
174
175 /* Initial ramdisk setup */
176 extern unsigned long sparc_ramdisk_image64;
177 extern unsigned int sparc_ramdisk_image;
178 extern unsigned int sparc_ramdisk_size;
179
180 struct page *mem_map_zero __read_mostly;
181 EXPORT_SYMBOL(mem_map_zero);
182
183 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
184
185 unsigned long sparc64_kern_pri_context __read_mostly;
186 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
187 unsigned long sparc64_kern_sec_context __read_mostly;
188
189 int num_kernel_image_mappings;
190
191 #ifdef CONFIG_DEBUG_DCFLUSH
192 atomic_t dcpage_flushes = ATOMIC_INIT(0);
193 #ifdef CONFIG_SMP
194 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
195 #endif
196 #endif
197
198 inline void flush_dcache_page_impl(struct page *page)
199 {
200 BUG_ON(tlb_type == hypervisor);
201 #ifdef CONFIG_DEBUG_DCFLUSH
202 atomic_inc(&dcpage_flushes);
203 #endif
204
205 #ifdef DCACHE_ALIASING_POSSIBLE
206 __flush_dcache_page(page_address(page),
207 ((tlb_type == spitfire) &&
208 page_mapping(page) != NULL));
209 #else
210 if (page_mapping(page) != NULL &&
211 tlb_type == spitfire)
212 __flush_icache_page(__pa(page_address(page)));
213 #endif
214 }
215
216 #define PG_dcache_dirty PG_arch_1
217 #define PG_dcache_cpu_shift 32UL
218 #define PG_dcache_cpu_mask \
219 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
220
221 #define dcache_dirty_cpu(page) \
222 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
223
224 static inline void set_dcache_dirty(struct page *page, int this_cpu)
225 {
226 unsigned long mask = this_cpu;
227 unsigned long non_cpu_bits;
228
229 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
230 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
231
232 __asm__ __volatile__("1:\n\t"
233 "ldx [%2], %%g7\n\t"
234 "and %%g7, %1, %%g1\n\t"
235 "or %%g1, %0, %%g1\n\t"
236 "casx [%2], %%g7, %%g1\n\t"
237 "cmp %%g7, %%g1\n\t"
238 "bne,pn %%xcc, 1b\n\t"
239 " nop"
240 : /* no outputs */
241 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
242 : "g1", "g7");
243 }
244
245 static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
246 {
247 unsigned long mask = (1UL << PG_dcache_dirty);
248
249 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
250 "1:\n\t"
251 "ldx [%2], %%g7\n\t"
252 "srlx %%g7, %4, %%g1\n\t"
253 "and %%g1, %3, %%g1\n\t"
254 "cmp %%g1, %0\n\t"
255 "bne,pn %%icc, 2f\n\t"
256 " andn %%g7, %1, %%g1\n\t"
257 "casx [%2], %%g7, %%g1\n\t"
258 "cmp %%g7, %%g1\n\t"
259 "bne,pn %%xcc, 1b\n\t"
260 " nop\n"
261 "2:"
262 : /* no outputs */
263 : "r" (cpu), "r" (mask), "r" (&page->flags),
264 "i" (PG_dcache_cpu_mask),
265 "i" (PG_dcache_cpu_shift)
266 : "g1", "g7");
267 }
268
269 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
270 {
271 unsigned long tsb_addr = (unsigned long) ent;
272
273 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
274 tsb_addr = __pa(tsb_addr);
275
276 __tsb_insert(tsb_addr, tag, pte);
277 }
278
279 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
280
281 static void flush_dcache(unsigned long pfn)
282 {
283 struct page *page;
284
285 page = pfn_to_page(pfn);
286 if (page) {
287 unsigned long pg_flags;
288
289 pg_flags = page->flags;
290 if (pg_flags & (1UL << PG_dcache_dirty)) {
291 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
292 PG_dcache_cpu_mask);
293 int this_cpu = get_cpu();
294
295 /* This is just to optimize away some function calls
296 * in the SMP case.
297 */
298 if (cpu == this_cpu)
299 flush_dcache_page_impl(page);
300 else
301 smp_flush_dcache_page_impl(page, cpu);
302
303 clear_dcache_dirty_cpu(page, cpu);
304
305 put_cpu();
306 }
307 }
308 }
309
310 /* mm->context.lock must be held */
311 static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index,
312 unsigned long tsb_hash_shift, unsigned long address,
313 unsigned long tte)
314 {
315 struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb;
316 unsigned long tag;
317
318 if (unlikely(!tsb))
319 return;
320
321 tsb += ((address >> tsb_hash_shift) &
322 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
323 tag = (address >> 22UL);
324 tsb_insert(tsb, tag, tte);
325 }
326
327 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
328 {
329 struct mm_struct *mm;
330 unsigned long flags;
331 pte_t pte = *ptep;
332
333 if (tlb_type != hypervisor) {
334 unsigned long pfn = pte_pfn(pte);
335
336 if (pfn_valid(pfn))
337 flush_dcache(pfn);
338 }
339
340 mm = vma->vm_mm;
341
342 /* Don't insert a non-valid PTE into the TSB, we'll deadlock. */
343 if (!pte_accessible(mm, pte))
344 return;
345
346 spin_lock_irqsave(&mm->context.lock, flags);
347
348 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
349 if ((mm->context.hugetlb_pte_count || mm->context.thp_pte_count) &&
350 is_hugetlb_pte(pte)) {
351 /* We are fabricating 8MB pages using 4MB real hw pages. */
352 pte_val(pte) |= (address & (1UL << REAL_HPAGE_SHIFT));
353 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
354 address, pte_val(pte));
355 } else
356 #endif
357 __update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT,
358 address, pte_val(pte));
359
360 spin_unlock_irqrestore(&mm->context.lock, flags);
361 }
362
363 void flush_dcache_page(struct page *page)
364 {
365 struct address_space *mapping;
366 int this_cpu;
367
368 if (tlb_type == hypervisor)
369 return;
370
371 /* Do not bother with the expensive D-cache flush if it
372 * is merely the zero page. The 'bigcore' testcase in GDB
373 * causes this case to run millions of times.
374 */
375 if (page == ZERO_PAGE(0))
376 return;
377
378 this_cpu = get_cpu();
379
380 mapping = page_mapping(page);
381 if (mapping && !mapping_mapped(mapping)) {
382 int dirty = test_bit(PG_dcache_dirty, &page->flags);
383 if (dirty) {
384 int dirty_cpu = dcache_dirty_cpu(page);
385
386 if (dirty_cpu == this_cpu)
387 goto out;
388 smp_flush_dcache_page_impl(page, dirty_cpu);
389 }
390 set_dcache_dirty(page, this_cpu);
391 } else {
392 /* We could delay the flush for the !page_mapping
393 * case too. But that case is for exec env/arg
394 * pages and those are %99 certainly going to get
395 * faulted into the tlb (and thus flushed) anyways.
396 */
397 flush_dcache_page_impl(page);
398 }
399
400 out:
401 put_cpu();
402 }
403 EXPORT_SYMBOL(flush_dcache_page);
404
405 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
406 {
407 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
408 if (tlb_type == spitfire) {
409 unsigned long kaddr;
410
411 /* This code only runs on Spitfire cpus so this is
412 * why we can assume _PAGE_PADDR_4U.
413 */
414 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
415 unsigned long paddr, mask = _PAGE_PADDR_4U;
416
417 if (kaddr >= PAGE_OFFSET)
418 paddr = kaddr & mask;
419 else {
420 pgd_t *pgdp = pgd_offset_k(kaddr);
421 pud_t *pudp = pud_offset(pgdp, kaddr);
422 pmd_t *pmdp = pmd_offset(pudp, kaddr);
423 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
424
425 paddr = pte_val(*ptep) & mask;
426 }
427 __flush_icache_page(paddr);
428 }
429 }
430 }
431 EXPORT_SYMBOL(flush_icache_range);
432
433 void mmu_info(struct seq_file *m)
434 {
435 static const char *pgsz_strings[] = {
436 "8K", "64K", "512K", "4MB", "32MB",
437 "256MB", "2GB", "16GB",
438 };
439 int i, printed;
440
441 if (tlb_type == cheetah)
442 seq_printf(m, "MMU Type\t: Cheetah\n");
443 else if (tlb_type == cheetah_plus)
444 seq_printf(m, "MMU Type\t: Cheetah+\n");
445 else if (tlb_type == spitfire)
446 seq_printf(m, "MMU Type\t: Spitfire\n");
447 else if (tlb_type == hypervisor)
448 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
449 else
450 seq_printf(m, "MMU Type\t: ???\n");
451
452 seq_printf(m, "MMU PGSZs\t: ");
453 printed = 0;
454 for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) {
455 if (cpu_pgsz_mask & (1UL << i)) {
456 seq_printf(m, "%s%s",
457 printed ? "," : "", pgsz_strings[i]);
458 printed++;
459 }
460 }
461 seq_putc(m, '\n');
462
463 #ifdef CONFIG_DEBUG_DCFLUSH
464 seq_printf(m, "DCPageFlushes\t: %d\n",
465 atomic_read(&dcpage_flushes));
466 #ifdef CONFIG_SMP
467 seq_printf(m, "DCPageFlushesXC\t: %d\n",
468 atomic_read(&dcpage_flushes_xcall));
469 #endif /* CONFIG_SMP */
470 #endif /* CONFIG_DEBUG_DCFLUSH */
471 }
472
473 struct linux_prom_translation prom_trans[512] __read_mostly;
474 unsigned int prom_trans_ents __read_mostly;
475
476 unsigned long kern_locked_tte_data;
477
478 /* The obp translations are saved based on 8k pagesize, since obp can
479 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
480 * HI_OBP_ADDRESS range are handled in ktlb.S.
481 */
482 static inline int in_obp_range(unsigned long vaddr)
483 {
484 return (vaddr >= LOW_OBP_ADDRESS &&
485 vaddr < HI_OBP_ADDRESS);
486 }
487
488 static int cmp_ptrans(const void *a, const void *b)
489 {
490 const struct linux_prom_translation *x = a, *y = b;
491
492 if (x->virt > y->virt)
493 return 1;
494 if (x->virt < y->virt)
495 return -1;
496 return 0;
497 }
498
499 /* Read OBP translations property into 'prom_trans[]'. */
500 static void __init read_obp_translations(void)
501 {
502 int n, node, ents, first, last, i;
503
504 node = prom_finddevice("/virtual-memory");
505 n = prom_getproplen(node, "translations");
506 if (unlikely(n == 0 || n == -1)) {
507 prom_printf("prom_mappings: Couldn't get size.\n");
508 prom_halt();
509 }
510 if (unlikely(n > sizeof(prom_trans))) {
511 prom_printf("prom_mappings: Size %d is too big.\n", n);
512 prom_halt();
513 }
514
515 if ((n = prom_getproperty(node, "translations",
516 (char *)&prom_trans[0],
517 sizeof(prom_trans))) == -1) {
518 prom_printf("prom_mappings: Couldn't get property.\n");
519 prom_halt();
520 }
521
522 n = n / sizeof(struct linux_prom_translation);
523
524 ents = n;
525
526 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
527 cmp_ptrans, NULL);
528
529 /* Now kick out all the non-OBP entries. */
530 for (i = 0; i < ents; i++) {
531 if (in_obp_range(prom_trans[i].virt))
532 break;
533 }
534 first = i;
535 for (; i < ents; i++) {
536 if (!in_obp_range(prom_trans[i].virt))
537 break;
538 }
539 last = i;
540
541 for (i = 0; i < (last - first); i++) {
542 struct linux_prom_translation *src = &prom_trans[i + first];
543 struct linux_prom_translation *dest = &prom_trans[i];
544
545 *dest = *src;
546 }
547 for (; i < ents; i++) {
548 struct linux_prom_translation *dest = &prom_trans[i];
549 dest->virt = dest->size = dest->data = 0x0UL;
550 }
551
552 prom_trans_ents = last - first;
553
554 if (tlb_type == spitfire) {
555 /* Clear diag TTE bits. */
556 for (i = 0; i < prom_trans_ents; i++)
557 prom_trans[i].data &= ~0x0003fe0000000000UL;
558 }
559
560 /* Force execute bit on. */
561 for (i = 0; i < prom_trans_ents; i++)
562 prom_trans[i].data |= (tlb_type == hypervisor ?
563 _PAGE_EXEC_4V : _PAGE_EXEC_4U);
564 }
565
566 static void __init hypervisor_tlb_lock(unsigned long vaddr,
567 unsigned long pte,
568 unsigned long mmu)
569 {
570 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
571
572 if (ret != 0) {
573 prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: "
574 "errors with %lx\n", vaddr, 0, pte, mmu, ret);
575 prom_halt();
576 }
577 }
578
579 static unsigned long kern_large_tte(unsigned long paddr);
580
581 static void __init remap_kernel(void)
582 {
583 unsigned long phys_page, tte_vaddr, tte_data;
584 int i, tlb_ent = sparc64_highest_locked_tlbent();
585
586 tte_vaddr = (unsigned long) KERNBASE;
587 phys_page = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
588 tte_data = kern_large_tte(phys_page);
589
590 kern_locked_tte_data = tte_data;
591
592 /* Now lock us into the TLBs via Hypervisor or OBP. */
593 if (tlb_type == hypervisor) {
594 for (i = 0; i < num_kernel_image_mappings; i++) {
595 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
596 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
597 tte_vaddr += 0x400000;
598 tte_data += 0x400000;
599 }
600 } else {
601 for (i = 0; i < num_kernel_image_mappings; i++) {
602 prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
603 prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
604 tte_vaddr += 0x400000;
605 tte_data += 0x400000;
606 }
607 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
608 }
609 if (tlb_type == cheetah_plus) {
610 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
611 CTX_CHEETAH_PLUS_NUC);
612 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
613 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
614 }
615 }
616
617
618 static void __init inherit_prom_mappings(void)
619 {
620 /* Now fixup OBP's idea about where we really are mapped. */
621 printk("Remapping the kernel... ");
622 remap_kernel();
623 printk("done.\n");
624 }
625
626 void prom_world(int enter)
627 {
628 if (!enter)
629 set_fs(get_fs());
630
631 __asm__ __volatile__("flushw");
632 }
633
634 void __flush_dcache_range(unsigned long start, unsigned long end)
635 {
636 unsigned long va;
637
638 if (tlb_type == spitfire) {
639 int n = 0;
640
641 for (va = start; va < end; va += 32) {
642 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
643 if (++n >= 512)
644 break;
645 }
646 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
647 start = __pa(start);
648 end = __pa(end);
649 for (va = start; va < end; va += 32)
650 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
651 "membar #Sync"
652 : /* no outputs */
653 : "r" (va),
654 "i" (ASI_DCACHE_INVALIDATE));
655 }
656 }
657 EXPORT_SYMBOL(__flush_dcache_range);
658
659 /* get_new_mmu_context() uses "cache + 1". */
660 DEFINE_SPINLOCK(ctx_alloc_lock);
661 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
662 #define MAX_CTX_NR (1UL << CTX_NR_BITS)
663 #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
664 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
665
666 /* Caller does TLB context flushing on local CPU if necessary.
667 * The caller also ensures that CTX_VALID(mm->context) is false.
668 *
669 * We must be careful about boundary cases so that we never
670 * let the user have CTX 0 (nucleus) or we ever use a CTX
671 * version of zero (and thus NO_CONTEXT would not be caught
672 * by version mis-match tests in mmu_context.h).
673 *
674 * Always invoked with interrupts disabled.
675 */
676 void get_new_mmu_context(struct mm_struct *mm)
677 {
678 unsigned long ctx, new_ctx;
679 unsigned long orig_pgsz_bits;
680 int new_version;
681
682 spin_lock(&ctx_alloc_lock);
683 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
684 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
685 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
686 new_version = 0;
687 if (new_ctx >= (1 << CTX_NR_BITS)) {
688 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
689 if (new_ctx >= ctx) {
690 int i;
691 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
692 CTX_FIRST_VERSION;
693 if (new_ctx == 1)
694 new_ctx = CTX_FIRST_VERSION;
695
696 /* Don't call memset, for 16 entries that's just
697 * plain silly...
698 */
699 mmu_context_bmap[0] = 3;
700 mmu_context_bmap[1] = 0;
701 mmu_context_bmap[2] = 0;
702 mmu_context_bmap[3] = 0;
703 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
704 mmu_context_bmap[i + 0] = 0;
705 mmu_context_bmap[i + 1] = 0;
706 mmu_context_bmap[i + 2] = 0;
707 mmu_context_bmap[i + 3] = 0;
708 }
709 new_version = 1;
710 goto out;
711 }
712 }
713 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
714 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
715 out:
716 tlb_context_cache = new_ctx;
717 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
718 spin_unlock(&ctx_alloc_lock);
719
720 if (unlikely(new_version))
721 smp_new_mmu_context_version();
722 }
723
724 static int numa_enabled = 1;
725 static int numa_debug;
726
727 static int __init early_numa(char *p)
728 {
729 if (!p)
730 return 0;
731
732 if (strstr(p, "off"))
733 numa_enabled = 0;
734
735 if (strstr(p, "debug"))
736 numa_debug = 1;
737
738 return 0;
739 }
740 early_param("numa", early_numa);
741
742 #define numadbg(f, a...) \
743 do { if (numa_debug) \
744 printk(KERN_INFO f, ## a); \
745 } while (0)
746
747 static void __init find_ramdisk(unsigned long phys_base)
748 {
749 #ifdef CONFIG_BLK_DEV_INITRD
750 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
751 unsigned long ramdisk_image;
752
753 /* Older versions of the bootloader only supported a
754 * 32-bit physical address for the ramdisk image
755 * location, stored at sparc_ramdisk_image. Newer
756 * SILO versions set sparc_ramdisk_image to zero and
757 * provide a full 64-bit physical address at
758 * sparc_ramdisk_image64.
759 */
760 ramdisk_image = sparc_ramdisk_image;
761 if (!ramdisk_image)
762 ramdisk_image = sparc_ramdisk_image64;
763
764 /* Another bootloader quirk. The bootloader normalizes
765 * the physical address to KERNBASE, so we have to
766 * factor that back out and add in the lowest valid
767 * physical page address to get the true physical address.
768 */
769 ramdisk_image -= KERNBASE;
770 ramdisk_image += phys_base;
771
772 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
773 ramdisk_image, sparc_ramdisk_size);
774
775 initrd_start = ramdisk_image;
776 initrd_end = ramdisk_image + sparc_ramdisk_size;
777
778 memblock_reserve(initrd_start, sparc_ramdisk_size);
779
780 initrd_start += PAGE_OFFSET;
781 initrd_end += PAGE_OFFSET;
782 }
783 #endif
784 }
785
786 struct node_mem_mask {
787 unsigned long mask;
788 unsigned long val;
789 };
790 static struct node_mem_mask node_masks[MAX_NUMNODES];
791 static int num_node_masks;
792
793 #ifdef CONFIG_NEED_MULTIPLE_NODES
794
795 int numa_cpu_lookup_table[NR_CPUS];
796 cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
797
798 struct mdesc_mblock {
799 u64 base;
800 u64 size;
801 u64 offset; /* RA-to-PA */
802 };
803 static struct mdesc_mblock *mblocks;
804 static int num_mblocks;
805
806 static unsigned long ra_to_pa(unsigned long addr)
807 {
808 int i;
809
810 for (i = 0; i < num_mblocks; i++) {
811 struct mdesc_mblock *m = &mblocks[i];
812
813 if (addr >= m->base &&
814 addr < (m->base + m->size)) {
815 addr += m->offset;
816 break;
817 }
818 }
819 return addr;
820 }
821
822 static int find_node(unsigned long addr)
823 {
824 int i;
825
826 addr = ra_to_pa(addr);
827 for (i = 0; i < num_node_masks; i++) {
828 struct node_mem_mask *p = &node_masks[i];
829
830 if ((addr & p->mask) == p->val)
831 return i;
832 }
833 /* The following condition has been observed on LDOM guests.*/
834 WARN_ONCE(1, "find_node: A physical address doesn't match a NUMA node"
835 " rule. Some physical memory will be owned by node 0.");
836 return 0;
837 }
838
839 static u64 memblock_nid_range(u64 start, u64 end, int *nid)
840 {
841 *nid = find_node(start);
842 start += PAGE_SIZE;
843 while (start < end) {
844 int n = find_node(start);
845
846 if (n != *nid)
847 break;
848 start += PAGE_SIZE;
849 }
850
851 if (start > end)
852 start = end;
853
854 return start;
855 }
856 #endif
857
858 /* This must be invoked after performing all of the necessary
859 * memblock_set_node() calls for 'nid'. We need to be able to get
860 * correct data from get_pfn_range_for_nid().
861 */
862 static void __init allocate_node_data(int nid)
863 {
864 struct pglist_data *p;
865 unsigned long start_pfn, end_pfn;
866 #ifdef CONFIG_NEED_MULTIPLE_NODES
867 unsigned long paddr;
868
869 paddr = memblock_alloc_try_nid(sizeof(struct pglist_data), SMP_CACHE_BYTES, nid);
870 if (!paddr) {
871 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
872 prom_halt();
873 }
874 NODE_DATA(nid) = __va(paddr);
875 memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
876
877 NODE_DATA(nid)->node_id = nid;
878 #endif
879
880 p = NODE_DATA(nid);
881
882 get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
883 p->node_start_pfn = start_pfn;
884 p->node_spanned_pages = end_pfn - start_pfn;
885 }
886
887 static void init_node_masks_nonnuma(void)
888 {
889 #ifdef CONFIG_NEED_MULTIPLE_NODES
890 int i;
891 #endif
892
893 numadbg("Initializing tables for non-numa.\n");
894
895 node_masks[0].mask = node_masks[0].val = 0;
896 num_node_masks = 1;
897
898 #ifdef CONFIG_NEED_MULTIPLE_NODES
899 for (i = 0; i < NR_CPUS; i++)
900 numa_cpu_lookup_table[i] = 0;
901
902 cpumask_setall(&numa_cpumask_lookup_table[0]);
903 #endif
904 }
905
906 #ifdef CONFIG_NEED_MULTIPLE_NODES
907 struct pglist_data *node_data[MAX_NUMNODES];
908
909 EXPORT_SYMBOL(numa_cpu_lookup_table);
910 EXPORT_SYMBOL(numa_cpumask_lookup_table);
911 EXPORT_SYMBOL(node_data);
912
913 struct mdesc_mlgroup {
914 u64 node;
915 u64 latency;
916 u64 match;
917 u64 mask;
918 };
919 static struct mdesc_mlgroup *mlgroups;
920 static int num_mlgroups;
921
922 static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
923 u32 cfg_handle)
924 {
925 u64 arc;
926
927 mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
928 u64 target = mdesc_arc_target(md, arc);
929 const u64 *val;
930
931 val = mdesc_get_property(md, target,
932 "cfg-handle", NULL);
933 if (val && *val == cfg_handle)
934 return 0;
935 }
936 return -ENODEV;
937 }
938
939 static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
940 u32 cfg_handle)
941 {
942 u64 arc, candidate, best_latency = ~(u64)0;
943
944 candidate = MDESC_NODE_NULL;
945 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
946 u64 target = mdesc_arc_target(md, arc);
947 const char *name = mdesc_node_name(md, target);
948 const u64 *val;
949
950 if (strcmp(name, "pio-latency-group"))
951 continue;
952
953 val = mdesc_get_property(md, target, "latency", NULL);
954 if (!val)
955 continue;
956
957 if (*val < best_latency) {
958 candidate = target;
959 best_latency = *val;
960 }
961 }
962
963 if (candidate == MDESC_NODE_NULL)
964 return -ENODEV;
965
966 return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
967 }
968
969 int of_node_to_nid(struct device_node *dp)
970 {
971 const struct linux_prom64_registers *regs;
972 struct mdesc_handle *md;
973 u32 cfg_handle;
974 int count, nid;
975 u64 grp;
976
977 /* This is the right thing to do on currently supported
978 * SUN4U NUMA platforms as well, as the PCI controller does
979 * not sit behind any particular memory controller.
980 */
981 if (!mlgroups)
982 return -1;
983
984 regs = of_get_property(dp, "reg", NULL);
985 if (!regs)
986 return -1;
987
988 cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
989
990 md = mdesc_grab();
991
992 count = 0;
993 nid = -1;
994 mdesc_for_each_node_by_name(md, grp, "group") {
995 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
996 nid = count;
997 break;
998 }
999 count++;
1000 }
1001
1002 mdesc_release(md);
1003
1004 return nid;
1005 }
1006
1007 static void __init add_node_ranges(void)
1008 {
1009 struct memblock_region *reg;
1010
1011 for_each_memblock(memory, reg) {
1012 unsigned long size = reg->size;
1013 unsigned long start, end;
1014
1015 start = reg->base;
1016 end = start + size;
1017 while (start < end) {
1018 unsigned long this_end;
1019 int nid;
1020
1021 this_end = memblock_nid_range(start, end, &nid);
1022
1023 numadbg("Setting memblock NUMA node nid[%d] "
1024 "start[%lx] end[%lx]\n",
1025 nid, start, this_end);
1026
1027 memblock_set_node(start, this_end - start,
1028 &memblock.memory, nid);
1029 start = this_end;
1030 }
1031 }
1032 }
1033
1034 static int __init grab_mlgroups(struct mdesc_handle *md)
1035 {
1036 unsigned long paddr;
1037 int count = 0;
1038 u64 node;
1039
1040 mdesc_for_each_node_by_name(md, node, "memory-latency-group")
1041 count++;
1042 if (!count)
1043 return -ENOENT;
1044
1045 paddr = memblock_alloc(count * sizeof(struct mdesc_mlgroup),
1046 SMP_CACHE_BYTES);
1047 if (!paddr)
1048 return -ENOMEM;
1049
1050 mlgroups = __va(paddr);
1051 num_mlgroups = count;
1052
1053 count = 0;
1054 mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1055 struct mdesc_mlgroup *m = &mlgroups[count++];
1056 const u64 *val;
1057
1058 m->node = node;
1059
1060 val = mdesc_get_property(md, node, "latency", NULL);
1061 m->latency = *val;
1062 val = mdesc_get_property(md, node, "address-match", NULL);
1063 m->match = *val;
1064 val = mdesc_get_property(md, node, "address-mask", NULL);
1065 m->mask = *val;
1066
1067 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1068 "match[%llx] mask[%llx]\n",
1069 count - 1, m->node, m->latency, m->match, m->mask);
1070 }
1071
1072 return 0;
1073 }
1074
1075 static int __init grab_mblocks(struct mdesc_handle *md)
1076 {
1077 unsigned long paddr;
1078 int count = 0;
1079 u64 node;
1080
1081 mdesc_for_each_node_by_name(md, node, "mblock")
1082 count++;
1083 if (!count)
1084 return -ENOENT;
1085
1086 paddr = memblock_alloc(count * sizeof(struct mdesc_mblock),
1087 SMP_CACHE_BYTES);
1088 if (!paddr)
1089 return -ENOMEM;
1090
1091 mblocks = __va(paddr);
1092 num_mblocks = count;
1093
1094 count = 0;
1095 mdesc_for_each_node_by_name(md, node, "mblock") {
1096 struct mdesc_mblock *m = &mblocks[count++];
1097 const u64 *val;
1098
1099 val = mdesc_get_property(md, node, "base", NULL);
1100 m->base = *val;
1101 val = mdesc_get_property(md, node, "size", NULL);
1102 m->size = *val;
1103 val = mdesc_get_property(md, node,
1104 "address-congruence-offset", NULL);
1105
1106 /* The address-congruence-offset property is optional.
1107 * Explicity zero it be identifty this.
1108 */
1109 if (val)
1110 m->offset = *val;
1111 else
1112 m->offset = 0UL;
1113
1114 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
1115 count - 1, m->base, m->size, m->offset);
1116 }
1117
1118 return 0;
1119 }
1120
1121 static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1122 u64 grp, cpumask_t *mask)
1123 {
1124 u64 arc;
1125
1126 cpumask_clear(mask);
1127
1128 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1129 u64 target = mdesc_arc_target(md, arc);
1130 const char *name = mdesc_node_name(md, target);
1131 const u64 *id;
1132
1133 if (strcmp(name, "cpu"))
1134 continue;
1135 id = mdesc_get_property(md, target, "id", NULL);
1136 if (*id < nr_cpu_ids)
1137 cpumask_set_cpu(*id, mask);
1138 }
1139 }
1140
1141 static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1142 {
1143 int i;
1144
1145 for (i = 0; i < num_mlgroups; i++) {
1146 struct mdesc_mlgroup *m = &mlgroups[i];
1147 if (m->node == node)
1148 return m;
1149 }
1150 return NULL;
1151 }
1152
1153 int __node_distance(int from, int to)
1154 {
1155 if ((from >= MAX_NUMNODES) || (to >= MAX_NUMNODES)) {
1156 pr_warn("Returning default NUMA distance value for %d->%d\n",
1157 from, to);
1158 return (from == to) ? LOCAL_DISTANCE : REMOTE_DISTANCE;
1159 }
1160 return numa_latency[from][to];
1161 }
1162
1163 static int find_best_numa_node_for_mlgroup(struct mdesc_mlgroup *grp)
1164 {
1165 int i;
1166
1167 for (i = 0; i < MAX_NUMNODES; i++) {
1168 struct node_mem_mask *n = &node_masks[i];
1169
1170 if ((grp->mask == n->mask) && (grp->match == n->val))
1171 break;
1172 }
1173 return i;
1174 }
1175
1176 static void find_numa_latencies_for_group(struct mdesc_handle *md, u64 grp,
1177 int index)
1178 {
1179 u64 arc;
1180
1181 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1182 int tnode;
1183 u64 target = mdesc_arc_target(md, arc);
1184 struct mdesc_mlgroup *m = find_mlgroup(target);
1185
1186 if (!m)
1187 continue;
1188 tnode = find_best_numa_node_for_mlgroup(m);
1189 if (tnode == MAX_NUMNODES)
1190 continue;
1191 numa_latency[index][tnode] = m->latency;
1192 }
1193 }
1194
1195 static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1196 int index)
1197 {
1198 struct mdesc_mlgroup *candidate = NULL;
1199 u64 arc, best_latency = ~(u64)0;
1200 struct node_mem_mask *n;
1201
1202 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1203 u64 target = mdesc_arc_target(md, arc);
1204 struct mdesc_mlgroup *m = find_mlgroup(target);
1205 if (!m)
1206 continue;
1207 if (m->latency < best_latency) {
1208 candidate = m;
1209 best_latency = m->latency;
1210 }
1211 }
1212 if (!candidate)
1213 return -ENOENT;
1214
1215 if (num_node_masks != index) {
1216 printk(KERN_ERR "Inconsistent NUMA state, "
1217 "index[%d] != num_node_masks[%d]\n",
1218 index, num_node_masks);
1219 return -EINVAL;
1220 }
1221
1222 n = &node_masks[num_node_masks++];
1223
1224 n->mask = candidate->mask;
1225 n->val = candidate->match;
1226
1227 numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%llx])\n",
1228 index, n->mask, n->val, candidate->latency);
1229
1230 return 0;
1231 }
1232
1233 static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1234 int index)
1235 {
1236 cpumask_t mask;
1237 int cpu;
1238
1239 numa_parse_mdesc_group_cpus(md, grp, &mask);
1240
1241 for_each_cpu(cpu, &mask)
1242 numa_cpu_lookup_table[cpu] = index;
1243 cpumask_copy(&numa_cpumask_lookup_table[index], &mask);
1244
1245 if (numa_debug) {
1246 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1247 for_each_cpu(cpu, &mask)
1248 printk("%d ", cpu);
1249 printk("]\n");
1250 }
1251
1252 return numa_attach_mlgroup(md, grp, index);
1253 }
1254
1255 static int __init numa_parse_mdesc(void)
1256 {
1257 struct mdesc_handle *md = mdesc_grab();
1258 int i, j, err, count;
1259 u64 node;
1260
1261 node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1262 if (node == MDESC_NODE_NULL) {
1263 mdesc_release(md);
1264 return -ENOENT;
1265 }
1266
1267 err = grab_mblocks(md);
1268 if (err < 0)
1269 goto out;
1270
1271 err = grab_mlgroups(md);
1272 if (err < 0)
1273 goto out;
1274
1275 count = 0;
1276 mdesc_for_each_node_by_name(md, node, "group") {
1277 err = numa_parse_mdesc_group(md, node, count);
1278 if (err < 0)
1279 break;
1280 count++;
1281 }
1282
1283 count = 0;
1284 mdesc_for_each_node_by_name(md, node, "group") {
1285 find_numa_latencies_for_group(md, node, count);
1286 count++;
1287 }
1288
1289 /* Normalize numa latency matrix according to ACPI SLIT spec. */
1290 for (i = 0; i < MAX_NUMNODES; i++) {
1291 u64 self_latency = numa_latency[i][i];
1292
1293 for (j = 0; j < MAX_NUMNODES; j++) {
1294 numa_latency[i][j] =
1295 (numa_latency[i][j] * LOCAL_DISTANCE) /
1296 self_latency;
1297 }
1298 }
1299
1300 add_node_ranges();
1301
1302 for (i = 0; i < num_node_masks; i++) {
1303 allocate_node_data(i);
1304 node_set_online(i);
1305 }
1306
1307 err = 0;
1308 out:
1309 mdesc_release(md);
1310 return err;
1311 }
1312
1313 static int __init numa_parse_jbus(void)
1314 {
1315 unsigned long cpu, index;
1316
1317 /* NUMA node id is encoded in bits 36 and higher, and there is
1318 * a 1-to-1 mapping from CPU ID to NUMA node ID.
1319 */
1320 index = 0;
1321 for_each_present_cpu(cpu) {
1322 numa_cpu_lookup_table[cpu] = index;
1323 cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu));
1324 node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1325 node_masks[index].val = cpu << 36UL;
1326
1327 index++;
1328 }
1329 num_node_masks = index;
1330
1331 add_node_ranges();
1332
1333 for (index = 0; index < num_node_masks; index++) {
1334 allocate_node_data(index);
1335 node_set_online(index);
1336 }
1337
1338 return 0;
1339 }
1340
1341 static int __init numa_parse_sun4u(void)
1342 {
1343 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1344 unsigned long ver;
1345
1346 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
1347 if ((ver >> 32UL) == __JALAPENO_ID ||
1348 (ver >> 32UL) == __SERRANO_ID)
1349 return numa_parse_jbus();
1350 }
1351 return -1;
1352 }
1353
1354 static int __init bootmem_init_numa(void)
1355 {
1356 int i, j;
1357 int err = -1;
1358
1359 numadbg("bootmem_init_numa()\n");
1360
1361 /* Some sane defaults for numa latency values */
1362 for (i = 0; i < MAX_NUMNODES; i++) {
1363 for (j = 0; j < MAX_NUMNODES; j++)
1364 numa_latency[i][j] = (i == j) ?
1365 LOCAL_DISTANCE : REMOTE_DISTANCE;
1366 }
1367
1368 if (numa_enabled) {
1369 if (tlb_type == hypervisor)
1370 err = numa_parse_mdesc();
1371 else
1372 err = numa_parse_sun4u();
1373 }
1374 return err;
1375 }
1376
1377 #else
1378
1379 static int bootmem_init_numa(void)
1380 {
1381 return -1;
1382 }
1383
1384 #endif
1385
1386 static void __init bootmem_init_nonnuma(void)
1387 {
1388 unsigned long top_of_ram = memblock_end_of_DRAM();
1389 unsigned long total_ram = memblock_phys_mem_size();
1390
1391 numadbg("bootmem_init_nonnuma()\n");
1392
1393 printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1394 top_of_ram, total_ram);
1395 printk(KERN_INFO "Memory hole size: %ldMB\n",
1396 (top_of_ram - total_ram) >> 20);
1397
1398 init_node_masks_nonnuma();
1399 memblock_set_node(0, (phys_addr_t)ULLONG_MAX, &memblock.memory, 0);
1400 allocate_node_data(0);
1401 node_set_online(0);
1402 }
1403
1404 static unsigned long __init bootmem_init(unsigned long phys_base)
1405 {
1406 unsigned long end_pfn;
1407
1408 end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
1409 max_pfn = max_low_pfn = end_pfn;
1410 min_low_pfn = (phys_base >> PAGE_SHIFT);
1411
1412 if (bootmem_init_numa() < 0)
1413 bootmem_init_nonnuma();
1414
1415 /* Dump memblock with node info. */
1416 memblock_dump_all();
1417
1418 /* XXX cpu notifier XXX */
1419
1420 sparse_memory_present_with_active_regions(MAX_NUMNODES);
1421 sparse_init();
1422
1423 return end_pfn;
1424 }
1425
1426 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1427 static int pall_ents __initdata;
1428
1429 static unsigned long max_phys_bits = 40;
1430
1431 bool kern_addr_valid(unsigned long addr)
1432 {
1433 pgd_t *pgd;
1434 pud_t *pud;
1435 pmd_t *pmd;
1436 pte_t *pte;
1437
1438 if ((long)addr < 0L) {
1439 unsigned long pa = __pa(addr);
1440
1441 if ((addr >> max_phys_bits) != 0UL)
1442 return false;
1443
1444 return pfn_valid(pa >> PAGE_SHIFT);
1445 }
1446
1447 if (addr >= (unsigned long) KERNBASE &&
1448 addr < (unsigned long)&_end)
1449 return true;
1450
1451 pgd = pgd_offset_k(addr);
1452 if (pgd_none(*pgd))
1453 return 0;
1454
1455 pud = pud_offset(pgd, addr);
1456 if (pud_none(*pud))
1457 return 0;
1458
1459 if (pud_large(*pud))
1460 return pfn_valid(pud_pfn(*pud));
1461
1462 pmd = pmd_offset(pud, addr);
1463 if (pmd_none(*pmd))
1464 return 0;
1465
1466 if (pmd_large(*pmd))
1467 return pfn_valid(pmd_pfn(*pmd));
1468
1469 pte = pte_offset_kernel(pmd, addr);
1470 if (pte_none(*pte))
1471 return 0;
1472
1473 return pfn_valid(pte_pfn(*pte));
1474 }
1475 EXPORT_SYMBOL(kern_addr_valid);
1476
1477 static unsigned long __ref kernel_map_hugepud(unsigned long vstart,
1478 unsigned long vend,
1479 pud_t *pud)
1480 {
1481 const unsigned long mask16gb = (1UL << 34) - 1UL;
1482 u64 pte_val = vstart;
1483
1484 /* Each PUD is 8GB */
1485 if ((vstart & mask16gb) ||
1486 (vend - vstart <= mask16gb)) {
1487 pte_val ^= kern_linear_pte_xor[2];
1488 pud_val(*pud) = pte_val | _PAGE_PUD_HUGE;
1489
1490 return vstart + PUD_SIZE;
1491 }
1492
1493 pte_val ^= kern_linear_pte_xor[3];
1494 pte_val |= _PAGE_PUD_HUGE;
1495
1496 vend = vstart + mask16gb + 1UL;
1497 while (vstart < vend) {
1498 pud_val(*pud) = pte_val;
1499
1500 pte_val += PUD_SIZE;
1501 vstart += PUD_SIZE;
1502 pud++;
1503 }
1504 return vstart;
1505 }
1506
1507 static bool kernel_can_map_hugepud(unsigned long vstart, unsigned long vend,
1508 bool guard)
1509 {
1510 if (guard && !(vstart & ~PUD_MASK) && (vend - vstart) >= PUD_SIZE)
1511 return true;
1512
1513 return false;
1514 }
1515
1516 static unsigned long __ref kernel_map_hugepmd(unsigned long vstart,
1517 unsigned long vend,
1518 pmd_t *pmd)
1519 {
1520 const unsigned long mask256mb = (1UL << 28) - 1UL;
1521 const unsigned long mask2gb = (1UL << 31) - 1UL;
1522 u64 pte_val = vstart;
1523
1524 /* Each PMD is 8MB */
1525 if ((vstart & mask256mb) ||
1526 (vend - vstart <= mask256mb)) {
1527 pte_val ^= kern_linear_pte_xor[0];
1528 pmd_val(*pmd) = pte_val | _PAGE_PMD_HUGE;
1529
1530 return vstart + PMD_SIZE;
1531 }
1532
1533 if ((vstart & mask2gb) ||
1534 (vend - vstart <= mask2gb)) {
1535 pte_val ^= kern_linear_pte_xor[1];
1536 pte_val |= _PAGE_PMD_HUGE;
1537 vend = vstart + mask256mb + 1UL;
1538 } else {
1539 pte_val ^= kern_linear_pte_xor[2];
1540 pte_val |= _PAGE_PMD_HUGE;
1541 vend = vstart + mask2gb + 1UL;
1542 }
1543
1544 while (vstart < vend) {
1545 pmd_val(*pmd) = pte_val;
1546
1547 pte_val += PMD_SIZE;
1548 vstart += PMD_SIZE;
1549 pmd++;
1550 }
1551
1552 return vstart;
1553 }
1554
1555 static bool kernel_can_map_hugepmd(unsigned long vstart, unsigned long vend,
1556 bool guard)
1557 {
1558 if (guard && !(vstart & ~PMD_MASK) && (vend - vstart) >= PMD_SIZE)
1559 return true;
1560
1561 return false;
1562 }
1563
1564 static unsigned long __ref kernel_map_range(unsigned long pstart,
1565 unsigned long pend, pgprot_t prot,
1566 bool use_huge)
1567 {
1568 unsigned long vstart = PAGE_OFFSET + pstart;
1569 unsigned long vend = PAGE_OFFSET + pend;
1570 unsigned long alloc_bytes = 0UL;
1571
1572 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1573 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1574 vstart, vend);
1575 prom_halt();
1576 }
1577
1578 while (vstart < vend) {
1579 unsigned long this_end, paddr = __pa(vstart);
1580 pgd_t *pgd = pgd_offset_k(vstart);
1581 pud_t *pud;
1582 pmd_t *pmd;
1583 pte_t *pte;
1584
1585 if (pgd_none(*pgd)) {
1586 pud_t *new;
1587
1588 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1589 alloc_bytes += PAGE_SIZE;
1590 pgd_populate(&init_mm, pgd, new);
1591 }
1592 pud = pud_offset(pgd, vstart);
1593 if (pud_none(*pud)) {
1594 pmd_t *new;
1595
1596 if (kernel_can_map_hugepud(vstart, vend, use_huge)) {
1597 vstart = kernel_map_hugepud(vstart, vend, pud);
1598 continue;
1599 }
1600 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1601 alloc_bytes += PAGE_SIZE;
1602 pud_populate(&init_mm, pud, new);
1603 }
1604
1605 pmd = pmd_offset(pud, vstart);
1606 if (pmd_none(*pmd)) {
1607 pte_t *new;
1608
1609 if (kernel_can_map_hugepmd(vstart, vend, use_huge)) {
1610 vstart = kernel_map_hugepmd(vstart, vend, pmd);
1611 continue;
1612 }
1613 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1614 alloc_bytes += PAGE_SIZE;
1615 pmd_populate_kernel(&init_mm, pmd, new);
1616 }
1617
1618 pte = pte_offset_kernel(pmd, vstart);
1619 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1620 if (this_end > vend)
1621 this_end = vend;
1622
1623 while (vstart < this_end) {
1624 pte_val(*pte) = (paddr | pgprot_val(prot));
1625
1626 vstart += PAGE_SIZE;
1627 paddr += PAGE_SIZE;
1628 pte++;
1629 }
1630 }
1631
1632 return alloc_bytes;
1633 }
1634
1635 static void __init flush_all_kernel_tsbs(void)
1636 {
1637 int i;
1638
1639 for (i = 0; i < KERNEL_TSB_NENTRIES; i++) {
1640 struct tsb *ent = &swapper_tsb[i];
1641
1642 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1643 }
1644 #ifndef CONFIG_DEBUG_PAGEALLOC
1645 for (i = 0; i < KERNEL_TSB4M_NENTRIES; i++) {
1646 struct tsb *ent = &swapper_4m_tsb[i];
1647
1648 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1649 }
1650 #endif
1651 }
1652
1653 extern unsigned int kvmap_linear_patch[1];
1654
1655 static void __init kernel_physical_mapping_init(void)
1656 {
1657 unsigned long i, mem_alloced = 0UL;
1658 bool use_huge = true;
1659
1660 #ifdef CONFIG_DEBUG_PAGEALLOC
1661 use_huge = false;
1662 #endif
1663 for (i = 0; i < pall_ents; i++) {
1664 unsigned long phys_start, phys_end;
1665
1666 phys_start = pall[i].phys_addr;
1667 phys_end = phys_start + pall[i].reg_size;
1668
1669 mem_alloced += kernel_map_range(phys_start, phys_end,
1670 PAGE_KERNEL, use_huge);
1671 }
1672
1673 printk("Allocated %ld bytes for kernel page tables.\n",
1674 mem_alloced);
1675
1676 kvmap_linear_patch[0] = 0x01000000; /* nop */
1677 flushi(&kvmap_linear_patch[0]);
1678
1679 flush_all_kernel_tsbs();
1680
1681 __flush_tlb_all();
1682 }
1683
1684 #ifdef CONFIG_DEBUG_PAGEALLOC
1685 void __kernel_map_pages(struct page *page, int numpages, int enable)
1686 {
1687 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1688 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1689
1690 kernel_map_range(phys_start, phys_end,
1691 (enable ? PAGE_KERNEL : __pgprot(0)), false);
1692
1693 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1694 PAGE_OFFSET + phys_end);
1695
1696 /* we should perform an IPI and flush all tlbs,
1697 * but that can deadlock->flush only current cpu.
1698 */
1699 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1700 PAGE_OFFSET + phys_end);
1701 }
1702 #endif
1703
1704 unsigned long __init find_ecache_flush_span(unsigned long size)
1705 {
1706 int i;
1707
1708 for (i = 0; i < pavail_ents; i++) {
1709 if (pavail[i].reg_size >= size)
1710 return pavail[i].phys_addr;
1711 }
1712
1713 return ~0UL;
1714 }
1715
1716 unsigned long PAGE_OFFSET;
1717 EXPORT_SYMBOL(PAGE_OFFSET);
1718
1719 unsigned long VMALLOC_END = 0x0000010000000000UL;
1720 EXPORT_SYMBOL(VMALLOC_END);
1721
1722 unsigned long sparc64_va_hole_top = 0xfffff80000000000UL;
1723 unsigned long sparc64_va_hole_bottom = 0x0000080000000000UL;
1724
1725 static void __init setup_page_offset(void)
1726 {
1727 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1728 /* Cheetah/Panther support a full 64-bit virtual
1729 * address, so we can use all that our page tables
1730 * support.
1731 */
1732 sparc64_va_hole_top = 0xfff0000000000000UL;
1733 sparc64_va_hole_bottom = 0x0010000000000000UL;
1734
1735 max_phys_bits = 42;
1736 } else if (tlb_type == hypervisor) {
1737 switch (sun4v_chip_type) {
1738 case SUN4V_CHIP_NIAGARA1:
1739 case SUN4V_CHIP_NIAGARA2:
1740 /* T1 and T2 support 48-bit virtual addresses. */
1741 sparc64_va_hole_top = 0xffff800000000000UL;
1742 sparc64_va_hole_bottom = 0x0000800000000000UL;
1743
1744 max_phys_bits = 39;
1745 break;
1746 case SUN4V_CHIP_NIAGARA3:
1747 /* T3 supports 48-bit virtual addresses. */
1748 sparc64_va_hole_top = 0xffff800000000000UL;
1749 sparc64_va_hole_bottom = 0x0000800000000000UL;
1750
1751 max_phys_bits = 43;
1752 break;
1753 case SUN4V_CHIP_NIAGARA4:
1754 case SUN4V_CHIP_NIAGARA5:
1755 case SUN4V_CHIP_SPARC64X:
1756 case SUN4V_CHIP_SPARC_M6:
1757 /* T4 and later support 52-bit virtual addresses. */
1758 sparc64_va_hole_top = 0xfff8000000000000UL;
1759 sparc64_va_hole_bottom = 0x0008000000000000UL;
1760 max_phys_bits = 47;
1761 break;
1762 case SUN4V_CHIP_SPARC_M7:
1763 case SUN4V_CHIP_SPARC_SN:
1764 default:
1765 /* M7 and later support 52-bit virtual addresses. */
1766 sparc64_va_hole_top = 0xfff8000000000000UL;
1767 sparc64_va_hole_bottom = 0x0008000000000000UL;
1768 max_phys_bits = 49;
1769 break;
1770 }
1771 }
1772
1773 if (max_phys_bits > MAX_PHYS_ADDRESS_BITS) {
1774 prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n",
1775 max_phys_bits);
1776 prom_halt();
1777 }
1778
1779 PAGE_OFFSET = sparc64_va_hole_top;
1780 VMALLOC_END = ((sparc64_va_hole_bottom >> 1) +
1781 (sparc64_va_hole_bottom >> 2));
1782
1783 pr_info("MM: PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n",
1784 PAGE_OFFSET, max_phys_bits);
1785 pr_info("MM: VMALLOC [0x%016lx --> 0x%016lx]\n",
1786 VMALLOC_START, VMALLOC_END);
1787 pr_info("MM: VMEMMAP [0x%016lx --> 0x%016lx]\n",
1788 VMEMMAP_BASE, VMEMMAP_BASE << 1);
1789 }
1790
1791 static void __init tsb_phys_patch(void)
1792 {
1793 struct tsb_ldquad_phys_patch_entry *pquad;
1794 struct tsb_phys_patch_entry *p;
1795
1796 pquad = &__tsb_ldquad_phys_patch;
1797 while (pquad < &__tsb_ldquad_phys_patch_end) {
1798 unsigned long addr = pquad->addr;
1799
1800 if (tlb_type == hypervisor)
1801 *(unsigned int *) addr = pquad->sun4v_insn;
1802 else
1803 *(unsigned int *) addr = pquad->sun4u_insn;
1804 wmb();
1805 __asm__ __volatile__("flush %0"
1806 : /* no outputs */
1807 : "r" (addr));
1808
1809 pquad++;
1810 }
1811
1812 p = &__tsb_phys_patch;
1813 while (p < &__tsb_phys_patch_end) {
1814 unsigned long addr = p->addr;
1815
1816 *(unsigned int *) addr = p->insn;
1817 wmb();
1818 __asm__ __volatile__("flush %0"
1819 : /* no outputs */
1820 : "r" (addr));
1821
1822 p++;
1823 }
1824 }
1825
1826 /* Don't mark as init, we give this to the Hypervisor. */
1827 #ifndef CONFIG_DEBUG_PAGEALLOC
1828 #define NUM_KTSB_DESCR 2
1829 #else
1830 #define NUM_KTSB_DESCR 1
1831 #endif
1832 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
1833
1834 /* The swapper TSBs are loaded with a base sequence of:
1835 *
1836 * sethi %uhi(SYMBOL), REG1
1837 * sethi %hi(SYMBOL), REG2
1838 * or REG1, %ulo(SYMBOL), REG1
1839 * or REG2, %lo(SYMBOL), REG2
1840 * sllx REG1, 32, REG1
1841 * or REG1, REG2, REG1
1842 *
1843 * When we use physical addressing for the TSB accesses, we patch the
1844 * first four instructions in the above sequence.
1845 */
1846
1847 static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa)
1848 {
1849 unsigned long high_bits, low_bits;
1850
1851 high_bits = (pa >> 32) & 0xffffffff;
1852 low_bits = (pa >> 0) & 0xffffffff;
1853
1854 while (start < end) {
1855 unsigned int *ia = (unsigned int *)(unsigned long)*start;
1856
1857 ia[0] = (ia[0] & ~0x3fffff) | (high_bits >> 10);
1858 __asm__ __volatile__("flush %0" : : "r" (ia));
1859
1860 ia[1] = (ia[1] & ~0x3fffff) | (low_bits >> 10);
1861 __asm__ __volatile__("flush %0" : : "r" (ia + 1));
1862
1863 ia[2] = (ia[2] & ~0x1fff) | (high_bits & 0x3ff);
1864 __asm__ __volatile__("flush %0" : : "r" (ia + 2));
1865
1866 ia[3] = (ia[3] & ~0x1fff) | (low_bits & 0x3ff);
1867 __asm__ __volatile__("flush %0" : : "r" (ia + 3));
1868
1869 start++;
1870 }
1871 }
1872
1873 static void ktsb_phys_patch(void)
1874 {
1875 extern unsigned int __swapper_tsb_phys_patch;
1876 extern unsigned int __swapper_tsb_phys_patch_end;
1877 unsigned long ktsb_pa;
1878
1879 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1880 patch_one_ktsb_phys(&__swapper_tsb_phys_patch,
1881 &__swapper_tsb_phys_patch_end, ktsb_pa);
1882 #ifndef CONFIG_DEBUG_PAGEALLOC
1883 {
1884 extern unsigned int __swapper_4m_tsb_phys_patch;
1885 extern unsigned int __swapper_4m_tsb_phys_patch_end;
1886 ktsb_pa = (kern_base +
1887 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1888 patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch,
1889 &__swapper_4m_tsb_phys_patch_end, ktsb_pa);
1890 }
1891 #endif
1892 }
1893
1894 static void __init sun4v_ktsb_init(void)
1895 {
1896 unsigned long ktsb_pa;
1897
1898 /* First KTSB for PAGE_SIZE mappings. */
1899 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1900
1901 switch (PAGE_SIZE) {
1902 case 8 * 1024:
1903 default:
1904 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1905 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1906 break;
1907
1908 case 64 * 1024:
1909 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1910 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1911 break;
1912
1913 case 512 * 1024:
1914 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1915 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1916 break;
1917
1918 case 4 * 1024 * 1024:
1919 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1920 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1921 break;
1922 }
1923
1924 ktsb_descr[0].assoc = 1;
1925 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1926 ktsb_descr[0].ctx_idx = 0;
1927 ktsb_descr[0].tsb_base = ktsb_pa;
1928 ktsb_descr[0].resv = 0;
1929
1930 #ifndef CONFIG_DEBUG_PAGEALLOC
1931 /* Second KTSB for 4MB/256MB/2GB/16GB mappings. */
1932 ktsb_pa = (kern_base +
1933 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1934
1935 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1936 ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB |
1937 HV_PGSZ_MASK_256MB |
1938 HV_PGSZ_MASK_2GB |
1939 HV_PGSZ_MASK_16GB) &
1940 cpu_pgsz_mask);
1941 ktsb_descr[1].assoc = 1;
1942 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1943 ktsb_descr[1].ctx_idx = 0;
1944 ktsb_descr[1].tsb_base = ktsb_pa;
1945 ktsb_descr[1].resv = 0;
1946 #endif
1947 }
1948
1949 void sun4v_ktsb_register(void)
1950 {
1951 unsigned long pa, ret;
1952
1953 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1954
1955 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
1956 if (ret != 0) {
1957 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1958 "errors with %lx\n", pa, ret);
1959 prom_halt();
1960 }
1961 }
1962
1963 static void __init sun4u_linear_pte_xor_finalize(void)
1964 {
1965 #ifndef CONFIG_DEBUG_PAGEALLOC
1966 /* This is where we would add Panther support for
1967 * 32MB and 256MB pages.
1968 */
1969 #endif
1970 }
1971
1972 static void __init sun4v_linear_pte_xor_finalize(void)
1973 {
1974 unsigned long pagecv_flag;
1975
1976 /* Bit 9 of TTE is no longer CV bit on M7 processor and it instead
1977 * enables MCD error. Do not set bit 9 on M7 processor.
1978 */
1979 switch (sun4v_chip_type) {
1980 case SUN4V_CHIP_SPARC_M7:
1981 case SUN4V_CHIP_SPARC_SN:
1982 pagecv_flag = 0x00;
1983 break;
1984 default:
1985 pagecv_flag = _PAGE_CV_4V;
1986 break;
1987 }
1988 #ifndef CONFIG_DEBUG_PAGEALLOC
1989 if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) {
1990 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
1991 PAGE_OFFSET;
1992 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | pagecv_flag |
1993 _PAGE_P_4V | _PAGE_W_4V);
1994 } else {
1995 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
1996 }
1997
1998 if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) {
1999 kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^
2000 PAGE_OFFSET;
2001 kern_linear_pte_xor[2] |= (_PAGE_CP_4V | pagecv_flag |
2002 _PAGE_P_4V | _PAGE_W_4V);
2003 } else {
2004 kern_linear_pte_xor[2] = kern_linear_pte_xor[1];
2005 }
2006
2007 if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) {
2008 kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^
2009 PAGE_OFFSET;
2010 kern_linear_pte_xor[3] |= (_PAGE_CP_4V | pagecv_flag |
2011 _PAGE_P_4V | _PAGE_W_4V);
2012 } else {
2013 kern_linear_pte_xor[3] = kern_linear_pte_xor[2];
2014 }
2015 #endif
2016 }
2017
2018 /* paging_init() sets up the page tables */
2019
2020 static unsigned long last_valid_pfn;
2021
2022 static void sun4u_pgprot_init(void);
2023 static void sun4v_pgprot_init(void);
2024
2025 static phys_addr_t __init available_memory(void)
2026 {
2027 phys_addr_t available = 0ULL;
2028 phys_addr_t pa_start, pa_end;
2029 u64 i;
2030
2031 for_each_free_mem_range(i, NUMA_NO_NODE, MEMBLOCK_NONE, &pa_start,
2032 &pa_end, NULL)
2033 available = available + (pa_end - pa_start);
2034
2035 return available;
2036 }
2037
2038 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
2039 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
2040 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2041 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2042 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2043 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2044
2045 /* We need to exclude reserved regions. This exclusion will include
2046 * vmlinux and initrd. To be more precise the initrd size could be used to
2047 * compute a new lower limit because it is freed later during initialization.
2048 */
2049 static void __init reduce_memory(phys_addr_t limit_ram)
2050 {
2051 phys_addr_t avail_ram = available_memory();
2052 phys_addr_t pa_start, pa_end;
2053 u64 i;
2054
2055 if (limit_ram >= avail_ram)
2056 return;
2057
2058 for_each_free_mem_range(i, NUMA_NO_NODE, MEMBLOCK_NONE, &pa_start,
2059 &pa_end, NULL) {
2060 phys_addr_t region_size = pa_end - pa_start;
2061 phys_addr_t clip_start = pa_start;
2062
2063 avail_ram = avail_ram - region_size;
2064 /* Are we consuming too much? */
2065 if (avail_ram < limit_ram) {
2066 phys_addr_t give_back = limit_ram - avail_ram;
2067
2068 region_size = region_size - give_back;
2069 clip_start = clip_start + give_back;
2070 }
2071
2072 memblock_remove(clip_start, region_size);
2073
2074 if (avail_ram <= limit_ram)
2075 break;
2076 i = 0UL;
2077 }
2078 }
2079
2080 void __init paging_init(void)
2081 {
2082 unsigned long end_pfn, shift, phys_base;
2083 unsigned long real_end, i;
2084 int node;
2085
2086 setup_page_offset();
2087
2088 /* These build time checkes make sure that the dcache_dirty_cpu()
2089 * page->flags usage will work.
2090 *
2091 * When a page gets marked as dcache-dirty, we store the
2092 * cpu number starting at bit 32 in the page->flags. Also,
2093 * functions like clear_dcache_dirty_cpu use the cpu mask
2094 * in 13-bit signed-immediate instruction fields.
2095 */
2096
2097 /*
2098 * Page flags must not reach into upper 32 bits that are used
2099 * for the cpu number
2100 */
2101 BUILD_BUG_ON(NR_PAGEFLAGS > 32);
2102
2103 /*
2104 * The bit fields placed in the high range must not reach below
2105 * the 32 bit boundary. Otherwise we cannot place the cpu field
2106 * at the 32 bit boundary.
2107 */
2108 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
2109 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
2110
2111 BUILD_BUG_ON(NR_CPUS > 4096);
2112
2113 kern_base = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
2114 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
2115
2116 /* Invalidate both kernel TSBs. */
2117 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
2118 #ifndef CONFIG_DEBUG_PAGEALLOC
2119 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2120 #endif
2121
2122 /* TTE.cv bit on sparc v9 occupies the same position as TTE.mcde
2123 * bit on M7 processor. This is a conflicting usage of the same
2124 * bit. Enabling TTE.cv on M7 would turn on Memory Corruption
2125 * Detection error on all pages and this will lead to problems
2126 * later. Kernel does not run with MCD enabled and hence rest
2127 * of the required steps to fully configure memory corruption
2128 * detection are not taken. We need to ensure TTE.mcde is not
2129 * set on M7 processor. Compute the value of cacheability
2130 * flag for use later taking this into consideration.
2131 */
2132 switch (sun4v_chip_type) {
2133 case SUN4V_CHIP_SPARC_M7:
2134 case SUN4V_CHIP_SPARC_SN:
2135 page_cache4v_flag = _PAGE_CP_4V;
2136 break;
2137 default:
2138 page_cache4v_flag = _PAGE_CACHE_4V;
2139 break;
2140 }
2141
2142 if (tlb_type == hypervisor)
2143 sun4v_pgprot_init();
2144 else
2145 sun4u_pgprot_init();
2146
2147 if (tlb_type == cheetah_plus ||
2148 tlb_type == hypervisor) {
2149 tsb_phys_patch();
2150 ktsb_phys_patch();
2151 }
2152
2153 if (tlb_type == hypervisor)
2154 sun4v_patch_tlb_handlers();
2155
2156 /* Find available physical memory...
2157 *
2158 * Read it twice in order to work around a bug in openfirmware.
2159 * The call to grab this table itself can cause openfirmware to
2160 * allocate memory, which in turn can take away some space from
2161 * the list of available memory. Reading it twice makes sure
2162 * we really do get the final value.
2163 */
2164 read_obp_translations();
2165 read_obp_memory("reg", &pall[0], &pall_ents);
2166 read_obp_memory("available", &pavail[0], &pavail_ents);
2167 read_obp_memory("available", &pavail[0], &pavail_ents);
2168
2169 phys_base = 0xffffffffffffffffUL;
2170 for (i = 0; i < pavail_ents; i++) {
2171 phys_base = min(phys_base, pavail[i].phys_addr);
2172 memblock_add(pavail[i].phys_addr, pavail[i].reg_size);
2173 }
2174
2175 memblock_reserve(kern_base, kern_size);
2176
2177 find_ramdisk(phys_base);
2178
2179 if (cmdline_memory_size)
2180 reduce_memory(cmdline_memory_size);
2181
2182 memblock_allow_resize();
2183 memblock_dump_all();
2184
2185 set_bit(0, mmu_context_bmap);
2186
2187 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
2188
2189 real_end = (unsigned long)_end;
2190 num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << ILOG2_4MB);
2191 printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
2192 num_kernel_image_mappings);
2193
2194 /* Set kernel pgd to upper alias so physical page computations
2195 * work.
2196 */
2197 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
2198
2199 memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir));
2200
2201 inherit_prom_mappings();
2202
2203 /* Ok, we can use our TLB miss and window trap handlers safely. */
2204 setup_tba();
2205
2206 __flush_tlb_all();
2207
2208 prom_build_devicetree();
2209 of_populate_present_mask();
2210 #ifndef CONFIG_SMP
2211 of_fill_in_cpu_data();
2212 #endif
2213
2214 if (tlb_type == hypervisor) {
2215 sun4v_mdesc_init();
2216 mdesc_populate_present_mask(cpu_all_mask);
2217 #ifndef CONFIG_SMP
2218 mdesc_fill_in_cpu_data(cpu_all_mask);
2219 #endif
2220 mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask);
2221
2222 sun4v_linear_pte_xor_finalize();
2223
2224 sun4v_ktsb_init();
2225 sun4v_ktsb_register();
2226 } else {
2227 unsigned long impl, ver;
2228
2229 cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K |
2230 HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB);
2231
2232 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
2233 impl = ((ver >> 32) & 0xffff);
2234 if (impl == PANTHER_IMPL)
2235 cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB |
2236 HV_PGSZ_MASK_256MB);
2237
2238 sun4u_linear_pte_xor_finalize();
2239 }
2240
2241 /* Flush the TLBs and the 4M TSB so that the updated linear
2242 * pte XOR settings are realized for all mappings.
2243 */
2244 __flush_tlb_all();
2245 #ifndef CONFIG_DEBUG_PAGEALLOC
2246 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2247 #endif
2248 __flush_tlb_all();
2249
2250 /* Setup bootmem... */
2251 last_valid_pfn = end_pfn = bootmem_init(phys_base);
2252
2253 /* Once the OF device tree and MDESC have been setup, we know
2254 * the list of possible cpus. Therefore we can allocate the
2255 * IRQ stacks.
2256 */
2257 for_each_possible_cpu(i) {
2258 node = cpu_to_node(i);
2259
2260 softirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
2261 THREAD_SIZE,
2262 THREAD_SIZE, 0);
2263 hardirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
2264 THREAD_SIZE,
2265 THREAD_SIZE, 0);
2266 }
2267
2268 kernel_physical_mapping_init();
2269
2270 {
2271 unsigned long max_zone_pfns[MAX_NR_ZONES];
2272
2273 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
2274
2275 max_zone_pfns[ZONE_NORMAL] = end_pfn;
2276
2277 free_area_init_nodes(max_zone_pfns);
2278 }
2279
2280 printk("Booting Linux...\n");
2281 }
2282
2283 int page_in_phys_avail(unsigned long paddr)
2284 {
2285 int i;
2286
2287 paddr &= PAGE_MASK;
2288
2289 for (i = 0; i < pavail_ents; i++) {
2290 unsigned long start, end;
2291
2292 start = pavail[i].phys_addr;
2293 end = start + pavail[i].reg_size;
2294
2295 if (paddr >= start && paddr < end)
2296 return 1;
2297 }
2298 if (paddr >= kern_base && paddr < (kern_base + kern_size))
2299 return 1;
2300 #ifdef CONFIG_BLK_DEV_INITRD
2301 if (paddr >= __pa(initrd_start) &&
2302 paddr < __pa(PAGE_ALIGN(initrd_end)))
2303 return 1;
2304 #endif
2305
2306 return 0;
2307 }
2308
2309 static void __init register_page_bootmem_info(void)
2310 {
2311 #ifdef CONFIG_NEED_MULTIPLE_NODES
2312 int i;
2313
2314 for_each_online_node(i)
2315 if (NODE_DATA(i)->node_spanned_pages)
2316 register_page_bootmem_info_node(NODE_DATA(i));
2317 #endif
2318 }
2319 void __init mem_init(void)
2320 {
2321 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
2322
2323 register_page_bootmem_info();
2324 free_all_bootmem();
2325
2326 /*
2327 * Set up the zero page, mark it reserved, so that page count
2328 * is not manipulated when freeing the page from user ptes.
2329 */
2330 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
2331 if (mem_map_zero == NULL) {
2332 prom_printf("paging_init: Cannot alloc zero page.\n");
2333 prom_halt();
2334 }
2335 mark_page_reserved(mem_map_zero);
2336
2337 mem_init_print_info(NULL);
2338
2339 if (tlb_type == cheetah || tlb_type == cheetah_plus)
2340 cheetah_ecache_flush_init();
2341 }
2342
2343 void free_initmem(void)
2344 {
2345 unsigned long addr, initend;
2346 int do_free = 1;
2347
2348 /* If the physical memory maps were trimmed by kernel command
2349 * line options, don't even try freeing this initmem stuff up.
2350 * The kernel image could have been in the trimmed out region
2351 * and if so the freeing below will free invalid page structs.
2352 */
2353 if (cmdline_memory_size)
2354 do_free = 0;
2355
2356 /*
2357 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2358 */
2359 addr = PAGE_ALIGN((unsigned long)(__init_begin));
2360 initend = (unsigned long)(__init_end) & PAGE_MASK;
2361 for (; addr < initend; addr += PAGE_SIZE) {
2362 unsigned long page;
2363
2364 page = (addr +
2365 ((unsigned long) __va(kern_base)) -
2366 ((unsigned long) KERNBASE));
2367 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
2368
2369 if (do_free)
2370 free_reserved_page(virt_to_page(page));
2371 }
2372 }
2373
2374 #ifdef CONFIG_BLK_DEV_INITRD
2375 void free_initrd_mem(unsigned long start, unsigned long end)
2376 {
2377 free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
2378 "initrd");
2379 }
2380 #endif
2381
2382 pgprot_t PAGE_KERNEL __read_mostly;
2383 EXPORT_SYMBOL(PAGE_KERNEL);
2384
2385 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2386 pgprot_t PAGE_COPY __read_mostly;
2387
2388 pgprot_t PAGE_SHARED __read_mostly;
2389 EXPORT_SYMBOL(PAGE_SHARED);
2390
2391 unsigned long pg_iobits __read_mostly;
2392
2393 unsigned long _PAGE_IE __read_mostly;
2394 EXPORT_SYMBOL(_PAGE_IE);
2395
2396 unsigned long _PAGE_E __read_mostly;
2397 EXPORT_SYMBOL(_PAGE_E);
2398
2399 unsigned long _PAGE_CACHE __read_mostly;
2400 EXPORT_SYMBOL(_PAGE_CACHE);
2401
2402 #ifdef CONFIG_SPARSEMEM_VMEMMAP
2403 int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend,
2404 int node)
2405 {
2406 unsigned long pte_base;
2407
2408 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2409 _PAGE_CP_4U | _PAGE_CV_4U |
2410 _PAGE_P_4U | _PAGE_W_4U);
2411 if (tlb_type == hypervisor)
2412 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2413 page_cache4v_flag | _PAGE_P_4V | _PAGE_W_4V);
2414
2415 pte_base |= _PAGE_PMD_HUGE;
2416
2417 vstart = vstart & PMD_MASK;
2418 vend = ALIGN(vend, PMD_SIZE);
2419 for (; vstart < vend; vstart += PMD_SIZE) {
2420 pgd_t *pgd = pgd_offset_k(vstart);
2421 unsigned long pte;
2422 pud_t *pud;
2423 pmd_t *pmd;
2424
2425 if (pgd_none(*pgd)) {
2426 pud_t *new = vmemmap_alloc_block(PAGE_SIZE, node);
2427
2428 if (!new)
2429 return -ENOMEM;
2430 pgd_populate(&init_mm, pgd, new);
2431 }
2432
2433 pud = pud_offset(pgd, vstart);
2434 if (pud_none(*pud)) {
2435 pmd_t *new = vmemmap_alloc_block(PAGE_SIZE, node);
2436
2437 if (!new)
2438 return -ENOMEM;
2439 pud_populate(&init_mm, pud, new);
2440 }
2441
2442 pmd = pmd_offset(pud, vstart);
2443
2444 pte = pmd_val(*pmd);
2445 if (!(pte & _PAGE_VALID)) {
2446 void *block = vmemmap_alloc_block(PMD_SIZE, node);
2447
2448 if (!block)
2449 return -ENOMEM;
2450
2451 pmd_val(*pmd) = pte_base | __pa(block);
2452 }
2453 }
2454
2455 return 0;
2456 }
2457
2458 void vmemmap_free(unsigned long start, unsigned long end)
2459 {
2460 }
2461 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
2462
2463 static void prot_init_common(unsigned long page_none,
2464 unsigned long page_shared,
2465 unsigned long page_copy,
2466 unsigned long page_readonly,
2467 unsigned long page_exec_bit)
2468 {
2469 PAGE_COPY = __pgprot(page_copy);
2470 PAGE_SHARED = __pgprot(page_shared);
2471
2472 protection_map[0x0] = __pgprot(page_none);
2473 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2474 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2475 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2476 protection_map[0x4] = __pgprot(page_readonly);
2477 protection_map[0x5] = __pgprot(page_readonly);
2478 protection_map[0x6] = __pgprot(page_copy);
2479 protection_map[0x7] = __pgprot(page_copy);
2480 protection_map[0x8] = __pgprot(page_none);
2481 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2482 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2483 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2484 protection_map[0xc] = __pgprot(page_readonly);
2485 protection_map[0xd] = __pgprot(page_readonly);
2486 protection_map[0xe] = __pgprot(page_shared);
2487 protection_map[0xf] = __pgprot(page_shared);
2488 }
2489
2490 static void __init sun4u_pgprot_init(void)
2491 {
2492 unsigned long page_none, page_shared, page_copy, page_readonly;
2493 unsigned long page_exec_bit;
2494 int i;
2495
2496 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2497 _PAGE_CACHE_4U | _PAGE_P_4U |
2498 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2499 _PAGE_EXEC_4U);
2500 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2501 _PAGE_CACHE_4U | _PAGE_P_4U |
2502 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2503 _PAGE_EXEC_4U | _PAGE_L_4U);
2504
2505 _PAGE_IE = _PAGE_IE_4U;
2506 _PAGE_E = _PAGE_E_4U;
2507 _PAGE_CACHE = _PAGE_CACHE_4U;
2508
2509 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2510 __ACCESS_BITS_4U | _PAGE_E_4U);
2511
2512 #ifdef CONFIG_DEBUG_PAGEALLOC
2513 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2514 #else
2515 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2516 PAGE_OFFSET;
2517 #endif
2518 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2519 _PAGE_P_4U | _PAGE_W_4U);
2520
2521 for (i = 1; i < 4; i++)
2522 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2523
2524 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2525 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2526 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2527
2528
2529 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2530 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2531 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2532 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2533 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2534 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2535 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2536
2537 page_exec_bit = _PAGE_EXEC_4U;
2538
2539 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2540 page_exec_bit);
2541 }
2542
2543 static void __init sun4v_pgprot_init(void)
2544 {
2545 unsigned long page_none, page_shared, page_copy, page_readonly;
2546 unsigned long page_exec_bit;
2547 int i;
2548
2549 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2550 page_cache4v_flag | _PAGE_P_4V |
2551 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2552 _PAGE_EXEC_4V);
2553 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
2554
2555 _PAGE_IE = _PAGE_IE_4V;
2556 _PAGE_E = _PAGE_E_4V;
2557 _PAGE_CACHE = page_cache4v_flag;
2558
2559 #ifdef CONFIG_DEBUG_PAGEALLOC
2560 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2561 #else
2562 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2563 PAGE_OFFSET;
2564 #endif
2565 kern_linear_pte_xor[0] |= (page_cache4v_flag | _PAGE_P_4V |
2566 _PAGE_W_4V);
2567
2568 for (i = 1; i < 4; i++)
2569 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2570
2571 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2572 __ACCESS_BITS_4V | _PAGE_E_4V);
2573
2574 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2575 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2576 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2577 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2578
2579 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | page_cache4v_flag;
2580 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2581 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2582 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2583 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2584 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2585 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2586
2587 page_exec_bit = _PAGE_EXEC_4V;
2588
2589 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2590 page_exec_bit);
2591 }
2592
2593 unsigned long pte_sz_bits(unsigned long sz)
2594 {
2595 if (tlb_type == hypervisor) {
2596 switch (sz) {
2597 case 8 * 1024:
2598 default:
2599 return _PAGE_SZ8K_4V;
2600 case 64 * 1024:
2601 return _PAGE_SZ64K_4V;
2602 case 512 * 1024:
2603 return _PAGE_SZ512K_4V;
2604 case 4 * 1024 * 1024:
2605 return _PAGE_SZ4MB_4V;
2606 }
2607 } else {
2608 switch (sz) {
2609 case 8 * 1024:
2610 default:
2611 return _PAGE_SZ8K_4U;
2612 case 64 * 1024:
2613 return _PAGE_SZ64K_4U;
2614 case 512 * 1024:
2615 return _PAGE_SZ512K_4U;
2616 case 4 * 1024 * 1024:
2617 return _PAGE_SZ4MB_4U;
2618 }
2619 }
2620 }
2621
2622 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2623 {
2624 pte_t pte;
2625
2626 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
2627 pte_val(pte) |= (((unsigned long)space) << 32);
2628 pte_val(pte) |= pte_sz_bits(page_size);
2629
2630 return pte;
2631 }
2632
2633 static unsigned long kern_large_tte(unsigned long paddr)
2634 {
2635 unsigned long val;
2636
2637 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2638 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2639 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2640 if (tlb_type == hypervisor)
2641 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2642 page_cache4v_flag | _PAGE_P_4V |
2643 _PAGE_EXEC_4V | _PAGE_W_4V);
2644
2645 return val | paddr;
2646 }
2647
2648 /* If not locked, zap it. */
2649 void __flush_tlb_all(void)
2650 {
2651 unsigned long pstate;
2652 int i;
2653
2654 __asm__ __volatile__("flushw\n\t"
2655 "rdpr %%pstate, %0\n\t"
2656 "wrpr %0, %1, %%pstate"
2657 : "=r" (pstate)
2658 : "i" (PSTATE_IE));
2659 if (tlb_type == hypervisor) {
2660 sun4v_mmu_demap_all();
2661 } else if (tlb_type == spitfire) {
2662 for (i = 0; i < 64; i++) {
2663 /* Spitfire Errata #32 workaround */
2664 /* NOTE: Always runs on spitfire, so no
2665 * cheetah+ page size encodings.
2666 */
2667 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2668 "flush %%g6"
2669 : /* No outputs */
2670 : "r" (0),
2671 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2672
2673 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2674 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2675 "membar #Sync"
2676 : /* no outputs */
2677 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2678 spitfire_put_dtlb_data(i, 0x0UL);
2679 }
2680
2681 /* Spitfire Errata #32 workaround */
2682 /* NOTE: Always runs on spitfire, so no
2683 * cheetah+ page size encodings.
2684 */
2685 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2686 "flush %%g6"
2687 : /* No outputs */
2688 : "r" (0),
2689 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2690
2691 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2692 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2693 "membar #Sync"
2694 : /* no outputs */
2695 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2696 spitfire_put_itlb_data(i, 0x0UL);
2697 }
2698 }
2699 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2700 cheetah_flush_dtlb_all();
2701 cheetah_flush_itlb_all();
2702 }
2703 __asm__ __volatile__("wrpr %0, 0, %%pstate"
2704 : : "r" (pstate));
2705 }
2706
2707 pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
2708 unsigned long address)
2709 {
2710 struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK | __GFP_ZERO);
2711 pte_t *pte = NULL;
2712
2713 if (page)
2714 pte = (pte_t *) page_address(page);
2715
2716 return pte;
2717 }
2718
2719 pgtable_t pte_alloc_one(struct mm_struct *mm,
2720 unsigned long address)
2721 {
2722 struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK | __GFP_ZERO);
2723 if (!page)
2724 return NULL;
2725 if (!pgtable_page_ctor(page)) {
2726 free_hot_cold_page(page, 0);
2727 return NULL;
2728 }
2729 return (pte_t *) page_address(page);
2730 }
2731
2732 void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
2733 {
2734 free_page((unsigned long)pte);
2735 }
2736
2737 static void __pte_free(pgtable_t pte)
2738 {
2739 struct page *page = virt_to_page(pte);
2740
2741 pgtable_page_dtor(page);
2742 __free_page(page);
2743 }
2744
2745 void pte_free(struct mm_struct *mm, pgtable_t pte)
2746 {
2747 __pte_free(pte);
2748 }
2749
2750 void pgtable_free(void *table, bool is_page)
2751 {
2752 if (is_page)
2753 __pte_free(table);
2754 else
2755 kmem_cache_free(pgtable_cache, table);
2756 }
2757
2758 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
2759 void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
2760 pmd_t *pmd)
2761 {
2762 unsigned long pte, flags;
2763 struct mm_struct *mm;
2764 pmd_t entry = *pmd;
2765
2766 if (!pmd_large(entry) || !pmd_young(entry))
2767 return;
2768
2769 pte = pmd_val(entry);
2770
2771 /* Don't insert a non-valid PMD into the TSB, we'll deadlock. */
2772 if (!(pte & _PAGE_VALID))
2773 return;
2774
2775 /* We are fabricating 8MB pages using 4MB real hw pages. */
2776 pte |= (addr & (1UL << REAL_HPAGE_SHIFT));
2777
2778 mm = vma->vm_mm;
2779
2780 spin_lock_irqsave(&mm->context.lock, flags);
2781
2782 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL)
2783 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
2784 addr, pte);
2785
2786 spin_unlock_irqrestore(&mm->context.lock, flags);
2787 }
2788 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
2789
2790 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
2791 static void context_reload(void *__data)
2792 {
2793 struct mm_struct *mm = __data;
2794
2795 if (mm == current->mm)
2796 load_secondary_context(mm);
2797 }
2798
2799 void hugetlb_setup(struct pt_regs *regs)
2800 {
2801 struct mm_struct *mm = current->mm;
2802 struct tsb_config *tp;
2803
2804 if (faulthandler_disabled() || !mm) {
2805 const struct exception_table_entry *entry;
2806
2807 entry = search_exception_tables(regs->tpc);
2808 if (entry) {
2809 regs->tpc = entry->fixup;
2810 regs->tnpc = regs->tpc + 4;
2811 return;
2812 }
2813 pr_alert("Unexpected HugeTLB setup in atomic context.\n");
2814 die_if_kernel("HugeTSB in atomic", regs);
2815 }
2816
2817 tp = &mm->context.tsb_block[MM_TSB_HUGE];
2818 if (likely(tp->tsb == NULL))
2819 tsb_grow(mm, MM_TSB_HUGE, 0);
2820
2821 tsb_context_switch(mm);
2822 smp_tsb_sync(mm);
2823
2824 /* On UltraSPARC-III+ and later, configure the second half of
2825 * the Data-TLB for huge pages.
2826 */
2827 if (tlb_type == cheetah_plus) {
2828 bool need_context_reload = false;
2829 unsigned long ctx;
2830
2831 spin_lock_irq(&ctx_alloc_lock);
2832 ctx = mm->context.sparc64_ctx_val;
2833 ctx &= ~CTX_PGSZ_MASK;
2834 ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT;
2835 ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT;
2836
2837 if (ctx != mm->context.sparc64_ctx_val) {
2838 /* When changing the page size fields, we
2839 * must perform a context flush so that no
2840 * stale entries match. This flush must
2841 * occur with the original context register
2842 * settings.
2843 */
2844 do_flush_tlb_mm(mm);
2845
2846 /* Reload the context register of all processors
2847 * also executing in this address space.
2848 */
2849 mm->context.sparc64_ctx_val = ctx;
2850 need_context_reload = true;
2851 }
2852 spin_unlock_irq(&ctx_alloc_lock);
2853
2854 if (need_context_reload)
2855 on_each_cpu(context_reload, mm, 0);
2856 }
2857 }
2858 #endif
2859
2860 static struct resource code_resource = {
2861 .name = "Kernel code",
2862 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
2863 };
2864
2865 static struct resource data_resource = {
2866 .name = "Kernel data",
2867 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
2868 };
2869
2870 static struct resource bss_resource = {
2871 .name = "Kernel bss",
2872 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
2873 };
2874
2875 static inline resource_size_t compute_kern_paddr(void *addr)
2876 {
2877 return (resource_size_t) (addr - KERNBASE + kern_base);
2878 }
2879
2880 static void __init kernel_lds_init(void)
2881 {
2882 code_resource.start = compute_kern_paddr(_text);
2883 code_resource.end = compute_kern_paddr(_etext - 1);
2884 data_resource.start = compute_kern_paddr(_etext);
2885 data_resource.end = compute_kern_paddr(_edata - 1);
2886 bss_resource.start = compute_kern_paddr(__bss_start);
2887 bss_resource.end = compute_kern_paddr(_end - 1);
2888 }
2889
2890 static int __init report_memory(void)
2891 {
2892 int i;
2893 struct resource *res;
2894
2895 kernel_lds_init();
2896
2897 for (i = 0; i < pavail_ents; i++) {
2898 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
2899
2900 if (!res) {
2901 pr_warn("Failed to allocate source.\n");
2902 break;
2903 }
2904
2905 res->name = "System RAM";
2906 res->start = pavail[i].phys_addr;
2907 res->end = pavail[i].phys_addr + pavail[i].reg_size - 1;
2908 res->flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM;
2909
2910 if (insert_resource(&iomem_resource, res) < 0) {
2911 pr_warn("Resource insertion failed.\n");
2912 break;
2913 }
2914
2915 insert_resource(res, &code_resource);
2916 insert_resource(res, &data_resource);
2917 insert_resource(res, &bss_resource);
2918 }
2919
2920 return 0;
2921 }
2922 arch_initcall(report_memory);
2923
2924 #ifdef CONFIG_SMP
2925 #define do_flush_tlb_kernel_range smp_flush_tlb_kernel_range
2926 #else
2927 #define do_flush_tlb_kernel_range __flush_tlb_kernel_range
2928 #endif
2929
2930 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
2931 {
2932 if (start < HI_OBP_ADDRESS && end > LOW_OBP_ADDRESS) {
2933 if (start < LOW_OBP_ADDRESS) {
2934 flush_tsb_kernel_range(start, LOW_OBP_ADDRESS);
2935 do_flush_tlb_kernel_range(start, LOW_OBP_ADDRESS);
2936 }
2937 if (end > HI_OBP_ADDRESS) {
2938 flush_tsb_kernel_range(HI_OBP_ADDRESS, end);
2939 do_flush_tlb_kernel_range(HI_OBP_ADDRESS, end);
2940 }
2941 } else {
2942 flush_tsb_kernel_range(start, end);
2943 do_flush_tlb_kernel_range(start, end);
2944 }
2945 }
Linux with added FPC-III support