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Linux 2.6.21-rc3
[linux/fpc-iii.git] / drivers / pci / hotplug / pciehp_hpc.c
blobfbc64aa2dd68a32f24d21fde630665e316150d65
1 /*
2 * PCI Express PCI Hot Plug Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
27 *
28 */
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/signal.h>
34 #include <linux/jiffies.h>
35 #include <linux/timer.h>
36 #include <linux/pci.h>
37 #include <linux/interrupt.h>
38 #include <linux/time.h>
39
40 #include "../pci.h"
41 #include "pciehp.h"
42 #ifdef DEBUG
43 #define DBG_K_TRACE_ENTRY ((unsigned int)0x00000001) /* On function entry */
44 #define DBG_K_TRACE_EXIT ((unsigned int)0x00000002) /* On function exit */
45 #define DBG_K_INFO ((unsigned int)0x00000004) /* Info messages */
46 #define DBG_K_ERROR ((unsigned int)0x00000008) /* Error messages */
47 #define DBG_K_TRACE (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT)
48 #define DBG_K_STANDARD (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE)
49 /* Redefine this flagword to set debug level */
50 #define DEBUG_LEVEL DBG_K_STANDARD
51
52 #define DEFINE_DBG_BUFFER char __dbg_str_buf[256];
53
54 #define DBG_PRINT( dbg_flags, args... ) \
55 do { \
56 if ( DEBUG_LEVEL & ( dbg_flags ) ) \
57 { \
58 int len; \
59 len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \
60 __FILE__, __LINE__, __FUNCTION__ ); \
61 sprintf( __dbg_str_buf + len, args ); \
62 printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \
63 } \
64 } while (0)
65
66 #define DBG_ENTER_ROUTINE DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]");
67 #define DBG_LEAVE_ROUTINE DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]");
68 #else
69 #define DEFINE_DBG_BUFFER
70 #define DBG_ENTER_ROUTINE
71 #define DBG_LEAVE_ROUTINE
72 #endif /* DEBUG */
73
74 struct ctrl_reg {
75 u8 cap_id;
76 u8 nxt_ptr;
77 u16 cap_reg;
78 u32 dev_cap;
79 u16 dev_ctrl;
80 u16 dev_status;
81 u32 lnk_cap;
82 u16 lnk_ctrl;
83 u16 lnk_status;
84 u32 slot_cap;
85 u16 slot_ctrl;
86 u16 slot_status;
87 u16 root_ctrl;
88 u16 rsvp;
89 u32 root_status;
90 } __attribute__ ((packed));
91
92 /* offsets to the controller registers based on the above structure layout */
93 enum ctrl_offsets {
94 PCIECAPID = offsetof(struct ctrl_reg, cap_id),
95 NXTCAPPTR = offsetof(struct ctrl_reg, nxt_ptr),
96 CAPREG = offsetof(struct ctrl_reg, cap_reg),
97 DEVCAP = offsetof(struct ctrl_reg, dev_cap),
98 DEVCTRL = offsetof(struct ctrl_reg, dev_ctrl),
99 DEVSTATUS = offsetof(struct ctrl_reg, dev_status),
100 LNKCAP = offsetof(struct ctrl_reg, lnk_cap),
101 LNKCTRL = offsetof(struct ctrl_reg, lnk_ctrl),
102 LNKSTATUS = offsetof(struct ctrl_reg, lnk_status),
103 SLOTCAP = offsetof(struct ctrl_reg, slot_cap),
104 SLOTCTRL = offsetof(struct ctrl_reg, slot_ctrl),
105 SLOTSTATUS = offsetof(struct ctrl_reg, slot_status),
106 ROOTCTRL = offsetof(struct ctrl_reg, root_ctrl),
107 ROOTSTATUS = offsetof(struct ctrl_reg, root_status),
108 };
109
110 static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value)
111 {
112 struct pci_dev *dev = ctrl->pci_dev;
113 return pci_read_config_word(dev, ctrl->cap_base + reg, value);
114 }
115
116 static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value)
117 {
118 struct pci_dev *dev = ctrl->pci_dev;
119 return pci_read_config_dword(dev, ctrl->cap_base + reg, value);
120 }
121
122 static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value)
123 {
124 struct pci_dev *dev = ctrl->pci_dev;
125 return pci_write_config_word(dev, ctrl->cap_base + reg, value);
126 }
127
128 static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value)
129 {
130 struct pci_dev *dev = ctrl->pci_dev;
131 return pci_write_config_dword(dev, ctrl->cap_base + reg, value);
132 }
133
134 /* Field definitions in PCI Express Capabilities Register */
135 #define CAP_VER 0x000F
136 #define DEV_PORT_TYPE 0x00F0
137 #define SLOT_IMPL 0x0100
138 #define MSG_NUM 0x3E00
139
140 /* Device or Port Type */
141 #define NAT_ENDPT 0x00
142 #define LEG_ENDPT 0x01
143 #define ROOT_PORT 0x04
144 #define UP_STREAM 0x05
145 #define DN_STREAM 0x06
146 #define PCIE_PCI_BRDG 0x07
147 #define PCI_PCIE_BRDG 0x10
148
149 /* Field definitions in Device Capabilities Register */
150 #define DATTN_BUTTN_PRSN 0x1000
151 #define DATTN_LED_PRSN 0x2000
152 #define DPWR_LED_PRSN 0x4000
153
154 /* Field definitions in Link Capabilities Register */
155 #define MAX_LNK_SPEED 0x000F
156 #define MAX_LNK_WIDTH 0x03F0
157
158 /* Link Width Encoding */
159 #define LNK_X1 0x01
160 #define LNK_X2 0x02
161 #define LNK_X4 0x04
162 #define LNK_X8 0x08
163 #define LNK_X12 0x0C
164 #define LNK_X16 0x10
165 #define LNK_X32 0x20
166
167 /*Field definitions of Link Status Register */
168 #define LNK_SPEED 0x000F
169 #define NEG_LINK_WD 0x03F0
170 #define LNK_TRN_ERR 0x0400
171 #define LNK_TRN 0x0800
172 #define SLOT_CLK_CONF 0x1000
173
174 /* Field definitions in Slot Capabilities Register */
175 #define ATTN_BUTTN_PRSN 0x00000001
176 #define PWR_CTRL_PRSN 0x00000002
177 #define MRL_SENS_PRSN 0x00000004
178 #define ATTN_LED_PRSN 0x00000008
179 #define PWR_LED_PRSN 0x00000010
180 #define HP_SUPR_RM_SUP 0x00000020
181 #define HP_CAP 0x00000040
182 #define SLOT_PWR_VALUE 0x000003F8
183 #define SLOT_PWR_LIMIT 0x00000C00
184 #define PSN 0xFFF80000 /* PSN: Physical Slot Number */
185
186 /* Field definitions in Slot Control Register */
187 #define ATTN_BUTTN_ENABLE 0x0001
188 #define PWR_FAULT_DETECT_ENABLE 0x0002
189 #define MRL_DETECT_ENABLE 0x0004
190 #define PRSN_DETECT_ENABLE 0x0008
191 #define CMD_CMPL_INTR_ENABLE 0x0010
192 #define HP_INTR_ENABLE 0x0020
193 #define ATTN_LED_CTRL 0x00C0
194 #define PWR_LED_CTRL 0x0300
195 #define PWR_CTRL 0x0400
196 #define EMI_CTRL 0x0800
197
198 /* Attention indicator and Power indicator states */
199 #define LED_ON 0x01
200 #define LED_BLINK 0x10
201 #define LED_OFF 0x11
202
203 /* Power Control Command */
204 #define POWER_ON 0
205 #define POWER_OFF 0x0400
206
207 /* EMI Status defines */
208 #define EMI_DISENGAGED 0
209 #define EMI_ENGAGED 1
210
211 /* Field definitions in Slot Status Register */
212 #define ATTN_BUTTN_PRESSED 0x0001
213 #define PWR_FAULT_DETECTED 0x0002
214 #define MRL_SENS_CHANGED 0x0004
215 #define PRSN_DETECT_CHANGED 0x0008
216 #define CMD_COMPLETED 0x0010
217 #define MRL_STATE 0x0020
218 #define PRSN_STATE 0x0040
219 #define EMI_STATE 0x0080
220 #define EMI_STATUS_BIT 7
221
222 static spinlock_t hpc_event_lock;
223
224 DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */
225 static int ctlr_seq_num = 0; /* Controller sequence # */
226
227 static irqreturn_t pcie_isr(int irq, void *dev_id);
228 static void start_int_poll_timer(struct controller *ctrl, int sec);
229
230 /* This is the interrupt polling timeout function. */
231 static void int_poll_timeout(unsigned long data)
232 {
233 struct controller *ctrl = (struct controller *)data;
234
235 DBG_ENTER_ROUTINE
236
237 /* Poll for interrupt events. regs == NULL => polling */
238 pcie_isr(0, ctrl);
239
240 init_timer(&ctrl->poll_timer);
241 if (!pciehp_poll_time)
242 pciehp_poll_time = 2; /* reset timer to poll in 2 secs if user doesn't specify at module installation*/
243
244 start_int_poll_timer(ctrl, pciehp_poll_time);
245 }
246
247 /* This function starts the interrupt polling timer. */
248 static void start_int_poll_timer(struct controller *ctrl, int sec)
249 {
250 /* Clamp to sane value */
251 if ((sec <= 0) || (sec > 60))
252 sec = 2;
253
254 ctrl->poll_timer.function = &int_poll_timeout;
255 ctrl->poll_timer.data = (unsigned long)ctrl;
256 ctrl->poll_timer.expires = jiffies + sec * HZ;
257 add_timer(&ctrl->poll_timer);
258 }
259
260 static inline int pcie_wait_cmd(struct controller *ctrl)
261 {
262 int retval = 0;
263 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
264 unsigned long timeout = msecs_to_jiffies(msecs);
265 int rc;
266
267 rc = wait_event_interruptible_timeout(ctrl->queue,
268 !ctrl->cmd_busy, timeout);
269 if (!rc)
270 dbg("Command not completed in 1000 msec\n");
271 else if (rc < 0) {
272 retval = -EINTR;
273 info("Command was interrupted by a signal\n");
274 }
275
276 return retval;
277 }
278
279 static int pcie_write_cmd(struct slot *slot, u16 cmd)
280 {
281 struct controller *ctrl = slot->ctrl;
282 int retval = 0;
283 u16 slot_status;
284
285 DBG_ENTER_ROUTINE
286
287 mutex_lock(&ctrl->ctrl_lock);
288
289 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
290 if (retval) {
291 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
292 goto out;
293 }
294
295 if ((slot_status & CMD_COMPLETED) == CMD_COMPLETED ) {
296 /* After 1 sec and CMD_COMPLETED still not set, just
297 proceed forward to issue the next command according
298 to spec. Just print out the error message */
299 dbg("%s: CMD_COMPLETED not clear after 1 sec.\n",
300 __FUNCTION__);
301 }
302
303 ctrl->cmd_busy = 1;
304 retval = pciehp_writew(ctrl, SLOTCTRL, (cmd | CMD_CMPL_INTR_ENABLE));
305 if (retval) {
306 err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__);
307 goto out;
308 }
309
310 /*
311 * Wait for command completion.
312 */
313 retval = pcie_wait_cmd(ctrl);
314 out:
315 mutex_unlock(&ctrl->ctrl_lock);
316 DBG_LEAVE_ROUTINE
317 return retval;
318 }
319
320 static int hpc_check_lnk_status(struct controller *ctrl)
321 {
322 u16 lnk_status;
323 int retval = 0;
324
325 DBG_ENTER_ROUTINE
326
327 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
328 if (retval) {
329 err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__);
330 return retval;
331 }
332
333 dbg("%s: lnk_status = %x\n", __FUNCTION__, lnk_status);
334 if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) ||
335 !(lnk_status & NEG_LINK_WD)) {
336 err("%s : Link Training Error occurs \n", __FUNCTION__);
337 retval = -1;
338 return retval;
339 }
340
341 DBG_LEAVE_ROUTINE
342 return retval;
343 }
344
345
346 static int hpc_get_attention_status(struct slot *slot, u8 *status)
347 {
348 struct controller *ctrl = slot->ctrl;
349 u16 slot_ctrl;
350 u8 atten_led_state;
351 int retval = 0;
352
353 DBG_ENTER_ROUTINE
354
355 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
356 if (retval) {
357 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
358 return retval;
359 }
360
361 dbg("%s: SLOTCTRL %x, value read %x\n",
362 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
363
364 atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6;
365
366 switch (atten_led_state) {
367 case 0:
368 *status = 0xFF; /* Reserved */
369 break;
370 case 1:
371 *status = 1; /* On */
372 break;
373 case 2:
374 *status = 2; /* Blink */
375 break;
376 case 3:
377 *status = 0; /* Off */
378 break;
379 default:
380 *status = 0xFF;
381 break;
382 }
383
384 DBG_LEAVE_ROUTINE
385 return 0;
386 }
387
388 static int hpc_get_power_status(struct slot *slot, u8 *status)
389 {
390 struct controller *ctrl = slot->ctrl;
391 u16 slot_ctrl;
392 u8 pwr_state;
393 int retval = 0;
394
395 DBG_ENTER_ROUTINE
396
397 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
398 if (retval) {
399 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
400 return retval;
401 }
402 dbg("%s: SLOTCTRL %x value read %x\n",
403 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
404
405 pwr_state = (slot_ctrl & PWR_CTRL) >> 10;
406
407 switch (pwr_state) {
408 case 0:
409 *status = 1;
410 break;
411 case 1:
412 *status = 0;
413 break;
414 default:
415 *status = 0xFF;
416 break;
417 }
418
419 DBG_LEAVE_ROUTINE
420 return retval;
421 }
422
423
424 static int hpc_get_latch_status(struct slot *slot, u8 *status)
425 {
426 struct controller *ctrl = slot->ctrl;
427 u16 slot_status;
428 int retval = 0;
429
430 DBG_ENTER_ROUTINE
431
432 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
433 if (retval) {
434 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
435 return retval;
436 }
437
438 *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1;
439
440 DBG_LEAVE_ROUTINE
441 return 0;
442 }
443
444 static int hpc_get_adapter_status(struct slot *slot, u8 *status)
445 {
446 struct controller *ctrl = slot->ctrl;
447 u16 slot_status;
448 u8 card_state;
449 int retval = 0;
450
451 DBG_ENTER_ROUTINE
452
453 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
454 if (retval) {
455 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
456 return retval;
457 }
458 card_state = (u8)((slot_status & PRSN_STATE) >> 6);
459 *status = (card_state == 1) ? 1 : 0;
460
461 DBG_LEAVE_ROUTINE
462 return 0;
463 }
464
465 static int hpc_query_power_fault(struct slot *slot)
466 {
467 struct controller *ctrl = slot->ctrl;
468 u16 slot_status;
469 u8 pwr_fault;
470 int retval = 0;
471
472 DBG_ENTER_ROUTINE
473
474 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
475 if (retval) {
476 err("%s: Cannot check for power fault\n", __FUNCTION__);
477 return retval;
478 }
479 pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1);
480
481 DBG_LEAVE_ROUTINE
482 return pwr_fault;
483 }
484
485 static int hpc_get_emi_status(struct slot *slot, u8 *status)
486 {
487 struct controller *ctrl = slot->ctrl;
488 u16 slot_status;
489 int retval = 0;
490
491 DBG_ENTER_ROUTINE
492
493 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
494 if (retval) {
495 err("%s : Cannot check EMI status\n", __FUNCTION__);
496 return retval;
497 }
498 *status = (slot_status & EMI_STATE) >> EMI_STATUS_BIT;
499
500 DBG_LEAVE_ROUTINE
501 return retval;
502 }
503
504 static int hpc_toggle_emi(struct slot *slot)
505 {
506 struct controller *ctrl = slot->ctrl;
507 u16 slot_cmd = 0;
508 u16 slot_ctrl;
509 int rc = 0;
510
511 DBG_ENTER_ROUTINE
512
513 rc = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
514 if (rc) {
515 err("%s : hp_register_read_word SLOT_CTRL failed\n",
516 __FUNCTION__);
517 return rc;
518 }
519
520 slot_cmd = (slot_ctrl | EMI_CTRL);
521 if (!pciehp_poll_mode)
522 slot_cmd = slot_cmd | HP_INTR_ENABLE;
523
524 pcie_write_cmd(slot, slot_cmd);
525 slot->last_emi_toggle = get_seconds();
526 DBG_LEAVE_ROUTINE
527 return rc;
528 }
529
530 static int hpc_set_attention_status(struct slot *slot, u8 value)
531 {
532 struct controller *ctrl = slot->ctrl;
533 u16 slot_cmd = 0;
534 u16 slot_ctrl;
535 int rc = 0;
536
537 DBG_ENTER_ROUTINE
538
539 rc = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
540 if (rc) {
541 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
542 return rc;
543 }
544
545 switch (value) {
546 case 0 : /* turn off */
547 slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x00C0;
548 break;
549 case 1: /* turn on */
550 slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x0040;
551 break;
552 case 2: /* turn blink */
553 slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x0080;
554 break;
555 default:
556 return -1;
557 }
558 if (!pciehp_poll_mode)
559 slot_cmd = slot_cmd | HP_INTR_ENABLE;
560
561 pcie_write_cmd(slot, slot_cmd);
562 dbg("%s: SLOTCTRL %x write cmd %x\n",
563 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
564
565 DBG_LEAVE_ROUTINE
566 return rc;
567 }
568
569
570 static void hpc_set_green_led_on(struct slot *slot)
571 {
572 struct controller *ctrl = slot->ctrl;
573 u16 slot_cmd;
574 u16 slot_ctrl;
575 int rc = 0;
576
577 DBG_ENTER_ROUTINE
578
579 rc = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
580 if (rc) {
581 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
582 return;
583 }
584 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0100;
585 if (!pciehp_poll_mode)
586 slot_cmd = slot_cmd | HP_INTR_ENABLE;
587
588 pcie_write_cmd(slot, slot_cmd);
589
590 dbg("%s: SLOTCTRL %x write cmd %x\n",
591 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
592 DBG_LEAVE_ROUTINE
593 return;
594 }
595
596 static void hpc_set_green_led_off(struct slot *slot)
597 {
598 struct controller *ctrl = slot->ctrl;
599 u16 slot_cmd;
600 u16 slot_ctrl;
601 int rc = 0;
602
603 DBG_ENTER_ROUTINE
604
605 rc = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
606 if (rc) {
607 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
608 return;
609 }
610
611 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0300;
612
613 if (!pciehp_poll_mode)
614 slot_cmd = slot_cmd | HP_INTR_ENABLE;
615 pcie_write_cmd(slot, slot_cmd);
616 dbg("%s: SLOTCTRL %x write cmd %x\n",
617 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
618
619 DBG_LEAVE_ROUTINE
620 return;
621 }
622
623 static void hpc_set_green_led_blink(struct slot *slot)
624 {
625 struct controller *ctrl = slot->ctrl;
626 u16 slot_cmd;
627 u16 slot_ctrl;
628 int rc = 0;
629
630 DBG_ENTER_ROUTINE
631
632 rc = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
633 if (rc) {
634 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
635 return;
636 }
637
638 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0200;
639
640 if (!pciehp_poll_mode)
641 slot_cmd = slot_cmd | HP_INTR_ENABLE;
642 pcie_write_cmd(slot, slot_cmd);
643
644 dbg("%s: SLOTCTRL %x write cmd %x\n",
645 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
646 DBG_LEAVE_ROUTINE
647 return;
648 }
649
650 static void hpc_release_ctlr(struct controller *ctrl)
651 {
652 DBG_ENTER_ROUTINE
653
654 if (pciehp_poll_mode)
655 del_timer(&ctrl->poll_timer);
656 else
657 free_irq(ctrl->pci_dev->irq, ctrl);
658
659 DBG_LEAVE_ROUTINE
660 }
661
662 static int hpc_power_on_slot(struct slot * slot)
663 {
664 struct controller *ctrl = slot->ctrl;
665 u16 slot_cmd;
666 u16 slot_ctrl, slot_status;
667 int retval = 0;
668
669 DBG_ENTER_ROUTINE
670
671 dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot);
672
673 /* Clear sticky power-fault bit from previous power failures */
674 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
675 if (retval) {
676 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
677 return retval;
678 }
679 slot_status &= PWR_FAULT_DETECTED;
680 if (slot_status) {
681 retval = pciehp_writew(ctrl, SLOTSTATUS, slot_status);
682 if (retval) {
683 err("%s: Cannot write to SLOTSTATUS register\n",
684 __FUNCTION__);
685 return retval;
686 }
687 }
688
689 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
690 if (retval) {
691 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
692 return retval;
693 }
694
695 slot_cmd = (slot_ctrl & ~PWR_CTRL) | POWER_ON;
696
697 /* Enable detection that we turned off at slot power-off time */
698 if (!pciehp_poll_mode)
699 slot_cmd = slot_cmd |
700 PWR_FAULT_DETECT_ENABLE |
701 MRL_DETECT_ENABLE |
702 PRSN_DETECT_ENABLE |
703 HP_INTR_ENABLE;
704
705 retval = pcie_write_cmd(slot, slot_cmd);
706
707 if (retval) {
708 err("%s: Write %x command failed!\n", __FUNCTION__, slot_cmd);
709 return -1;
710 }
711 dbg("%s: SLOTCTRL %x write cmd %x\n",
712 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
713
714 DBG_LEAVE_ROUTINE
715
716 return retval;
717 }
718
719 static int hpc_power_off_slot(struct slot * slot)
720 {
721 struct controller *ctrl = slot->ctrl;
722 u16 slot_cmd;
723 u16 slot_ctrl;
724 int retval = 0;
725
726 DBG_ENTER_ROUTINE
727
728 dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot);
729
730 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
731 if (retval) {
732 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
733 return retval;
734 }
735
736 slot_cmd = (slot_ctrl & ~PWR_CTRL) | POWER_OFF;
737
738 /*
739 * If we get MRL or presence detect interrupts now, the isr
740 * will notice the sticky power-fault bit too and issue power
741 * indicator change commands. This will lead to an endless loop
742 * of command completions, since the power-fault bit remains on
743 * till the slot is powered on again.
744 */
745 if (!pciehp_poll_mode)
746 slot_cmd = (slot_cmd &
747 ~PWR_FAULT_DETECT_ENABLE &
748 ~MRL_DETECT_ENABLE &
749 ~PRSN_DETECT_ENABLE) | HP_INTR_ENABLE;
750
751 retval = pcie_write_cmd(slot, slot_cmd);
752
753 if (retval) {
754 err("%s: Write command failed!\n", __FUNCTION__);
755 return -1;
756 }
757 dbg("%s: SLOTCTRL %x write cmd %x\n",
758 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
759
760 DBG_LEAVE_ROUTINE
761
762 return retval;
763 }
764
765 static irqreturn_t pcie_isr(int irq, void *dev_id)
766 {
767 struct controller *ctrl = (struct controller *)dev_id;
768 u16 slot_status, intr_detect, intr_loc;
769 u16 temp_word;
770 int hp_slot = 0; /* only 1 slot per PCI Express port */
771 int rc = 0;
772
773 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
774 if (rc) {
775 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
776 return IRQ_NONE;
777 }
778
779 intr_detect = ( ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED | MRL_SENS_CHANGED |
780 PRSN_DETECT_CHANGED | CMD_COMPLETED );
781
782 intr_loc = slot_status & intr_detect;
783
784 /* Check to see if it was our interrupt */
785 if ( !intr_loc )
786 return IRQ_NONE;
787
788 dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc);
789 /* Mask Hot-plug Interrupt Enable */
790 if (!pciehp_poll_mode) {
791 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
792 if (rc) {
793 err("%s: Cannot read SLOT_CTRL register\n",
794 __FUNCTION__);
795 return IRQ_NONE;
796 }
797
798 dbg("%s: pciehp_readw(SLOTCTRL) with value %x\n",
799 __FUNCTION__, temp_word);
800 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00;
801 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
802 if (rc) {
803 err("%s: Cannot write to SLOTCTRL register\n",
804 __FUNCTION__);
805 return IRQ_NONE;
806 }
807
808 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
809 if (rc) {
810 err("%s: Cannot read SLOT_STATUS register\n",
811 __FUNCTION__);
812 return IRQ_NONE;
813 }
814 dbg("%s: pciehp_readw(SLOTSTATUS) with value %x\n",
815 __FUNCTION__, slot_status);
816
817 /* Clear command complete interrupt caused by this write */
818 temp_word = 0x1f;
819 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
820 if (rc) {
821 err("%s: Cannot write to SLOTSTATUS register\n",
822 __FUNCTION__);
823 return IRQ_NONE;
824 }
825 }
826
827 if (intr_loc & CMD_COMPLETED) {
828 /*
829 * Command Complete Interrupt Pending
830 */
831 ctrl->cmd_busy = 0;
832 wake_up_interruptible(&ctrl->queue);
833 }
834
835 if (intr_loc & MRL_SENS_CHANGED)
836 pciehp_handle_switch_change(hp_slot, ctrl);
837
838 if (intr_loc & ATTN_BUTTN_PRESSED)
839 pciehp_handle_attention_button(hp_slot, ctrl);
840
841 if (intr_loc & PRSN_DETECT_CHANGED)
842 pciehp_handle_presence_change(hp_slot, ctrl);
843
844 if (intr_loc & PWR_FAULT_DETECTED)
845 pciehp_handle_power_fault(hp_slot, ctrl);
846
847 /* Clear all events after serving them */
848 temp_word = 0x1F;
849 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
850 if (rc) {
851 err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__);
852 return IRQ_NONE;
853 }
854 /* Unmask Hot-plug Interrupt Enable */
855 if (!pciehp_poll_mode) {
856 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
857 if (rc) {
858 err("%s: Cannot read SLOTCTRL register\n",
859 __FUNCTION__);
860 return IRQ_NONE;
861 }
862
863 dbg("%s: Unmask Hot-plug Interrupt Enable\n", __FUNCTION__);
864 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
865
866 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
867 if (rc) {
868 err("%s: Cannot write to SLOTCTRL register\n",
869 __FUNCTION__);
870 return IRQ_NONE;
871 }
872
873 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
874 if (rc) {
875 err("%s: Cannot read SLOT_STATUS register\n",
876 __FUNCTION__);
877 return IRQ_NONE;
878 }
879
880 /* Clear command complete interrupt caused by this write */
881 temp_word = 0x1F;
882 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
883 if (rc) {
884 err("%s: Cannot write to SLOTSTATUS failed\n",
885 __FUNCTION__);
886 return IRQ_NONE;
887 }
888 dbg("%s: pciehp_writew(SLOTSTATUS) with value %x\n",
889 __FUNCTION__, temp_word);
890 }
891
892 return IRQ_HANDLED;
893 }
894
895 static int hpc_get_max_lnk_speed (struct slot *slot, enum pci_bus_speed *value)
896 {
897 struct controller *ctrl = slot->ctrl;
898 enum pcie_link_speed lnk_speed;
899 u32 lnk_cap;
900 int retval = 0;
901
902 DBG_ENTER_ROUTINE
903
904 retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap);
905 if (retval) {
906 err("%s: Cannot read LNKCAP register\n", __FUNCTION__);
907 return retval;
908 }
909
910 switch (lnk_cap & 0x000F) {
911 case 1:
912 lnk_speed = PCIE_2PT5GB;
913 break;
914 default:
915 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
916 break;
917 }
918
919 *value = lnk_speed;
920 dbg("Max link speed = %d\n", lnk_speed);
921 DBG_LEAVE_ROUTINE
922 return retval;
923 }
924
925 static int hpc_get_max_lnk_width (struct slot *slot, enum pcie_link_width *value)
926 {
927 struct controller *ctrl = slot->ctrl;
928 enum pcie_link_width lnk_wdth;
929 u32 lnk_cap;
930 int retval = 0;
931
932 DBG_ENTER_ROUTINE
933
934 retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap);
935 if (retval) {
936 err("%s: Cannot read LNKCAP register\n", __FUNCTION__);
937 return retval;
938 }
939
940 switch ((lnk_cap & 0x03F0) >> 4){
941 case 0:
942 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
943 break;
944 case 1:
945 lnk_wdth = PCIE_LNK_X1;
946 break;
947 case 2:
948 lnk_wdth = PCIE_LNK_X2;
949 break;
950 case 4:
951 lnk_wdth = PCIE_LNK_X4;
952 break;
953 case 8:
954 lnk_wdth = PCIE_LNK_X8;
955 break;
956 case 12:
957 lnk_wdth = PCIE_LNK_X12;
958 break;
959 case 16:
960 lnk_wdth = PCIE_LNK_X16;
961 break;
962 case 32:
963 lnk_wdth = PCIE_LNK_X32;
964 break;
965 default:
966 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
967 break;
968 }
969
970 *value = lnk_wdth;
971 dbg("Max link width = %d\n", lnk_wdth);
972 DBG_LEAVE_ROUTINE
973 return retval;
974 }
975
976 static int hpc_get_cur_lnk_speed (struct slot *slot, enum pci_bus_speed *value)
977 {
978 struct controller *ctrl = slot->ctrl;
979 enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN;
980 int retval = 0;
981 u16 lnk_status;
982
983 DBG_ENTER_ROUTINE
984
985 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
986 if (retval) {
987 err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__);
988 return retval;
989 }
990
991 switch (lnk_status & 0x0F) {
992 case 1:
993 lnk_speed = PCIE_2PT5GB;
994 break;
995 default:
996 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
997 break;
998 }
999
1000 *value = lnk_speed;
1001 dbg("Current link speed = %d\n", lnk_speed);
1002 DBG_LEAVE_ROUTINE
1003 return retval;
1004 }
1005
1006 static int hpc_get_cur_lnk_width (struct slot *slot, enum pcie_link_width *value)
1007 {
1008 struct controller *ctrl = slot->ctrl;
1009 enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
1010 int retval = 0;
1011 u16 lnk_status;
1012
1013 DBG_ENTER_ROUTINE
1014
1015 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
1016 if (retval) {
1017 err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__);
1018 return retval;
1019 }
1020
1021 switch ((lnk_status & 0x03F0) >> 4){
1022 case 0:
1023 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
1024 break;
1025 case 1:
1026 lnk_wdth = PCIE_LNK_X1;
1027 break;
1028 case 2:
1029 lnk_wdth = PCIE_LNK_X2;
1030 break;
1031 case 4:
1032 lnk_wdth = PCIE_LNK_X4;
1033 break;
1034 case 8:
1035 lnk_wdth = PCIE_LNK_X8;
1036 break;
1037 case 12:
1038 lnk_wdth = PCIE_LNK_X12;
1039 break;
1040 case 16:
1041 lnk_wdth = PCIE_LNK_X16;
1042 break;
1043 case 32:
1044 lnk_wdth = PCIE_LNK_X32;
1045 break;
1046 default:
1047 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
1048 break;
1049 }
1050
1051 *value = lnk_wdth;
1052 dbg("Current link width = %d\n", lnk_wdth);
1053 DBG_LEAVE_ROUTINE
1054 return retval;
1055 }
1056
1057 static struct hpc_ops pciehp_hpc_ops = {
1058 .power_on_slot = hpc_power_on_slot,
1059 .power_off_slot = hpc_power_off_slot,
1060 .set_attention_status = hpc_set_attention_status,
1061 .get_power_status = hpc_get_power_status,
1062 .get_attention_status = hpc_get_attention_status,
1063 .get_latch_status = hpc_get_latch_status,
1064 .get_adapter_status = hpc_get_adapter_status,
1065 .get_emi_status = hpc_get_emi_status,
1066 .toggle_emi = hpc_toggle_emi,
1067
1068 .get_max_bus_speed = hpc_get_max_lnk_speed,
1069 .get_cur_bus_speed = hpc_get_cur_lnk_speed,
1070 .get_max_lnk_width = hpc_get_max_lnk_width,
1071 .get_cur_lnk_width = hpc_get_cur_lnk_width,
1072
1073 .query_power_fault = hpc_query_power_fault,
1074 .green_led_on = hpc_set_green_led_on,
1075 .green_led_off = hpc_set_green_led_off,
1076 .green_led_blink = hpc_set_green_led_blink,
1077
1078 .release_ctlr = hpc_release_ctlr,
1079 .check_lnk_status = hpc_check_lnk_status,
1080 };
1081
1082 #ifdef CONFIG_ACPI
1083 int pciehp_acpi_get_hp_hw_control_from_firmware(struct pci_dev *dev)
1084 {
1085 acpi_status status;
1086 acpi_handle chandle, handle = DEVICE_ACPI_HANDLE(&(dev->dev));
1087 struct pci_dev *pdev = dev;
1088 struct pci_bus *parent;
1089 struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL };
1090
1091 /*
1092 * Per PCI firmware specification, we should run the ACPI _OSC
1093 * method to get control of hotplug hardware before using it.
1094 * If an _OSC is missing, we look for an OSHP to do the same thing.
1095 * To handle different BIOS behavior, we look for _OSC and OSHP
1096 * within the scope of the hotplug controller and its parents, upto
1097 * the host bridge under which this controller exists.
1098 */
1099 while (!handle) {
1100 /*
1101 * This hotplug controller was not listed in the ACPI name
1102 * space at all. Try to get acpi handle of parent pci bus.
1103 */
1104 if (!pdev || !pdev->bus->parent)
1105 break;
1106 parent = pdev->bus->parent;
1107 dbg("Could not find %s in acpi namespace, trying parent\n",
1108 pci_name(pdev));
1109 if (!parent->self)
1110 /* Parent must be a host bridge */
1111 handle = acpi_get_pci_rootbridge_handle(
1112 pci_domain_nr(parent),
1113 parent->number);
1114 else
1115 handle = DEVICE_ACPI_HANDLE(
1116 &(parent->self->dev));
1117 pdev = parent->self;
1118 }
1119
1120 while (handle) {
1121 acpi_get_name(handle, ACPI_FULL_PATHNAME, &string);
1122 dbg("Trying to get hotplug control for %s \n",
1123 (char *)string.pointer);
1124 status = pci_osc_control_set(handle,
1125 OSC_PCI_EXPRESS_NATIVE_HP_CONTROL);
1126 if (status == AE_NOT_FOUND)
1127 status = acpi_run_oshp(handle);
1128 if (ACPI_SUCCESS(status)) {
1129 dbg("Gained control for hotplug HW for pci %s (%s)\n",
1130 pci_name(dev), (char *)string.pointer);
1131 kfree(string.pointer);
1132 return 0;
1133 }
1134 if (acpi_root_bridge(handle))
1135 break;
1136 chandle = handle;
1137 status = acpi_get_parent(chandle, &handle);
1138 if (ACPI_FAILURE(status))
1139 break;
1140 }
1141
1142 err("Cannot get control of hotplug hardware for pci %s\n",
1143 pci_name(dev));
1144
1145 kfree(string.pointer);
1146 return -1;
1147 }
1148 #endif
1149
1150
1151
1152 int pcie_init(struct controller * ctrl, struct pcie_device *dev)
1153 {
1154 int rc;
1155 static int first = 1;
1156 u16 temp_word;
1157 u16 cap_reg;
1158 u16 intr_enable = 0;
1159 u32 slot_cap;
1160 int cap_base;
1161 u16 slot_status, slot_ctrl;
1162 struct pci_dev *pdev;
1163
1164 DBG_ENTER_ROUTINE
1165
1166 pdev = dev->port;
1167 ctrl->pci_dev = pdev; /* save pci_dev in context */
1168
1169 dbg("%s: hotplug controller vendor id 0x%x device id 0x%x\n",
1170 __FUNCTION__, pdev->vendor, pdev->device);
1171
1172 if ((cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP)) == 0) {
1173 dbg("%s: Can't find PCI_CAP_ID_EXP (0x10)\n", __FUNCTION__);
1174 goto abort_free_ctlr;
1175 }
1176
1177 ctrl->cap_base = cap_base;
1178
1179 dbg("%s: pcie_cap_base %x\n", __FUNCTION__, cap_base);
1180
1181 rc = pciehp_readw(ctrl, CAPREG, &cap_reg);
1182 if (rc) {
1183 err("%s: Cannot read CAPREG register\n", __FUNCTION__);
1184 goto abort_free_ctlr;
1185 }
1186 dbg("%s: CAPREG offset %x cap_reg %x\n",
1187 __FUNCTION__, ctrl->cap_base + CAPREG, cap_reg);
1188
1189 if (((cap_reg & SLOT_IMPL) == 0) || (((cap_reg & DEV_PORT_TYPE) != 0x0040)
1190 && ((cap_reg & DEV_PORT_TYPE) != 0x0060))) {
1191 dbg("%s : This is not a root port or the port is not connected to a slot\n", __FUNCTION__);
1192 goto abort_free_ctlr;
1193 }
1194
1195 rc = pciehp_readl(ctrl, SLOTCAP, &slot_cap);
1196 if (rc) {
1197 err("%s: Cannot read SLOTCAP register\n", __FUNCTION__);
1198 goto abort_free_ctlr;
1199 }
1200 dbg("%s: SLOTCAP offset %x slot_cap %x\n",
1201 __FUNCTION__, ctrl->cap_base + SLOTCAP, slot_cap);
1202
1203 if (!(slot_cap & HP_CAP)) {
1204 dbg("%s : This slot is not hot-plug capable\n", __FUNCTION__);
1205 goto abort_free_ctlr;
1206 }
1207 /* For debugging purpose */
1208 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
1209 if (rc) {
1210 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
1211 goto abort_free_ctlr;
1212 }
1213 dbg("%s: SLOTSTATUS offset %x slot_status %x\n",
1214 __FUNCTION__, ctrl->cap_base + SLOTSTATUS, slot_status);
1215
1216 rc = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
1217 if (rc) {
1218 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
1219 goto abort_free_ctlr;
1220 }
1221 dbg("%s: SLOTCTRL offset %x slot_ctrl %x\n",
1222 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
1223
1224 if (first) {
1225 spin_lock_init(&hpc_event_lock);
1226 first = 0;
1227 }
1228
1229 for ( rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++)
1230 if (pci_resource_len(pdev, rc) > 0)
1231 dbg("pci resource[%d] start=0x%llx(len=0x%llx)\n", rc,
1232 (unsigned long long)pci_resource_start(pdev, rc),
1233 (unsigned long long)pci_resource_len(pdev, rc));
1234
1235 info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device,
1236 pdev->subsystem_vendor, pdev->subsystem_device);
1237
1238 mutex_init(&ctrl->crit_sect);
1239 mutex_init(&ctrl->ctrl_lock);
1240
1241 /* setup wait queue */
1242 init_waitqueue_head(&ctrl->queue);
1243
1244 /* return PCI Controller Info */
1245 ctrl->slot_device_offset = 0;
1246 ctrl->num_slots = 1;
1247 ctrl->first_slot = slot_cap >> 19;
1248 ctrl->ctrlcap = slot_cap & 0x0000007f;
1249
1250 /* Mask Hot-plug Interrupt Enable */
1251 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
1252 if (rc) {
1253 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
1254 goto abort_free_ctlr;
1255 }
1256
1257 dbg("%s: SLOTCTRL %x value read %x\n",
1258 __FUNCTION__, ctrl->cap_base + SLOTCTRL, temp_word);
1259 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00;
1260
1261 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
1262 if (rc) {
1263 err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__);
1264 goto abort_free_ctlr;
1265 }
1266
1267 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
1268 if (rc) {
1269 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
1270 goto abort_free_ctlr;
1271 }
1272
1273 temp_word = 0x1F; /* Clear all events */
1274 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
1275 if (rc) {
1276 err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__);
1277 goto abort_free_ctlr;
1278 }
1279
1280 if (pciehp_poll_mode) {
1281 /* Install interrupt polling timer. Start with 10 sec delay */
1282 init_timer(&ctrl->poll_timer);
1283 start_int_poll_timer(ctrl, 10);
1284 } else {
1285 /* Installs the interrupt handler */
1286 rc = request_irq(ctrl->pci_dev->irq, pcie_isr, IRQF_SHARED,
1287 MY_NAME, (void *)ctrl);
1288 dbg("%s: request_irq %d for hpc%d (returns %d)\n",
1289 __FUNCTION__, ctrl->pci_dev->irq, ctlr_seq_num, rc);
1290 if (rc) {
1291 err("Can't get irq %d for the hotplug controller\n",
1292 ctrl->pci_dev->irq);
1293 goto abort_free_ctlr;
1294 }
1295 }
1296 dbg("pciehp ctrl b:d:f:irq=0x%x:%x:%x:%x\n", pdev->bus->number,
1297 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), dev->irq);
1298
1299 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
1300 if (rc) {
1301 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
1302 goto abort_free_irq;
1303 }
1304
1305 intr_enable = intr_enable | PRSN_DETECT_ENABLE;
1306
1307 if (ATTN_BUTTN(slot_cap))
1308 intr_enable = intr_enable | ATTN_BUTTN_ENABLE;
1309
1310 if (POWER_CTRL(slot_cap))
1311 intr_enable = intr_enable | PWR_FAULT_DETECT_ENABLE;
1312
1313 if (MRL_SENS(slot_cap))
1314 intr_enable = intr_enable | MRL_DETECT_ENABLE;
1315
1316 temp_word = (temp_word & ~intr_enable) | intr_enable;
1317
1318 if (pciehp_poll_mode) {
1319 temp_word = (temp_word & ~HP_INTR_ENABLE) | 0x0;
1320 } else {
1321 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
1322 }
1323
1324 /* Unmask Hot-plug Interrupt Enable for the interrupt notification mechanism case */
1325 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
1326 if (rc) {
1327 err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__);
1328 goto abort_free_irq;
1329 }
1330 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
1331 if (rc) {
1332 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
1333 goto abort_disable_intr;
1334 }
1335
1336 temp_word = 0x1F; /* Clear all events */
1337 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
1338 if (rc) {
1339 err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__);
1340 goto abort_disable_intr;
1341 }
1342
1343 if (pciehp_force) {
1344 dbg("Bypassing BIOS check for pciehp use on %s\n",
1345 pci_name(ctrl->pci_dev));
1346 } else {
1347 rc = pciehp_get_hp_hw_control_from_firmware(ctrl->pci_dev);
1348 if (rc)
1349 goto abort_disable_intr;
1350 }
1351
1352 ctlr_seq_num++;
1353 ctrl->hpc_ops = &pciehp_hpc_ops;
1354
1355 DBG_LEAVE_ROUTINE
1356 return 0;
1357
1358 /* We end up here for the many possible ways to fail this API. */
1359 abort_disable_intr:
1360 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
1361 if (!rc) {
1362 temp_word &= ~(intr_enable | HP_INTR_ENABLE);
1363 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
1364 }
1365 if (rc)
1366 err("%s : disabling interrupts failed\n", __FUNCTION__);
1367
1368 abort_free_irq:
1369 if (pciehp_poll_mode)
1370 del_timer_sync(&ctrl->poll_timer);
1371 else
1372 free_irq(ctrl->pci_dev->irq, ctrl);
1373
1374 abort_free_ctlr:
1375 DBG_LEAVE_ROUTINE
1376 return -1;
1377 }
Linux with added FPC-III support