| blob | fa78f0163270a3e8d8a8c59a358c13952ddda768 |
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright 2019 NXP
4 */
6 #include <dt-bindings/clock/imx8mn-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
12 #include "imx8mn-pinfunc.h"
14 / {
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
19 aliases {
20 ethernet0 = &fec1;
21 gpio0 = &gpio1;
22 gpio1 = &gpio2;
23 gpio2 = &gpio3;
24 gpio3 = &gpio4;
25 gpio4 = &gpio5;
26 i2c0 = &i2c1;
27 i2c1 = &i2c2;
28 i2c2 = &i2c3;
29 i2c3 = &i2c4;
30 mmc0 = &usdhc1;
31 mmc1 = &usdhc2;
32 mmc2 = &usdhc3;
33 serial0 = &uart1;
34 serial1 = &uart2;
35 serial2 = &uart3;
36 serial3 = &uart4;
37 spi0 = &ecspi1;
38 spi1 = &ecspi2;
39 spi2 = &ecspi3;
40 };
42 cpus {
43 #address-cells = <1>;
44 #size-cells = <0>;
46 idle-states {
47 entry-method = "psci";
49 cpu_pd_wait: cpu-pd-wait {
50 compatible = "arm,idle-state";
51 arm,psci-suspend-param = <0x0010033>;
52 local-timer-stop;
53 entry-latency-us = <1000>;
54 exit-latency-us = <700>;
55 min-residency-us = <2700>;
56 };
57 };
59 A53_0: cpu@0 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a53";
62 reg = <0x0>;
63 clock-latency = <61036>;
64 clocks = <&clk IMX8MN_CLK_ARM>;
65 enable-method = "psci";
66 next-level-cache = <&A53_L2>;
67 operating-points-v2 = <&a53_opp_table>;
68 nvmem-cells = <&cpu_speed_grade>;
69 nvmem-cell-names = "speed_grade";
70 cpu-idle-states = <&cpu_pd_wait>;
71 #cooling-cells = <2>;
72 };
74 A53_1: cpu@1 {
75 device_type = "cpu";
76 compatible = "arm,cortex-a53";
77 reg = <0x1>;
78 clock-latency = <61036>;
79 clocks = <&clk IMX8MN_CLK_ARM>;
80 enable-method = "psci";
81 next-level-cache = <&A53_L2>;
82 operating-points-v2 = <&a53_opp_table>;
83 cpu-idle-states = <&cpu_pd_wait>;
84 #cooling-cells = <2>;
85 };
87 A53_2: cpu@2 {
88 device_type = "cpu";
89 compatible = "arm,cortex-a53";
90 reg = <0x2>;
91 clock-latency = <61036>;
92 clocks = <&clk IMX8MN_CLK_ARM>;
93 enable-method = "psci";
94 next-level-cache = <&A53_L2>;
95 operating-points-v2 = <&a53_opp_table>;
96 cpu-idle-states = <&cpu_pd_wait>;
97 #cooling-cells = <2>;
98 };
100 A53_3: cpu@3 {
101 device_type = "cpu";
102 compatible = "arm,cortex-a53";
103 reg = <0x3>;
104 clock-latency = <61036>;
105 clocks = <&clk IMX8MN_CLK_ARM>;
106 enable-method = "psci";
107 next-level-cache = <&A53_L2>;
108 operating-points-v2 = <&a53_opp_table>;
109 cpu-idle-states = <&cpu_pd_wait>;
110 #cooling-cells = <2>;
111 };
113 A53_L2: l2-cache0 {
114 compatible = "cache";
115 };
116 };
118 a53_opp_table: opp-table {
119 compatible = "operating-points-v2";
120 opp-shared;
122 opp-1200000000 {
123 opp-hz = /bits/ 64 <1200000000>;
124 opp-microvolt = <950000>;
125 opp-supported-hw = <0xb00>, <0x7>;
126 clock-latency-ns = <150000>;
127 opp-suspend;
128 };
130 opp-1400000000 {
131 opp-hz = /bits/ 64 <1400000000>;
132 opp-microvolt = <950000>;
133 opp-supported-hw = <0x300>, <0x7>;
134 clock-latency-ns = <150000>;
135 opp-suspend;
136 };
138 opp-1500000000 {
139 opp-hz = /bits/ 64 <1500000000>;
140 opp-microvolt = <1000000>;
141 opp-supported-hw = <0x100>, <0x3>;
142 clock-latency-ns = <150000>;
143 opp-suspend;
144 };
145 };
147 osc_32k: clock-osc-32k {
148 compatible = "fixed-clock";
149 #clock-cells = <0>;
150 clock-frequency = <32768>;
151 clock-output-names = "osc_32k";
152 };
154 osc_24m: clock-osc-24m {
155 compatible = "fixed-clock";
156 #clock-cells = <0>;
157 clock-frequency = <24000000>;
158 clock-output-names = "osc_24m";
159 };
161 clk_ext1: clock-ext1 {
162 compatible = "fixed-clock";
163 #clock-cells = <0>;
164 clock-frequency = <133000000>;
165 clock-output-names = "clk_ext1";
166 };
168 clk_ext2: clock-ext2 {
169 compatible = "fixed-clock";
170 #clock-cells = <0>;
171 clock-frequency = <133000000>;
172 clock-output-names = "clk_ext2";
173 };
175 clk_ext3: clock-ext3 {
176 compatible = "fixed-clock";
177 #clock-cells = <0>;
178 clock-frequency = <133000000>;
179 clock-output-names = "clk_ext3";
180 };
182 clk_ext4: clock-ext4 {
183 compatible = "fixed-clock";
184 #clock-cells = <0>;
185 clock-frequency= <133000000>;
186 clock-output-names = "clk_ext4";
187 };
189 psci {
190 compatible = "arm,psci-1.0";
191 method = "smc";
192 };
194 thermal-zones {
195 cpu-thermal {
196 polling-delay-passive = <250>;
197 polling-delay = <2000>;
198 thermal-sensors = <&tmu>;
199 trips {
200 cpu_alert0: trip0 {
201 temperature = <85000>;
202 hysteresis = <2000>;
203 type = "passive";
204 };
206 cpu_crit0: trip1 {
207 temperature = <95000>;
208 hysteresis = <2000>;
209 type = "critical";
210 };
211 };
213 cooling-maps {
214 map0 {
215 trip = <&cpu_alert0>;
216 cooling-device =
217 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
218 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
219 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
220 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
221 };
222 };
223 };
224 };
226 timer {
227 compatible = "arm,armv8-timer";
228 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
229 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
230 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
231 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
232 clock-frequency = <8000000>;
233 arm,no-tick-in-suspend;
234 };
236 soc@0 {
237 compatible = "simple-bus";
238 #address-cells = <1>;
239 #size-cells = <1>;
240 ranges = <0x0 0x0 0x0 0x3e000000>;
242 aips1: bus@30000000 {
243 compatible = "fsl,aips-bus", "simple-bus";
244 reg = <0x301f0000 0x10000>;
245 #address-cells = <1>;
246 #size-cells = <1>;
247 ranges;
249 gpio1: gpio@30200000 {
250 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
251 reg = <0x30200000 0x10000>;
252 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>;
255 gpio-controller;
256 #gpio-cells = <2>;
257 interrupt-controller;
258 #interrupt-cells = <2>;
259 gpio-ranges = <&iomuxc 0 10 30>;
260 };
262 gpio2: gpio@30210000 {
263 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
264 reg = <0x30210000 0x10000>;
265 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
266 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
267 clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>;
268 gpio-controller;
269 #gpio-cells = <2>;
270 interrupt-controller;
271 #interrupt-cells = <2>;
272 gpio-ranges = <&iomuxc 0 40 21>;
273 };
275 gpio3: gpio@30220000 {
276 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
277 reg = <0x30220000 0x10000>;
278 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
279 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
280 clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>;
281 gpio-controller;
282 #gpio-cells = <2>;
283 interrupt-controller;
284 #interrupt-cells = <2>;
285 gpio-ranges = <&iomuxc 0 61 26>;
286 };
288 gpio4: gpio@30230000 {
289 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
290 reg = <0x30230000 0x10000>;
291 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
293 clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>;
294 gpio-controller;
295 #gpio-cells = <2>;
296 interrupt-controller;
297 #interrupt-cells = <2>;
298 gpio-ranges = <&iomuxc 21 108 11>;
299 };
301 gpio5: gpio@30240000 {
302 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
303 reg = <0x30240000 0x10000>;
304 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>;
307 gpio-controller;
308 #gpio-cells = <2>;
309 interrupt-controller;
310 #interrupt-cells = <2>;
311 gpio-ranges = <&iomuxc 0 119 30>;
312 };
314 tmu: tmu@30260000 {
315 compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu";
316 reg = <0x30260000 0x10000>;
317 clocks = <&clk IMX8MN_CLK_TMU_ROOT>;
318 #thermal-sensor-cells = <0>;
319 };
321 wdog1: watchdog@30280000 {
322 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
323 reg = <0x30280000 0x10000>;
324 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>;
326 status = "disabled";
327 };
329 wdog2: watchdog@30290000 {
330 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
331 reg = <0x30290000 0x10000>;
332 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>;
334 status = "disabled";
335 };
337 wdog3: watchdog@302a0000 {
338 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
339 reg = <0x302a0000 0x10000>;
340 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
341 clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>;
342 status = "disabled";
343 };
345 sdma3: dma-controller@302b0000 {
346 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
347 reg = <0x302b0000 0x10000>;
348 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
349 clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>,
350 <&clk IMX8MN_CLK_SDMA3_ROOT>;
351 clock-names = "ipg", "ahb";
352 #dma-cells = <3>;
353 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
354 };
356 sdma2: dma-controller@302c0000 {
357 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
358 reg = <0x302c0000 0x10000>;
359 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
360 clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>,
361 <&clk IMX8MN_CLK_SDMA2_ROOT>;
362 clock-names = "ipg", "ahb";
363 #dma-cells = <3>;
364 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
365 };
367 iomuxc: pinctrl@30330000 {
368 compatible = "fsl,imx8mn-iomuxc";
369 reg = <0x30330000 0x10000>;
370 };
372 gpr: iomuxc-gpr@30340000 {
373 compatible = "fsl,imx8mn-iomuxc-gpr", "syscon";
374 reg = <0x30340000 0x10000>;
375 };
377 ocotp: ocotp-ctrl@30350000 {
378 compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon";
379 reg = <0x30350000 0x10000>;
380 clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>;
381 #address-cells = <1>;
382 #size-cells = <1>;
384 cpu_speed_grade: speed-grade@10 {
385 reg = <0x10 4>;
386 };
387 };
389 anatop: anatop@30360000 {
390 compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop",
391 "syscon";
392 reg = <0x30360000 0x10000>;
393 };
395 snvs: snvs@30370000 {
396 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
397 reg = <0x30370000 0x10000>;
399 snvs_rtc: snvs-rtc-lp {
400 compatible = "fsl,sec-v4.0-mon-rtc-lp";
401 regmap = <&snvs>;
402 offset = <0x34>;
403 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
405 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>;
406 clock-names = "snvs-rtc";
407 };
409 snvs_pwrkey: snvs-powerkey {
410 compatible = "fsl,sec-v4.0-pwrkey";
411 regmap = <&snvs>;
412 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
413 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>;
414 clock-names = "snvs-pwrkey";
415 linux,keycode = <KEY_POWER>;
416 wakeup-source;
417 status = "disabled";
418 };
419 };
421 clk: clock-controller@30380000 {
422 compatible = "fsl,imx8mn-ccm";
423 reg = <0x30380000 0x10000>;
424 #clock-cells = <1>;
425 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
426 <&clk_ext3>, <&clk_ext4>;
427 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
428 "clk_ext3", "clk_ext4";
429 assigned-clocks = <&clk IMX8MN_CLK_NOC>,
430 <&clk IMX8MN_CLK_AUDIO_AHB>,
431 <&clk IMX8MN_CLK_IPG_AUDIO_ROOT>,
432 <&clk IMX8MN_SYS_PLL3>;
433 assigned-clock-parents = <&clk IMX8MN_SYS_PLL3_OUT>,
434 <&clk IMX8MN_SYS_PLL1_800M>;
435 assigned-clock-rates = <0>,
436 <400000000>,
437 <400000000>,
438 <600000000>;
439 };
441 src: reset-controller@30390000 {
442 compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon";
443 reg = <0x30390000 0x10000>;
444 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
445 #reset-cells = <1>;
446 };
447 };
449 aips2: bus@30400000 {
450 compatible = "fsl,aips-bus", "simple-bus";
451 reg = <0x305f0000 0x10000>;
452 #address-cells = <1>;
453 #size-cells = <1>;
454 ranges;
456 pwm1: pwm@30660000 {
457 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
458 reg = <0x30660000 0x10000>;
459 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&clk IMX8MN_CLK_PWM1_ROOT>,
461 <&clk IMX8MN_CLK_PWM1_ROOT>;
462 clock-names = "ipg", "per";
463 #pwm-cells = <2>;
464 status = "disabled";
465 };
467 pwm2: pwm@30670000 {
468 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
469 reg = <0x30670000 0x10000>;
470 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
471 clocks = <&clk IMX8MN_CLK_PWM2_ROOT>,
472 <&clk IMX8MN_CLK_PWM2_ROOT>;
473 clock-names = "ipg", "per";
474 #pwm-cells = <2>;
475 status = "disabled";
476 };
478 pwm3: pwm@30680000 {
479 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
480 reg = <0x30680000 0x10000>;
481 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
482 clocks = <&clk IMX8MN_CLK_PWM3_ROOT>,
483 <&clk IMX8MN_CLK_PWM3_ROOT>;
484 clock-names = "ipg", "per";
485 #pwm-cells = <2>;
486 status = "disabled";
487 };
489 pwm4: pwm@30690000 {
490 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
491 reg = <0x30690000 0x10000>;
492 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
493 clocks = <&clk IMX8MN_CLK_PWM4_ROOT>,
494 <&clk IMX8MN_CLK_PWM4_ROOT>;
495 clock-names = "ipg", "per";
496 #pwm-cells = <2>;
497 status = "disabled";
498 };
500 system_counter: timer@306a0000 {
501 compatible = "nxp,sysctr-timer";
502 reg = <0x306a0000 0x20000>;
503 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
504 clocks = <&osc_24m>;
505 clock-names = "per";
506 };
507 };
509 aips3: bus@30800000 {
510 compatible = "fsl,aips-bus", "simple-bus";
511 reg = <0x309f0000 0x10000>;
512 #address-cells = <1>;
513 #size-cells = <1>;
514 ranges;
516 ecspi1: spi@30820000 {
517 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
518 #address-cells = <1>;
519 #size-cells = <0>;
520 reg = <0x30820000 0x10000>;
521 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
522 clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>,
523 <&clk IMX8MN_CLK_ECSPI1_ROOT>;
524 clock-names = "ipg", "per";
525 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
526 dma-names = "rx", "tx";
527 status = "disabled";
528 };
530 ecspi2: spi@30830000 {
531 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
532 #address-cells = <1>;
533 #size-cells = <0>;
534 reg = <0x30830000 0x10000>;
535 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
536 clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>,
537 <&clk IMX8MN_CLK_ECSPI2_ROOT>;
538 clock-names = "ipg", "per";
539 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
540 dma-names = "rx", "tx";
541 status = "disabled";
542 };
544 ecspi3: spi@30840000 {
545 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
546 #address-cells = <1>;
547 #size-cells = <0>;
548 reg = <0x30840000 0x10000>;
549 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
550 clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>,
551 <&clk IMX8MN_CLK_ECSPI3_ROOT>;
552 clock-names = "ipg", "per";
553 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
554 dma-names = "rx", "tx";
555 status = "disabled";
556 };
558 uart1: serial@30860000 {
559 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
560 reg = <0x30860000 0x10000>;
561 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
562 clocks = <&clk IMX8MN_CLK_UART1_ROOT>,
563 <&clk IMX8MN_CLK_UART1_ROOT>;
564 clock-names = "ipg", "per";
565 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
566 dma-names = "rx", "tx";
567 status = "disabled";
568 };
570 uart3: serial@30880000 {
571 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
572 reg = <0x30880000 0x10000>;
573 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
574 clocks = <&clk IMX8MN_CLK_UART3_ROOT>,
575 <&clk IMX8MN_CLK_UART3_ROOT>;
576 clock-names = "ipg", "per";
577 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
578 dma-names = "rx", "tx";
579 status = "disabled";
580 };
582 uart2: serial@30890000 {
583 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
584 reg = <0x30890000 0x10000>;
585 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
586 clocks = <&clk IMX8MN_CLK_UART2_ROOT>,
587 <&clk IMX8MN_CLK_UART2_ROOT>;
588 clock-names = "ipg", "per";
589 status = "disabled";
590 };
592 crypto: crypto@30900000 {
593 compatible = "fsl,sec-v4.0";
594 #address-cells = <1>;
595 #size-cells = <1>;
596 reg = <0x30900000 0x40000>;
597 ranges = <0 0x30900000 0x40000>;
598 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
599 clocks = <&clk IMX8MN_CLK_AHB>,
600 <&clk IMX8MN_CLK_IPG_ROOT>;
601 clock-names = "aclk", "ipg";
603 sec_jr0: jr@1000 {
604 compatible = "fsl,sec-v4.0-job-ring";
605 reg = <0x1000 0x1000>;
606 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
607 };
609 sec_jr1: jr@2000 {
610 compatible = "fsl,sec-v4.0-job-ring";
611 reg = <0x2000 0x1000>;
612 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
613 };
615 sec_jr2: jr@3000 {
616 compatible = "fsl,sec-v4.0-job-ring";
617 reg = <0x3000 0x1000>;
618 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
619 };
620 };
622 i2c1: i2c@30a20000 {
623 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
624 #address-cells = <1>;
625 #size-cells = <0>;
626 reg = <0x30a20000 0x10000>;
627 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
628 clocks = <&clk IMX8MN_CLK_I2C1_ROOT>;
629 status = "disabled";
630 };
632 i2c2: i2c@30a30000 {
633 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
634 #address-cells = <1>;
635 #size-cells = <0>;
636 reg = <0x30a30000 0x10000>;
637 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
638 clocks = <&clk IMX8MN_CLK_I2C2_ROOT>;
639 status = "disabled";
640 };
642 i2c3: i2c@30a40000 {
643 #address-cells = <1>;
644 #size-cells = <0>;
645 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
646 reg = <0x30a40000 0x10000>;
647 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
648 clocks = <&clk IMX8MN_CLK_I2C3_ROOT>;
649 status = "disabled";
650 };
652 i2c4: i2c@30a50000 {
653 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
654 #address-cells = <1>;
655 #size-cells = <0>;
656 reg = <0x30a50000 0x10000>;
657 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
658 clocks = <&clk IMX8MN_CLK_I2C4_ROOT>;
659 status = "disabled";
660 };
662 uart4: serial@30a60000 {
663 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
664 reg = <0x30a60000 0x10000>;
665 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
666 clocks = <&clk IMX8MN_CLK_UART4_ROOT>,
667 <&clk IMX8MN_CLK_UART4_ROOT>;
668 clock-names = "ipg", "per";
669 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
670 dma-names = "rx", "tx";
671 status = "disabled";
672 };
674 usdhc1: mmc@30b40000 {
675 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
676 reg = <0x30b40000 0x10000>;
677 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
678 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
679 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
680 <&clk IMX8MN_CLK_USDHC1_ROOT>;
681 clock-names = "ipg", "ahb", "per";
682 fsl,tuning-start-tap = <20>;
683 fsl,tuning-step= <2>;
684 bus-width = <4>;
685 status = "disabled";
686 };
688 usdhc2: mmc@30b50000 {
689 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
690 reg = <0x30b50000 0x10000>;
691 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
692 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
693 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
694 <&clk IMX8MN_CLK_USDHC2_ROOT>;
695 clock-names = "ipg", "ahb", "per";
696 fsl,tuning-start-tap = <20>;
697 fsl,tuning-step= <2>;
698 bus-width = <4>;
699 status = "disabled";
700 };
702 usdhc3: mmc@30b60000 {
703 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
704 reg = <0x30b60000 0x10000>;
705 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
706 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
707 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
708 <&clk IMX8MN_CLK_USDHC3_ROOT>;
709 clock-names = "ipg", "ahb", "per";
710 fsl,tuning-start-tap = <20>;
711 fsl,tuning-step= <2>;
712 bus-width = <4>;
713 status = "disabled";
714 };
716 sdma1: dma-controller@30bd0000 {
717 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
718 reg = <0x30bd0000 0x10000>;
719 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
720 clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>,
721 <&clk IMX8MN_CLK_SDMA1_ROOT>;
722 clock-names = "ipg", "ahb";
723 #dma-cells = <3>;
724 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
725 };
727 fec1: ethernet@30be0000 {
728 compatible = "fsl,imx8mn-fec", "fsl,imx6sx-fec";
729 reg = <0x30be0000 0x10000>;
730 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
731 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
732 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
733 clocks = <&clk IMX8MN_CLK_ENET1_ROOT>,
734 <&clk IMX8MN_CLK_ENET1_ROOT>,
735 <&clk IMX8MN_CLK_ENET_TIMER>,
736 <&clk IMX8MN_CLK_ENET_REF>,
737 <&clk IMX8MN_CLK_ENET_PHY_REF>;
738 clock-names = "ipg", "ahb", "ptp",
739 "enet_clk_ref", "enet_out";
740 assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>,
741 <&clk IMX8MN_CLK_ENET_TIMER>,
742 <&clk IMX8MN_CLK_ENET_REF>,
743 <&clk IMX8MN_CLK_ENET_TIMER>;
744 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
745 <&clk IMX8MN_SYS_PLL2_100M>,
746 <&clk IMX8MN_SYS_PLL2_125M>;
747 assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
748 fsl,num-tx-queues = <3>;
749 fsl,num-rx-queues = <3>;
750 status = "disabled";
751 };
753 };
755 aips4: bus@32c00000 {
756 compatible = "fsl,aips-bus", "simple-bus";
757 reg = <0x32df0000 0x10000>;
758 #address-cells = <1>;
759 #size-cells = <1>;
760 ranges;
762 usbotg1: usb@32e40000 {
763 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
764 reg = <0x32e40000 0x200>;
765 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
766 clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
767 clock-names = "usb1_ctrl_root_clk";
768 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>;
769 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
770 fsl,usbphy = <&usbphynop1>;
771 fsl,usbmisc = <&usbmisc1 0>;
772 status = "disabled";
773 };
775 usbmisc1: usbmisc@32e40200 {
776 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
777 #index-cells = <1>;
778 reg = <0x32e40200 0x200>;
779 };
781 usbotg2: usb@32e50000 {
782 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
783 reg = <0x32e50000 0x200>;
784 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
785 clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
786 clock-names = "usb1_ctrl_root_clk";
787 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>,
788 <&clk IMX8MN_CLK_USB_CORE_REF>;
789 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>,
790 <&clk IMX8MN_SYS_PLL1_100M>;
791 fsl,usbphy = <&usbphynop2>;
792 fsl,usbmisc = <&usbmisc2 0>;
793 status = "disabled";
794 };
796 usbmisc2: usbmisc@32e50200 {
797 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
798 #index-cells = <1>;
799 reg = <0x32e50200 0x200>;
800 };
802 };
804 dma_apbh: dma-controller@33000000 {
805 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
806 reg = <0x33000000 0x2000>;
807 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
808 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
809 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
810 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
811 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
812 #dma-cells = <1>;
813 dma-channels = <4>;
814 clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
815 };
817 gpmi: nand-controller@33002000 {
818 compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand";
819 #address-cells = <1>;
820 #size-cells = <1>;
821 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
822 reg-names = "gpmi-nand", "bch";
823 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
824 interrupt-names = "bch";
825 clocks = <&clk IMX8MN_CLK_NAND_ROOT>,
826 <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
827 clock-names = "gpmi_io", "gpmi_bch_apb";
828 dmas = <&dma_apbh 0>;
829 dma-names = "rx-tx";
830 status = "disabled";
831 };
833 gic: interrupt-controller@38800000 {
834 compatible = "arm,gic-v3";
835 reg = <0x38800000 0x10000>,
836 <0x38880000 0xc0000>;
837 #interrupt-cells = <3>;
838 interrupt-controller;
839 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
840 };
842 ddrc: memory-controller@3d400000 {
843 compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc";
844 reg = <0x3d400000 0x400000>;
845 clock-names = "core", "pll", "alt", "apb";
846 clocks = <&clk IMX8MN_CLK_DRAM_CORE>,
847 <&clk IMX8MN_DRAM_PLL>,
848 <&clk IMX8MN_CLK_DRAM_ALT>,
849 <&clk IMX8MN_CLK_DRAM_APB>;
850 };
852 ddr-pmu@3d800000 {
853 compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu";
854 reg = <0x3d800000 0x400000>;
855 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
856 };
857 };
859 usbphynop1: usbphynop1 {
860 compatible = "usb-nop-xceiv";
861 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
862 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
863 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
864 clock-names = "main_clk";
865 };
867 usbphynop2: usbphynop2 {
868 compatible = "usb-nop-xceiv";
869 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
870 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
871 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
872 clock-names = "main_clk";
873 };
874 };