| blob | 79023433a740b7ca06a67b90675fbd8f6c4bf987 |
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Device Tree Source for the r8a774a1 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r8a774a1-cpg-mssr.h>
11 #include <dt-bindings/power/r8a774a1-sysc.h>
13 / {
14 compatible = "renesas,r8a774a1";
15 #address-cells = <2>;
16 #size-cells = <2>;
18 aliases {
19 i2c0 = &i2c0;
20 i2c1 = &i2c1;
21 i2c2 = &i2c2;
22 i2c3 = &i2c3;
23 i2c4 = &i2c4;
24 i2c5 = &i2c5;
25 i2c6 = &i2c6;
26 i2c7 = &i2c_dvfs;
27 };
29 /*
30 * The external audio clocks are configured as 0 Hz fixed frequency
31 * clocks by default.
32 * Boards that provide audio clocks should override them.
33 */
34 audio_clk_a: audio_clk_a {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <0>;
38 };
40 audio_clk_b: audio_clk_b {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <0>;
44 };
46 audio_clk_c: audio_clk_c {
47 compatible = "fixed-clock";
48 #clock-cells = <0>;
49 clock-frequency = <0>;
50 };
52 /* External CAN clock - to be overridden by boards that provide it */
53 can_clk: can {
54 compatible = "fixed-clock";
55 #clock-cells = <0>;
56 clock-frequency = <0>;
57 };
59 cluster0_opp: opp_table0 {
60 compatible = "operating-points-v2";
61 opp-shared;
63 opp-500000000 {
64 opp-hz = /bits/ 64 <500000000>;
65 opp-microvolt = <820000>;
66 clock-latency-ns = <300000>;
67 };
68 opp-1000000000 {
69 opp-hz = /bits/ 64 <1000000000>;
70 opp-microvolt = <820000>;
71 clock-latency-ns = <300000>;
72 };
73 opp-1500000000 {
74 opp-hz = /bits/ 64 <1500000000>;
75 opp-microvolt = <820000>;
76 clock-latency-ns = <300000>;
77 };
78 };
80 cluster1_opp: opp_table1 {
81 compatible = "operating-points-v2";
82 opp-shared;
84 opp-800000000 {
85 opp-hz = /bits/ 64 <800000000>;
86 opp-microvolt = <820000>;
87 clock-latency-ns = <300000>;
88 };
89 opp-1000000000 {
90 opp-hz = /bits/ 64 <1000000000>;
91 opp-microvolt = <820000>;
92 clock-latency-ns = <300000>;
93 };
94 opp-1200000000 {
95 opp-hz = /bits/ 64 <1200000000>;
96 opp-microvolt = <820000>;
97 clock-latency-ns = <300000>;
98 };
99 };
101 cpus {
102 #address-cells = <1>;
103 #size-cells = <0>;
105 cpu-map {
106 cluster0 {
107 core0 {
108 cpu = <&a57_0>;
109 };
110 core1 {
111 cpu = <&a57_1>;
112 };
113 };
115 cluster1 {
116 core0 {
117 cpu = <&a53_0>;
118 };
119 core1 {
120 cpu = <&a53_1>;
121 };
122 core2 {
123 cpu = <&a53_2>;
124 };
125 core3 {
126 cpu = <&a53_3>;
127 };
128 };
129 };
131 a57_0: cpu@0 {
132 compatible = "arm,cortex-a57";
133 reg = <0x0>;
134 device_type = "cpu";
135 power-domains = <&sysc R8A774A1_PD_CA57_CPU0>;
136 next-level-cache = <&L2_CA57>;
137 enable-method = "psci";
138 dynamic-power-coefficient = <854>;
139 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
140 operating-points-v2 = <&cluster0_opp>;
141 capacity-dmips-mhz = <1024>;
142 #cooling-cells = <2>;
143 };
145 a57_1: cpu@1 {
146 compatible = "arm,cortex-a57";
147 reg = <0x1>;
148 device_type = "cpu";
149 power-domains = <&sysc R8A774A1_PD_CA57_CPU1>;
150 next-level-cache = <&L2_CA57>;
151 enable-method = "psci";
152 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
153 operating-points-v2 = <&cluster0_opp>;
154 capacity-dmips-mhz = <1024>;
155 #cooling-cells = <2>;
156 };
158 a53_0: cpu@100 {
159 compatible = "arm,cortex-a53";
160 reg = <0x100>;
161 device_type = "cpu";
162 power-domains = <&sysc R8A774A1_PD_CA53_CPU0>;
163 next-level-cache = <&L2_CA53>;
164 enable-method = "psci";
165 #cooling-cells = <2>;
166 dynamic-power-coefficient = <277>;
167 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
168 operating-points-v2 = <&cluster1_opp>;
169 capacity-dmips-mhz = <560>;
170 };
172 a53_1: cpu@101 {
173 compatible = "arm,cortex-a53";
174 reg = <0x101>;
175 device_type = "cpu";
176 power-domains = <&sysc R8A774A1_PD_CA53_CPU1>;
177 next-level-cache = <&L2_CA53>;
178 enable-method = "psci";
179 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
180 operating-points-v2 = <&cluster1_opp>;
181 capacity-dmips-mhz = <560>;
182 };
184 a53_2: cpu@102 {
185 compatible = "arm,cortex-a53";
186 reg = <0x102>;
187 device_type = "cpu";
188 power-domains = <&sysc R8A774A1_PD_CA53_CPU2>;
189 next-level-cache = <&L2_CA53>;
190 enable-method = "psci";
191 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
192 operating-points-v2 = <&cluster1_opp>;
193 capacity-dmips-mhz = <560>;
194 };
196 a53_3: cpu@103 {
197 compatible = "arm,cortex-a53";
198 reg = <0x103>;
199 device_type = "cpu";
200 power-domains = <&sysc R8A774A1_PD_CA53_CPU3>;
201 next-level-cache = <&L2_CA53>;
202 enable-method = "psci";
203 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
204 operating-points-v2 = <&cluster1_opp>;
205 capacity-dmips-mhz = <560>;
206 };
208 L2_CA57: cache-controller-0 {
209 compatible = "cache";
210 power-domains = <&sysc R8A774A1_PD_CA57_SCU>;
211 cache-unified;
212 cache-level = <2>;
213 };
215 L2_CA53: cache-controller-1 {
216 compatible = "cache";
217 power-domains = <&sysc R8A774A1_PD_CA53_SCU>;
218 cache-unified;
219 cache-level = <2>;
220 };
221 };
223 extal_clk: extal {
224 compatible = "fixed-clock";
225 #clock-cells = <0>;
226 /* This value must be overridden by the board */
227 clock-frequency = <0>;
228 };
230 extalr_clk: extalr {
231 compatible = "fixed-clock";
232 #clock-cells = <0>;
233 /* This value must be overridden by the board */
234 clock-frequency = <0>;
235 };
237 /* External PCIe clock - can be overridden by the board */
238 pcie_bus_clk: pcie_bus {
239 compatible = "fixed-clock";
240 #clock-cells = <0>;
241 clock-frequency = <0>;
242 };
244 pmu_a53 {
245 compatible = "arm,cortex-a53-pmu";
246 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
247 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
248 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
249 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
250 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
251 };
253 pmu_a57 {
254 compatible = "arm,cortex-a57-pmu";
255 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
256 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
257 interrupt-affinity = <&a57_0>, <&a57_1>;
258 };
260 psci {
261 compatible = "arm,psci-1.0", "arm,psci-0.2";
262 method = "smc";
263 };
265 /* External SCIF clock - to be overridden by boards that provide it */
266 scif_clk: scif {
267 compatible = "fixed-clock";
268 #clock-cells = <0>;
269 clock-frequency = <0>;
270 };
272 soc {
273 compatible = "simple-bus";
274 interrupt-parent = <&gic>;
275 #address-cells = <2>;
276 #size-cells = <2>;
277 ranges;
279 rwdt: watchdog@e6020000 {
280 compatible = "renesas,r8a774a1-wdt",
281 "renesas,rcar-gen3-wdt";
282 reg = <0 0xe6020000 0 0x0c>;
283 clocks = <&cpg CPG_MOD 402>;
284 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
285 resets = <&cpg 402>;
286 status = "disabled";
287 };
289 gpio0: gpio@e6050000 {
290 compatible = "renesas,gpio-r8a774a1",
291 "renesas,rcar-gen3-gpio";
292 reg = <0 0xe6050000 0 0x50>;
293 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
294 #gpio-cells = <2>;
295 gpio-controller;
296 gpio-ranges = <&pfc 0 0 16>;
297 #interrupt-cells = <2>;
298 interrupt-controller;
299 clocks = <&cpg CPG_MOD 912>;
300 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
301 resets = <&cpg 912>;
302 };
304 gpio1: gpio@e6051000 {
305 compatible = "renesas,gpio-r8a774a1",
306 "renesas,rcar-gen3-gpio";
307 reg = <0 0xe6051000 0 0x50>;
308 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
309 #gpio-cells = <2>;
310 gpio-controller;
311 gpio-ranges = <&pfc 0 32 29>;
312 #interrupt-cells = <2>;
313 interrupt-controller;
314 clocks = <&cpg CPG_MOD 911>;
315 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
316 resets = <&cpg 911>;
317 };
319 gpio2: gpio@e6052000 {
320 compatible = "renesas,gpio-r8a774a1",
321 "renesas,rcar-gen3-gpio";
322 reg = <0 0xe6052000 0 0x50>;
323 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
324 #gpio-cells = <2>;
325 gpio-controller;
326 gpio-ranges = <&pfc 0 64 15>;
327 #interrupt-cells = <2>;
328 interrupt-controller;
329 clocks = <&cpg CPG_MOD 910>;
330 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
331 resets = <&cpg 910>;
332 };
334 gpio3: gpio@e6053000 {
335 compatible = "renesas,gpio-r8a774a1",
336 "renesas,rcar-gen3-gpio";
337 reg = <0 0xe6053000 0 0x50>;
338 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
339 #gpio-cells = <2>;
340 gpio-controller;
341 gpio-ranges = <&pfc 0 96 16>;
342 #interrupt-cells = <2>;
343 interrupt-controller;
344 clocks = <&cpg CPG_MOD 909>;
345 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
346 resets = <&cpg 909>;
347 };
349 gpio4: gpio@e6054000 {
350 compatible = "renesas,gpio-r8a774a1",
351 "renesas,rcar-gen3-gpio";
352 reg = <0 0xe6054000 0 0x50>;
353 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
354 #gpio-cells = <2>;
355 gpio-controller;
356 gpio-ranges = <&pfc 0 128 18>;
357 #interrupt-cells = <2>;
358 interrupt-controller;
359 clocks = <&cpg CPG_MOD 908>;
360 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
361 resets = <&cpg 908>;
362 };
364 gpio5: gpio@e6055000 {
365 compatible = "renesas,gpio-r8a774a1",
366 "renesas,rcar-gen3-gpio";
367 reg = <0 0xe6055000 0 0x50>;
368 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
369 #gpio-cells = <2>;
370 gpio-controller;
371 gpio-ranges = <&pfc 0 160 26>;
372 #interrupt-cells = <2>;
373 interrupt-controller;
374 clocks = <&cpg CPG_MOD 907>;
375 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
376 resets = <&cpg 907>;
377 };
379 gpio6: gpio@e6055400 {
380 compatible = "renesas,gpio-r8a774a1",
381 "renesas,rcar-gen3-gpio";
382 reg = <0 0xe6055400 0 0x50>;
383 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
384 #gpio-cells = <2>;
385 gpio-controller;
386 gpio-ranges = <&pfc 0 192 32>;
387 #interrupt-cells = <2>;
388 interrupt-controller;
389 clocks = <&cpg CPG_MOD 906>;
390 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
391 resets = <&cpg 906>;
392 };
394 gpio7: gpio@e6055800 {
395 compatible = "renesas,gpio-r8a774a1",
396 "renesas,rcar-gen3-gpio";
397 reg = <0 0xe6055800 0 0x50>;
398 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
399 #gpio-cells = <2>;
400 gpio-controller;
401 gpio-ranges = <&pfc 0 224 4>;
402 #interrupt-cells = <2>;
403 interrupt-controller;
404 clocks = <&cpg CPG_MOD 905>;
405 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
406 resets = <&cpg 905>;
407 };
409 pfc: pin-controller@e6060000 {
410 compatible = "renesas,pfc-r8a774a1";
411 reg = <0 0xe6060000 0 0x50c>;
412 };
414 cmt0: timer@e60f0000 {
415 compatible = "renesas,r8a774a1-cmt0",
416 "renesas,rcar-gen3-cmt0";
417 reg = <0 0xe60f0000 0 0x1004>;
418 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
419 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&cpg CPG_MOD 303>;
421 clock-names = "fck";
422 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
423 resets = <&cpg 303>;
424 status = "disabled";
425 };
427 cmt1: timer@e6130000 {
428 compatible = "renesas,r8a774a1-cmt1",
429 "renesas,rcar-gen3-cmt1";
430 reg = <0 0xe6130000 0 0x1004>;
431 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
432 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
433 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
434 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
435 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
436 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
437 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
438 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
439 clocks = <&cpg CPG_MOD 302>;
440 clock-names = "fck";
441 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
442 resets = <&cpg 302>;
443 status = "disabled";
444 };
446 cmt2: timer@e6140000 {
447 compatible = "renesas,r8a774a1-cmt1",
448 "renesas,rcar-gen3-cmt1";
449 reg = <0 0xe6140000 0 0x1004>;
450 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
451 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
452 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
453 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
454 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
455 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
456 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
457 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
458 clocks = <&cpg CPG_MOD 301>;
459 clock-names = "fck";
460 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
461 resets = <&cpg 301>;
462 status = "disabled";
463 };
465 cmt3: timer@e6148000 {
466 compatible = "renesas,r8a774a1-cmt1",
467 "renesas,rcar-gen3-cmt1";
468 reg = <0 0xe6148000 0 0x1004>;
469 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
470 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
471 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
472 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
474 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
475 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
476 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
477 clocks = <&cpg CPG_MOD 300>;
478 clock-names = "fck";
479 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
480 resets = <&cpg 300>;
481 status = "disabled";
482 };
484 cpg: clock-controller@e6150000 {
485 compatible = "renesas,r8a774a1-cpg-mssr";
486 reg = <0 0xe6150000 0 0x0bb0>;
487 clocks = <&extal_clk>, <&extalr_clk>;
488 clock-names = "extal", "extalr";
489 #clock-cells = <2>;
490 #power-domain-cells = <0>;
491 #reset-cells = <1>;
492 };
494 rst: reset-controller@e6160000 {
495 compatible = "renesas,r8a774a1-rst";
496 reg = <0 0xe6160000 0 0x018c>;
497 };
499 sysc: system-controller@e6180000 {
500 compatible = "renesas,r8a774a1-sysc";
501 reg = <0 0xe6180000 0 0x0400>;
502 #power-domain-cells = <1>;
503 };
505 tsc: thermal@e6198000 {
506 compatible = "renesas,r8a774a1-thermal";
507 reg = <0 0xe6198000 0 0x100>,
508 <0 0xe61a0000 0 0x100>,
509 <0 0xe61a8000 0 0x100>;
510 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
511 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
513 clocks = <&cpg CPG_MOD 522>;
514 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
515 resets = <&cpg 522>;
516 #thermal-sensor-cells = <1>;
517 };
519 intc_ex: interrupt-controller@e61c0000 {
520 compatible = "renesas,intc-ex-r8a774a1", "renesas,irqc";
521 #interrupt-cells = <2>;
522 interrupt-controller;
523 reg = <0 0xe61c0000 0 0x200>;
524 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
525 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
526 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
527 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
528 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
529 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
530 clocks = <&cpg CPG_MOD 407>;
531 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
532 resets = <&cpg 407>;
533 };
535 tmu0: timer@e61e0000 {
536 compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
537 reg = <0 0xe61e0000 0 0x30>;
538 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
539 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
540 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
541 clocks = <&cpg CPG_MOD 125>;
542 clock-names = "fck";
543 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
544 resets = <&cpg 125>;
545 status = "disabled";
546 };
548 tmu1: timer@e6fc0000 {
549 compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
550 reg = <0 0xe6fc0000 0 0x30>;
551 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
552 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
553 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
554 clocks = <&cpg CPG_MOD 124>;
555 clock-names = "fck";
556 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
557 resets = <&cpg 124>;
558 status = "disabled";
559 };
561 tmu2: timer@e6fd0000 {
562 compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
563 reg = <0 0xe6fd0000 0 0x30>;
564 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
566 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
567 clocks = <&cpg CPG_MOD 123>;
568 clock-names = "fck";
569 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
570 resets = <&cpg 123>;
571 status = "disabled";
572 };
574 tmu3: timer@e6fe0000 {
575 compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
576 reg = <0 0xe6fe0000 0 0x30>;
577 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
578 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
579 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
580 clocks = <&cpg CPG_MOD 122>;
581 clock-names = "fck";
582 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
583 resets = <&cpg 122>;
584 status = "disabled";
585 };
587 tmu4: timer@ffc00000 {
588 compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
589 reg = <0 0xffc00000 0 0x30>;
590 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
591 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
592 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
593 clocks = <&cpg CPG_MOD 121>;
594 clock-names = "fck";
595 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
596 resets = <&cpg 121>;
597 status = "disabled";
598 };
600 i2c0: i2c@e6500000 {
601 #address-cells = <1>;
602 #size-cells = <0>;
603 compatible = "renesas,i2c-r8a774a1",
604 "renesas,rcar-gen3-i2c";
605 reg = <0 0xe6500000 0 0x40>;
606 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
607 clocks = <&cpg CPG_MOD 931>;
608 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
609 resets = <&cpg 931>;
610 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
611 <&dmac2 0x91>, <&dmac2 0x90>;
612 dma-names = "tx", "rx", "tx", "rx";
613 i2c-scl-internal-delay-ns = <110>;
614 status = "disabled";
615 };
617 i2c1: i2c@e6508000 {
618 #address-cells = <1>;
619 #size-cells = <0>;
620 compatible = "renesas,i2c-r8a774a1",
621 "renesas,rcar-gen3-i2c";
622 reg = <0 0xe6508000 0 0x40>;
623 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
624 clocks = <&cpg CPG_MOD 930>;
625 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
626 resets = <&cpg 930>;
627 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
628 <&dmac2 0x93>, <&dmac2 0x92>;
629 dma-names = "tx", "rx", "tx", "rx";
630 i2c-scl-internal-delay-ns = <6>;
631 status = "disabled";
632 };
634 i2c2: i2c@e6510000 {
635 #address-cells = <1>;
636 #size-cells = <0>;
637 compatible = "renesas,i2c-r8a774a1",
638 "renesas,rcar-gen3-i2c";
639 reg = <0 0xe6510000 0 0x40>;
640 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
641 clocks = <&cpg CPG_MOD 929>;
642 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
643 resets = <&cpg 929>;
644 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
645 <&dmac2 0x95>, <&dmac2 0x94>;
646 dma-names = "tx", "rx", "tx", "rx";
647 i2c-scl-internal-delay-ns = <6>;
648 status = "disabled";
649 };
651 i2c3: i2c@e66d0000 {
652 #address-cells = <1>;
653 #size-cells = <0>;
654 compatible = "renesas,i2c-r8a774a1",
655 "renesas,rcar-gen3-i2c";
656 reg = <0 0xe66d0000 0 0x40>;
657 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
658 clocks = <&cpg CPG_MOD 928>;
659 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
660 resets = <&cpg 928>;
661 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
662 dma-names = "tx", "rx";
663 i2c-scl-internal-delay-ns = <110>;
664 status = "disabled";
665 };
667 i2c4: i2c@e66d8000 {
668 #address-cells = <1>;
669 #size-cells = <0>;
670 compatible = "renesas,i2c-r8a774a1",
671 "renesas,rcar-gen3-i2c";
672 reg = <0 0xe66d8000 0 0x40>;
673 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
674 clocks = <&cpg CPG_MOD 927>;
675 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
676 resets = <&cpg 927>;
677 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
678 dma-names = "tx", "rx";
679 i2c-scl-internal-delay-ns = <110>;
680 status = "disabled";
681 };
683 i2c5: i2c@e66e0000 {
684 #address-cells = <1>;
685 #size-cells = <0>;
686 compatible = "renesas,i2c-r8a774a1",
687 "renesas,rcar-gen3-i2c";
688 reg = <0 0xe66e0000 0 0x40>;
689 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
690 clocks = <&cpg CPG_MOD 919>;
691 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
692 resets = <&cpg 919>;
693 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
694 dma-names = "tx", "rx";
695 i2c-scl-internal-delay-ns = <110>;
696 status = "disabled";
697 };
699 i2c6: i2c@e66e8000 {
700 #address-cells = <1>;
701 #size-cells = <0>;
702 compatible = "renesas,i2c-r8a774a1",
703 "renesas,rcar-gen3-i2c";
704 reg = <0 0xe66e8000 0 0x40>;
705 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
706 clocks = <&cpg CPG_MOD 918>;
707 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
708 resets = <&cpg 918>;
709 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
710 dma-names = "tx", "rx";
711 i2c-scl-internal-delay-ns = <6>;
712 status = "disabled";
713 };
715 i2c_dvfs: i2c@e60b0000 {
716 #address-cells = <1>;
717 #size-cells = <0>;
718 compatible = "renesas,iic-r8a774a1",
719 "renesas,rcar-gen3-iic",
720 "renesas,rmobile-iic";
721 reg = <0 0xe60b0000 0 0x425>;
722 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
723 clocks = <&cpg CPG_MOD 926>;
724 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
725 resets = <&cpg 926>;
726 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
727 dma-names = "tx", "rx";
728 status = "disabled";
729 };
731 hscif0: serial@e6540000 {
732 compatible = "renesas,hscif-r8a774a1",
733 "renesas,rcar-gen3-hscif",
734 "renesas,hscif";
735 reg = <0 0xe6540000 0 0x60>;
736 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
737 clocks = <&cpg CPG_MOD 520>,
738 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
739 <&scif_clk>;
740 clock-names = "fck", "brg_int", "scif_clk";
741 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
742 <&dmac2 0x31>, <&dmac2 0x30>;
743 dma-names = "tx", "rx", "tx", "rx";
744 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
745 resets = <&cpg 520>;
746 status = "disabled";
747 };
749 hscif1: serial@e6550000 {
750 compatible = "renesas,hscif-r8a774a1",
751 "renesas,rcar-gen3-hscif",
752 "renesas,hscif";
753 reg = <0 0xe6550000 0 0x60>;
754 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
755 clocks = <&cpg CPG_MOD 519>,
756 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
757 <&scif_clk>;
758 clock-names = "fck", "brg_int", "scif_clk";
759 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
760 <&dmac2 0x33>, <&dmac2 0x32>;
761 dma-names = "tx", "rx", "tx", "rx";
762 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
763 resets = <&cpg 519>;
764 status = "disabled";
765 };
767 hscif2: serial@e6560000 {
768 compatible = "renesas,hscif-r8a774a1",
769 "renesas,rcar-gen3-hscif",
770 "renesas,hscif";
771 reg = <0 0xe6560000 0 0x60>;
772 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
773 clocks = <&cpg CPG_MOD 518>,
774 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
775 <&scif_clk>;
776 clock-names = "fck", "brg_int", "scif_clk";
777 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
778 <&dmac2 0x35>, <&dmac2 0x34>;
779 dma-names = "tx", "rx", "tx", "rx";
780 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
781 resets = <&cpg 518>;
782 status = "disabled";
783 };
785 hscif3: serial@e66a0000 {
786 compatible = "renesas,hscif-r8a774a1",
787 "renesas,rcar-gen3-hscif",
788 "renesas,hscif";
789 reg = <0 0xe66a0000 0 0x60>;
790 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
791 clocks = <&cpg CPG_MOD 517>,
792 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
793 <&scif_clk>;
794 clock-names = "fck", "brg_int", "scif_clk";
795 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
796 dma-names = "tx", "rx";
797 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
798 resets = <&cpg 517>;
799 status = "disabled";
800 };
802 hscif4: serial@e66b0000 {
803 compatible = "renesas,hscif-r8a774a1",
804 "renesas,rcar-gen3-hscif",
805 "renesas,hscif";
806 reg = <0 0xe66b0000 0 0x60>;
807 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
808 clocks = <&cpg CPG_MOD 516>,
809 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
810 <&scif_clk>;
811 clock-names = "fck", "brg_int", "scif_clk";
812 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
813 dma-names = "tx", "rx";
814 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
815 resets = <&cpg 516>;
816 status = "disabled";
817 };
819 hsusb: usb@e6590000 {
820 compatible = "renesas,usbhs-r8a774a1",
821 "renesas,rcar-gen3-usbhs";
822 reg = <0 0xe6590000 0 0x200>;
823 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
824 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
825 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
826 <&usb_dmac1 0>, <&usb_dmac1 1>;
827 dma-names = "ch0", "ch1", "ch2", "ch3";
828 renesas,buswait = <11>;
829 phys = <&usb2_phy0 3>;
830 phy-names = "usb";
831 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
832 resets = <&cpg 704>, <&cpg 703>;
833 status = "disabled";
834 };
836 usb_dmac0: dma-controller@e65a0000 {
837 compatible = "renesas,r8a774a1-usb-dmac",
838 "renesas,usb-dmac";
839 reg = <0 0xe65a0000 0 0x100>;
840 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
841 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
842 interrupt-names = "ch0", "ch1";
843 clocks = <&cpg CPG_MOD 330>;
844 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
845 resets = <&cpg 330>;
846 #dma-cells = <1>;
847 dma-channels = <2>;
848 };
850 usb_dmac1: dma-controller@e65b0000 {
851 compatible = "renesas,r8a774a1-usb-dmac",
852 "renesas,usb-dmac";
853 reg = <0 0xe65b0000 0 0x100>;
854 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
855 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
856 interrupt-names = "ch0", "ch1";
857 clocks = <&cpg CPG_MOD 331>;
858 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
859 resets = <&cpg 331>;
860 #dma-cells = <1>;
861 dma-channels = <2>;
862 };
864 usb3_phy0: usb-phy@e65ee000 {
865 compatible = "renesas,r8a774a1-usb3-phy",
866 "renesas,rcar-gen3-usb3-phy";
867 reg = <0 0xe65ee000 0 0x90>;
868 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
869 <&usb_extal_clk>;
870 clock-names = "usb3-if", "usb3s_clk", "usb_extal";
871 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
872 resets = <&cpg 328>;
873 #phy-cells = <0>;
874 status = "disabled";
875 };
877 dmac0: dma-controller@e6700000 {
878 compatible = "renesas,dmac-r8a774a1",
879 "renesas,rcar-dmac";
880 reg = <0 0xe6700000 0 0x10000>;
881 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
882 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
883 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
884 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
885 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
886 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
887 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
888 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
889 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
890 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
891 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
892 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
893 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
894 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
895 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
896 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
897 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
898 interrupt-names = "error",
899 "ch0", "ch1", "ch2", "ch3",
900 "ch4", "ch5", "ch6", "ch7",
901 "ch8", "ch9", "ch10", "ch11",
902 "ch12", "ch13", "ch14", "ch15";
903 clocks = <&cpg CPG_MOD 219>;
904 clock-names = "fck";
905 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
906 resets = <&cpg 219>;
907 #dma-cells = <1>;
908 dma-channels = <16>;
909 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
910 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
911 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
912 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
913 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
914 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
915 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
916 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
917 };
919 dmac1: dma-controller@e7300000 {
920 compatible = "renesas,dmac-r8a774a1",
921 "renesas,rcar-dmac";
922 reg = <0 0xe7300000 0 0x10000>;
923 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
924 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
925 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
926 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
927 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
928 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
929 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
930 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
931 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
932 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
933 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
934 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
935 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
936 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
937 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
938 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
939 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
940 interrupt-names = "error",
941 "ch0", "ch1", "ch2", "ch3",
942 "ch4", "ch5", "ch6", "ch7",
943 "ch8", "ch9", "ch10", "ch11",
944 "ch12", "ch13", "ch14", "ch15";
945 clocks = <&cpg CPG_MOD 218>;
946 clock-names = "fck";
947 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
948 resets = <&cpg 218>;
949 #dma-cells = <1>;
950 dma-channels = <16>;
951 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
952 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
953 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
954 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
955 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
956 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
957 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
958 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
959 };
961 dmac2: dma-controller@e7310000 {
962 compatible = "renesas,dmac-r8a774a1",
963 "renesas,rcar-dmac";
964 reg = <0 0xe7310000 0 0x10000>;
965 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
966 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
967 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
968 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
969 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
970 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
971 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
972 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
973 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
974 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
975 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
976 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
977 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
978 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
979 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
980 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
981 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
982 interrupt-names = "error",
983 "ch0", "ch1", "ch2", "ch3",
984 "ch4", "ch5", "ch6", "ch7",
985 "ch8", "ch9", "ch10", "ch11",
986 "ch12", "ch13", "ch14", "ch15";
987 clocks = <&cpg CPG_MOD 217>;
988 clock-names = "fck";
989 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
990 resets = <&cpg 217>;
991 #dma-cells = <1>;
992 dma-channels = <16>;
993 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
994 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
995 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
996 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
997 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
998 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
999 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
1000 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
1001 };
1003 ipmmu_ds0: mmu@e6740000 {
1004 compatible = "renesas,ipmmu-r8a774a1";
1005 reg = <0 0xe6740000 0 0x1000>;
1006 renesas,ipmmu-main = <&ipmmu_mm 0>;
1007 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1008 #iommu-cells = <1>;
1009 };
1011 ipmmu_ds1: mmu@e7740000 {
1012 compatible = "renesas,ipmmu-r8a774a1";
1013 reg = <0 0xe7740000 0 0x1000>;
1014 renesas,ipmmu-main = <&ipmmu_mm 1>;
1015 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1016 #iommu-cells = <1>;
1017 };
1019 ipmmu_hc: mmu@e6570000 {
1020 compatible = "renesas,ipmmu-r8a774a1";
1021 reg = <0 0xe6570000 0 0x1000>;
1022 renesas,ipmmu-main = <&ipmmu_mm 2>;
1023 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1024 #iommu-cells = <1>;
1025 };
1027 ipmmu_mm: mmu@e67b0000 {
1028 compatible = "renesas,ipmmu-r8a774a1";
1029 reg = <0 0xe67b0000 0 0x1000>;
1030 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1031 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
1032 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1033 #iommu-cells = <1>;
1034 };
1036 ipmmu_mp: mmu@ec670000 {
1037 compatible = "renesas,ipmmu-r8a774a1";
1038 reg = <0 0xec670000 0 0x1000>;
1039 renesas,ipmmu-main = <&ipmmu_mm 4>;
1040 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1041 #iommu-cells = <1>;
1042 };
1044 ipmmu_pv0: mmu@fd800000 {
1045 compatible = "renesas,ipmmu-r8a774a1";
1046 reg = <0 0xfd800000 0 0x1000>;
1047 renesas,ipmmu-main = <&ipmmu_mm 5>;
1048 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1049 #iommu-cells = <1>;
1050 };
1052 ipmmu_pv1: mmu@fd950000 {
1053 compatible = "renesas,ipmmu-r8a774a1";
1054 reg = <0 0xfd950000 0 0x1000>;
1055 renesas,ipmmu-main = <&ipmmu_mm 6>;
1056 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1057 #iommu-cells = <1>;
1058 };
1060 ipmmu_vc0: mmu@fe6b0000 {
1061 compatible = "renesas,ipmmu-r8a774a1";
1062 reg = <0 0xfe6b0000 0 0x1000>;
1063 renesas,ipmmu-main = <&ipmmu_mm 8>;
1064 power-domains = <&sysc R8A774A1_PD_A3VC>;
1065 #iommu-cells = <1>;
1066 };
1068 ipmmu_vi0: mmu@febd0000 {
1069 compatible = "renesas,ipmmu-r8a774a1";
1070 reg = <0 0xfebd0000 0 0x1000>;
1071 renesas,ipmmu-main = <&ipmmu_mm 9>;
1072 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1073 #iommu-cells = <1>;
1074 };
1076 avb: ethernet@e6800000 {
1077 compatible = "renesas,etheravb-r8a774a1",
1078 "renesas,etheravb-rcar-gen3";
1079 reg = <0 0xe6800000 0 0x800>;
1080 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1081 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1082 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
1083 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
1084 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
1085 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1086 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1087 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
1088 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
1089 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
1090 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
1091 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
1092 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
1093 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
1094 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
1095 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
1096 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
1097 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1098 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1099 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1100 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
1101 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
1102 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
1103 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
1104 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1105 interrupt-names = "ch0", "ch1", "ch2", "ch3",
1106 "ch4", "ch5", "ch6", "ch7",
1107 "ch8", "ch9", "ch10", "ch11",
1108 "ch12", "ch13", "ch14", "ch15",
1109 "ch16", "ch17", "ch18", "ch19",
1110 "ch20", "ch21", "ch22", "ch23",
1111 "ch24";
1112 clocks = <&cpg CPG_MOD 812>;
1113 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1114 resets = <&cpg 812>;
1115 phy-mode = "rgmii";
1116 iommus = <&ipmmu_ds0 16>;
1117 #address-cells = <1>;
1118 #size-cells = <0>;
1119 status = "disabled";
1120 };
1122 can0: can@e6c30000 {
1123 compatible = "renesas,can-r8a774a1",
1124 "renesas,rcar-gen3-can";
1125 reg = <0 0xe6c30000 0 0x1000>;
1126 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1127 clocks = <&cpg CPG_MOD 916>,
1128 <&cpg CPG_CORE R8A774A1_CLK_CANFD>,
1129 <&can_clk>;
1130 clock-names = "clkp1", "clkp2", "can_clk";
1131 assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>;
1132 assigned-clock-rates = <40000000>;
1133 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1134 resets = <&cpg 916>;
1135 status = "disabled";
1136 };
1138 can1: can@e6c38000 {
1139 compatible = "renesas,can-r8a774a1",
1140 "renesas,rcar-gen3-can";
1141 reg = <0 0xe6c38000 0 0x1000>;
1142 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1143 clocks = <&cpg CPG_MOD 915>,
1144 <&cpg CPG_CORE R8A774A1_CLK_CANFD>,
1145 <&can_clk>;
1146 clock-names = "clkp1", "clkp2", "can_clk";
1147 assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>;
1148 assigned-clock-rates = <40000000>;
1149 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1150 resets = <&cpg 915>;
1151 status = "disabled";
1152 };
1154 canfd: can@e66c0000 {
1155 compatible = "renesas,r8a774a1-canfd",
1156 "renesas,rcar-gen3-canfd";
1157 reg = <0 0xe66c0000 0 0x8000>;
1158 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1159 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1160 clocks = <&cpg CPG_MOD 914>,
1161 <&cpg CPG_CORE R8A774A1_CLK_CANFD>,
1162 <&can_clk>;
1163 clock-names = "fck", "canfd", "can_clk";
1164 assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>;
1165 assigned-clock-rates = <40000000>;
1166 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1167 resets = <&cpg 914>;
1168 status = "disabled";
1170 channel0 {
1171 status = "disabled";
1172 };
1174 channel1 {
1175 status = "disabled";
1176 };
1177 };
1179 pwm0: pwm@e6e30000 {
1180 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
1181 reg = <0 0xe6e30000 0 0x8>;
1182 #pwm-cells = <2>;
1183 clocks = <&cpg CPG_MOD 523>;
1184 resets = <&cpg 523>;
1185 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1186 status = "disabled";
1187 };
1189 pwm1: pwm@e6e31000 {
1190 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
1191 reg = <0 0xe6e31000 0 0x8>;
1192 #pwm-cells = <2>;
1193 clocks = <&cpg CPG_MOD 523>;
1194 resets = <&cpg 523>;
1195 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1196 status = "disabled";
1197 };
1199 pwm2: pwm@e6e32000 {
1200 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
1201 reg = <0 0xe6e32000 0 0x8>;
1202 #pwm-cells = <2>;
1203 clocks = <&cpg CPG_MOD 523>;
1204 resets = <&cpg 523>;
1205 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1206 status = "disabled";
1207 };
1209 pwm3: pwm@e6e33000 {
1210 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
1211 reg = <0 0xe6e33000 0 0x8>;
1212 #pwm-cells = <2>;
1213 clocks = <&cpg CPG_MOD 523>;
1214 resets = <&cpg 523>;
1215 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1216 status = "disabled";
1217 };
1219 pwm4: pwm@e6e34000 {
1220 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
1221 reg = <0 0xe6e34000 0 0x8>;
1222 #pwm-cells = <2>;
1223 clocks = <&cpg CPG_MOD 523>;
1224 resets = <&cpg 523>;
1225 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1226 status = "disabled";
1227 };
1229 pwm5: pwm@e6e35000 {
1230 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
1231 reg = <0 0xe6e35000 0 0x8>;
1232 #pwm-cells = <2>;
1233 clocks = <&cpg CPG_MOD 523>;
1234 resets = <&cpg 523>;
1235 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1236 status = "disabled";
1237 };
1239 pwm6: pwm@e6e36000 {
1240 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
1241 reg = <0 0xe6e36000 0 0x8>;
1242 #pwm-cells = <2>;
1243 clocks = <&cpg CPG_MOD 523>;
1244 resets = <&cpg 523>;
1245 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1246 status = "disabled";
1247 };
1249 scif0: serial@e6e60000 {
1250 compatible = "renesas,scif-r8a774a1",
1251 "renesas,rcar-gen3-scif", "renesas,scif";
1252 reg = <0 0xe6e60000 0 0x40>;
1253 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1254 clocks = <&cpg CPG_MOD 207>,
1255 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
1256 <&scif_clk>;
1257 clock-names = "fck", "brg_int", "scif_clk";
1258 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1259 <&dmac2 0x51>, <&dmac2 0x50>;
1260 dma-names = "tx", "rx", "tx", "rx";
1261 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1262 resets = <&cpg 207>;
1263 status = "disabled";
1264 };
1266 scif1: serial@e6e68000 {
1267 compatible = "renesas,scif-r8a774a1",
1268 "renesas,rcar-gen3-scif", "renesas,scif";
1269 reg = <0 0xe6e68000 0 0x40>;
1270 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1271 clocks = <&cpg CPG_MOD 206>,
1272 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
1273 <&scif_clk>;
1274 clock-names = "fck", "brg_int", "scif_clk";
1275 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1276 <&dmac2 0x53>, <&dmac2 0x52>;
1277 dma-names = "tx", "rx", "tx", "rx";
1278 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1279 resets = <&cpg 206>;
1280 status = "disabled";
1281 };
1283 scif2: serial@e6e88000 {
1284 compatible = "renesas,scif-r8a774a1",
1285 "renesas,rcar-gen3-scif", "renesas,scif";
1286 reg = <0 0xe6e88000 0 0x40>;
1287 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1288 clocks = <&cpg CPG_MOD 310>,
1289 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
1290 <&scif_clk>;
1291 clock-names = "fck", "brg_int", "scif_clk";
1292 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1293 <&dmac2 0x13>, <&dmac2 0x12>;
1294 dma-names = "tx", "rx", "tx", "rx";
1295 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1296 resets = <&cpg 310>;
1297 status = "disabled";
1298 };
1300 scif3: serial@e6c50000 {
1301 compatible = "renesas,scif-r8a774a1",
1302 "renesas,rcar-gen3-scif", "renesas,scif";
1303 reg = <0 0xe6c50000 0 0x40>;
1304 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1305 clocks = <&cpg CPG_MOD 204>,
1306 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
1307 <&scif_clk>;
1308 clock-names = "fck", "brg_int", "scif_clk";
1309 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1310 dma-names = "tx", "rx";
1311 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1312 resets = <&cpg 204>;
1313 status = "disabled";
1314 };
1316 scif4: serial@e6c40000 {
1317 compatible = "renesas,scif-r8a774a1",
1318 "renesas,rcar-gen3-scif", "renesas,scif";
1319 reg = <0 0xe6c40000 0 0x40>;
1320 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1321 clocks = <&cpg CPG_MOD 203>,
1322 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
1323 <&scif_clk>;
1324 clock-names = "fck", "brg_int", "scif_clk";
1325 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1326 dma-names = "tx", "rx";
1327 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1328 resets = <&cpg 203>;
1329 status = "disabled";
1330 };
1332 scif5: serial@e6f30000 {
1333 compatible = "renesas,scif-r8a774a1",
1334 "renesas,rcar-gen3-scif", "renesas,scif";
1335 reg = <0 0xe6f30000 0 0x40>;
1336 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1337 clocks = <&cpg CPG_MOD 202>,
1338 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
1339 <&scif_clk>;
1340 clock-names = "fck", "brg_int", "scif_clk";
1341 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1342 <&dmac2 0x5b>, <&dmac2 0x5a>;
1343 dma-names = "tx", "rx", "tx", "rx";
1344 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1345 resets = <&cpg 202>;
1346 status = "disabled";
1347 };
1349 msiof0: spi@e6e90000 {
1350 compatible = "renesas,msiof-r8a774a1",
1351 "renesas,rcar-gen3-msiof";
1352 reg = <0 0xe6e90000 0 0x0064>;
1353 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1354 clocks = <&cpg CPG_MOD 211>;
1355 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1356 <&dmac2 0x41>, <&dmac2 0x40>;
1357 dma-names = "tx", "rx", "tx", "rx";
1358 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1359 resets = <&cpg 211>;
1360 #address-cells = <1>;
1361 #size-cells = <0>;
1362 status = "disabled";
1363 };
1365 msiof1: spi@e6ea0000 {
1366 compatible = "renesas,msiof-r8a774a1",
1367 "renesas,rcar-gen3-msiof";
1368 reg = <0 0xe6ea0000 0 0x0064>;
1369 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1370 clocks = <&cpg CPG_MOD 210>;
1371 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1372 <&dmac2 0x43>, <&dmac2 0x42>;
1373 dma-names = "tx", "rx", "tx", "rx";
1374 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1375 resets = <&cpg 210>;
1376 #address-cells = <1>;
1377 #size-cells = <0>;
1378 status = "disabled";
1379 };
1381 msiof2: spi@e6c00000 {
1382 compatible = "renesas,msiof-r8a774a1",
1383 "renesas,rcar-gen3-msiof";
1384 reg = <0 0xe6c00000 0 0x0064>;
1385 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1386 clocks = <&cpg CPG_MOD 209>;
1387 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1388 dma-names = "tx", "rx";
1389 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1390 resets = <&cpg 209>;
1391 #address-cells = <1>;
1392 #size-cells = <0>;
1393 status = "disabled";
1394 };
1396 msiof3: spi@e6c10000 {
1397 compatible = "renesas,msiof-r8a774a1",
1398 "renesas,rcar-gen3-msiof";
1399 reg = <0 0xe6c10000 0 0x0064>;
1400 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1401 clocks = <&cpg CPG_MOD 208>;
1402 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1403 dma-names = "tx", "rx";
1404 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1405 resets = <&cpg 208>;
1406 #address-cells = <1>;
1407 #size-cells = <0>;
1408 status = "disabled";
1409 };
1411 vin0: video@e6ef0000 {
1412 compatible = "renesas,vin-r8a774a1";
1413 reg = <0 0xe6ef0000 0 0x1000>;
1414 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1415 clocks = <&cpg CPG_MOD 811>;
1416 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1417 resets = <&cpg 811>;
1418 renesas,id = <0>;
1419 status = "disabled";
1421 ports {
1422 #address-cells = <1>;
1423 #size-cells = <0>;
1425 port@1 {
1426 #address-cells = <1>;
1427 #size-cells = <0>;
1429 reg = <1>;
1431 vin0csi20: endpoint@0 {
1432 reg = <0>;
1433 remote-endpoint = <&csi20vin0>;
1434 };
1435 vin0csi40: endpoint@2 {
1436 reg = <2>;
1437 remote-endpoint = <&csi40vin0>;
1438 };
1439 };
1440 };
1441 };
1443 vin1: video@e6ef1000 {
1444 compatible = "renesas,vin-r8a774a1";
1445 reg = <0 0xe6ef1000 0 0x1000>;
1446 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
1447 clocks = <&cpg CPG_MOD 810>;
1448 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1449 resets = <&cpg 810>;
1450 renesas,id = <1>;
1451 status = "disabled";
1453 ports {
1454 #address-cells = <1>;
1455 #size-cells = <0>;
1457 port@1 {
1458 #address-cells = <1>;
1459 #size-cells = <0>;
1461 reg = <1>;
1463 vin1csi20: endpoint@0 {
1464 reg = <0>;
1465 remote-endpoint = <&csi20vin1>;
1466 };
1467 vin1csi40: endpoint@2 {
1468 reg = <2>;
1469 remote-endpoint = <&csi40vin1>;
1470 };
1471 };
1472 };
1473 };
1475 vin2: video@e6ef2000 {
1476 compatible = "renesas,vin-r8a774a1";
1477 reg = <0 0xe6ef2000 0 0x1000>;
1478 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1479 clocks = <&cpg CPG_MOD 809>;
1480 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1481 resets = <&cpg 809>;
1482 renesas,id = <2>;
1483 status = "disabled";
1485 ports {
1486 #address-cells = <1>;
1487 #size-cells = <0>;
1489 port@1 {
1490 #address-cells = <1>;
1491 #size-cells = <0>;
1493 reg = <1>;
1495 vin2csi20: endpoint@0 {
1496 reg = <0>;
1497 remote-endpoint = <&csi20vin2>;
1498 };
1499 vin2csi40: endpoint@2 {
1500 reg = <2>;
1501 remote-endpoint = <&csi40vin2>;
1502 };
1503 };
1504 };
1505 };
1507 vin3: video@e6ef3000 {
1508 compatible = "renesas,vin-r8a774a1";
1509 reg = <0 0xe6ef3000 0 0x1000>;
1510 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
1511 clocks = <&cpg CPG_MOD 808>;
1512 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1513 resets = <&cpg 808>;
1514 renesas,id = <3>;
1515 status = "disabled";
1517 ports {
1518 #address-cells = <1>;
1519 #size-cells = <0>;
1521 port@1 {
1522 #address-cells = <1>;
1523 #size-cells = <0>;
1525 reg = <1>;
1527 vin3csi20: endpoint@0 {
1528 reg = <0>;
1529 remote-endpoint = <&csi20vin3>;
1530 };
1531 vin3csi40: endpoint@2 {
1532 reg = <2>;
1533 remote-endpoint = <&csi40vin3>;
1534 };
1535 };
1536 };
1537 };
1539 vin4: video@e6ef4000 {
1540 compatible = "renesas,vin-r8a774a1";
1541 reg = <0 0xe6ef4000 0 0x1000>;
1542 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1543 clocks = <&cpg CPG_MOD 807>;
1544 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1545 resets = <&cpg 807>;
1546 renesas,id = <4>;
1547 status = "disabled";
1549 ports {
1550 #address-cells = <1>;
1551 #size-cells = <0>;
1553 port@1 {
1554 #address-cells = <1>;
1555 #size-cells = <0>;
1557 reg = <1>;
1559 vin4csi20: endpoint@0 {
1560 reg = <0>;
1561 remote-endpoint = <&csi20vin4>;
1562 };
1563 vin4csi40: endpoint@2 {
1564 reg = <2>;
1565 remote-endpoint = <&csi40vin4>;
1566 };
1567 };
1568 };
1569 };
1571 vin5: video@e6ef5000 {
1572 compatible = "renesas,vin-r8a774a1";
1573 reg = <0 0xe6ef5000 0 0x1000>;
1574 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1575 clocks = <&cpg CPG_MOD 806>;
1576 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1577 resets = <&cpg 806>;
1578 renesas,id = <5>;
1579 status = "disabled";
1581 ports {
1582 #address-cells = <1>;
1583 #size-cells = <0>;
1585 port@1 {
1586 #address-cells = <1>;
1587 #size-cells = <0>;
1589 reg = <1>;
1591 vin5csi20: endpoint@0 {
1592 reg = <0>;
1593 remote-endpoint = <&csi20vin5>;
1594 };
1595 vin5csi40: endpoint@2 {
1596 reg = <2>;
1597 remote-endpoint = <&csi40vin5>;
1598 };
1599 };
1600 };
1601 };
1603 vin6: video@e6ef6000 {
1604 compatible = "renesas,vin-r8a774a1";
1605 reg = <0 0xe6ef6000 0 0x1000>;
1606 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
1607 clocks = <&cpg CPG_MOD 805>;
1608 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1609 resets = <&cpg 805>;
1610 renesas,id = <6>;
1611 status = "disabled";
1613 ports {
1614 #address-cells = <1>;
1615 #size-cells = <0>;
1617 port@1 {
1618 #address-cells = <1>;
1619 #size-cells = <0>;
1621 reg = <1>;
1623 vin6csi20: endpoint@0 {
1624 reg = <0>;
1625 remote-endpoint = <&csi20vin6>;
1626 };
1627 vin6csi40: endpoint@2 {
1628 reg = <2>;
1629 remote-endpoint = <&csi40vin6>;
1630 };
1631 };
1632 };
1633 };
1635 vin7: video@e6ef7000 {
1636 compatible = "renesas,vin-r8a774a1";
1637 reg = <0 0xe6ef7000 0 0x1000>;
1638 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
1639 clocks = <&cpg CPG_MOD 804>;
1640 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1641 resets = <&cpg 804>;
1642 renesas,id = <7>;
1643 status = "disabled";
1645 ports {
1646 #address-cells = <1>;
1647 #size-cells = <0>;
1649 port@1 {
1650 #address-cells = <1>;
1651 #size-cells = <0>;
1653 reg = <1>;
1655 vin7csi20: endpoint@0 {
1656 reg = <0>;
1657 remote-endpoint = <&csi20vin7>;
1658 };
1659 vin7csi40: endpoint@2 {
1660 reg = <2>;
1661 remote-endpoint = <&csi40vin7>;
1662 };
1663 };
1664 };
1665 };
1667 rcar_sound: sound@ec500000 {
1668 /*
1669 * #sound-dai-cells is required
1670 *
1671 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1672 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1673 */
1674 /*
1675 * #clock-cells is required for audio_clkout0/1/2/3
1676 *
1677 * clkout : #clock-cells = <0>; <&rcar_sound>;
1678 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
1679 */
1680 compatible = "renesas,rcar_sound-r8a774a1", "renesas,rcar_sound-gen3";
1681 reg = <0 0xec500000 0 0x1000>, /* SCU */
1682 <0 0xec5a0000 0 0x100>, /* ADG */
1683 <0 0xec540000 0 0x1000>, /* SSIU */
1684 <0 0xec541000 0 0x280>, /* SSI */
1685 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1686 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1688 clocks = <&cpg CPG_MOD 1005>,
1689 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1690 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1691 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1692 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1693 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1694 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1695 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1696 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1697 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1698 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1699 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1700 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1701 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1702 <&audio_clk_a>, <&audio_clk_b>,
1703 <&audio_clk_c>,
1704 <&cpg CPG_CORE R8A774A1_CLK_S0D4>;
1705 clock-names = "ssi-all",
1706 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1707 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1708 "ssi.1", "ssi.0",
1709 "src.9", "src.8", "src.7", "src.6",
1710 "src.5", "src.4", "src.3", "src.2",
1711 "src.1", "src.0",
1712 "mix.1", "mix.0",
1713 "ctu.1", "ctu.0",
1714 "dvc.0", "dvc.1",
1715 "clk_a", "clk_b", "clk_c", "clk_i";
1716 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1717 resets = <&cpg 1005>,
1718 <&cpg 1006>, <&cpg 1007>,
1719 <&cpg 1008>, <&cpg 1009>,
1720 <&cpg 1010>, <&cpg 1011>,
1721 <&cpg 1012>, <&cpg 1013>,
1722 <&cpg 1014>, <&cpg 1015>;
1723 reset-names = "ssi-all",
1724 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1725 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1726 "ssi.1", "ssi.0";
1727 status = "disabled";
1729 rcar_sound,ctu {
1730 ctu00: ctu-0 { };
1731 ctu01: ctu-1 { };
1732 ctu02: ctu-2 { };
1733 ctu03: ctu-3 { };
1734 ctu10: ctu-4 { };
1735 ctu11: ctu-5 { };
1736 ctu12: ctu-6 { };
1737 ctu13: ctu-7 { };
1738 };
1740 rcar_sound,dvc {
1741 dvc0: dvc-0 {
1742 dmas = <&audma1 0xbc>;
1743 dma-names = "tx";
1744 };
1745 dvc1: dvc-1 {
1746 dmas = <&audma1 0xbe>;
1747 dma-names = "tx";
1748 };
1749 };
1751 rcar_sound,mix {
1752 mix0: mix-0 { };
1753 mix1: mix-1 { };
1754 };
1756 rcar_sound,src {
1757 src0: src-0 {
1758 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1759 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1760 dma-names = "rx", "tx";
1761 };
1762 src1: src-1 {
1763 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1764 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1765 dma-names = "rx", "tx";
1766 };
1767 src2: src-2 {
1768 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1769 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1770 dma-names = "rx", "tx";
1771 };
1772 src3: src-3 {
1773 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1774 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1775 dma-names = "rx", "tx";
1776 };
1777 src4: src-4 {
1778 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1779 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1780 dma-names = "rx", "tx";
1781 };
1782 src5: src-5 {
1783 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1784 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1785 dma-names = "rx", "tx";
1786 };
1787 src6: src-6 {
1788 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1789 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1790 dma-names = "rx", "tx";
1791 };
1792 src7: src-7 {
1793 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1794 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1795 dma-names = "rx", "tx";
1796 };
1797 src8: src-8 {
1798 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1799 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1800 dma-names = "rx", "tx";
1801 };
1802 src9: src-9 {
1803 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1804 dmas = <&audma0 0x97>, <&audma1 0xba>;
1805 dma-names = "rx", "tx";
1806 };
1807 };
1809 rcar_sound,ssi {
1810 ssi0: ssi-0 {
1811 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1812 dmas = <&audma0 0x01>, <&audma1 0x02>;
1813 dma-names = "rx", "tx";
1814 };
1815 ssi1: ssi-1 {
1816 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1817 dmas = <&audma0 0x03>, <&audma1 0x04>;
1818 dma-names = "rx", "tx";
1819 };
1820 ssi2: ssi-2 {
1821 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1822 dmas = <&audma0 0x05>, <&audma1 0x06>;
1823 dma-names = "rx", "tx";
1824 };
1825 ssi3: ssi-3 {
1826 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1827 dmas = <&audma0 0x07>, <&audma1 0x08>;
1828 dma-names = "rx", "tx";
1829 };
1830 ssi4: ssi-4 {
1831 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1832 dmas = <&audma0 0x09>, <&audma1 0x0a>;
1833 dma-names = "rx", "tx";
1834 };
1835 ssi5: ssi-5 {
1836 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1837 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
1838 dma-names = "rx", "tx";
1839 };
1840 ssi6: ssi-6 {
1841 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1842 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
1843 dma-names = "rx", "tx";
1844 };
1845 ssi7: ssi-7 {
1846 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1847 dmas = <&audma0 0x0f>, <&audma1 0x10>;
1848 dma-names = "rx", "tx";
1849 };
1850 ssi8: ssi-8 {
1851 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1852 dmas = <&audma0 0x11>, <&audma1 0x12>;
1853 dma-names = "rx", "tx";
1854 };
1855 ssi9: ssi-9 {
1856 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1857 dmas = <&audma0 0x13>, <&audma1 0x14>;
1858 dma-names = "rx", "tx";
1859 };
1860 };
1862 rcar_sound,ssiu {
1863 ssiu00: ssiu-0 {
1864 dmas = <&audma0 0x15>, <&audma1 0x16>;
1865 dma-names = "rx", "tx";
1866 };
1867 ssiu01: ssiu-1 {
1868 dmas = <&audma0 0x35>, <&audma1 0x36>;
1869 dma-names = "rx", "tx";
1870 };
1871 ssiu02: ssiu-2 {
1872 dmas = <&audma0 0x37>, <&audma1 0x38>;
1873 dma-names = "rx", "tx";
1874 };
1875 ssiu03: ssiu-3 {
1876 dmas = <&audma0 0x47>, <&audma1 0x48>;
1877 dma-names = "rx", "tx";
1878 };
1879 ssiu04: ssiu-4 {
1880 dmas = <&audma0 0x3F>, <&audma1 0x40>;
1881 dma-names = "rx", "tx";
1882 };
1883 ssiu05: ssiu-5 {
1884 dmas = <&audma0 0x43>, <&audma1 0x44>;
1885 dma-names = "rx", "tx";
1886 };
1887 ssiu06: ssiu-6 {
1888 dmas = <&audma0 0x4F>, <&audma1 0x50>;
1889 dma-names = "rx", "tx";
1890 };
1891 ssiu07: ssiu-7 {
1892 dmas = <&audma0 0x53>, <&audma1 0x54>;
1893 dma-names = "rx", "tx";
1894 };
1895 ssiu10: ssiu-8 {
1896 dmas = <&audma0 0x49>, <&audma1 0x4a>;
1897 dma-names = "rx", "tx";
1898 };
1899 ssiu11: ssiu-9 {
1900 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
1901 dma-names = "rx", "tx";
1902 };
1903 ssiu12: ssiu-10 {
1904 dmas = <&audma0 0x57>, <&audma1 0x58>;
1905 dma-names = "rx", "tx";
1906 };
1907 ssiu13: ssiu-11 {
1908 dmas = <&audma0 0x59>, <&audma1 0x5A>;
1909 dma-names = "rx", "tx";
1910 };
1911 ssiu14: ssiu-12 {
1912 dmas = <&audma0 0x5F>, <&audma1 0x60>;
1913 dma-names = "rx", "tx";
1914 };
1915 ssiu15: ssiu-13 {
1916 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
1917 dma-names = "rx", "tx";
1918 };
1919 ssiu16: ssiu-14 {
1920 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
1921 dma-names = "rx", "tx";
1922 };
1923 ssiu17: ssiu-15 {
1924 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
1925 dma-names = "rx", "tx";
1926 };
1927 ssiu20: ssiu-16 {
1928 dmas = <&audma0 0x63>, <&audma1 0x64>;
1929 dma-names = "rx", "tx";
1930 };
1931 ssiu21: ssiu-17 {
1932 dmas = <&audma0 0x67>, <&audma1 0x68>;
1933 dma-names = "rx", "tx";
1934 };
1935 ssiu22: ssiu-18 {
1936 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
1937 dma-names = "rx", "tx";
1938 };
1939 ssiu23: ssiu-19 {
1940 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
1941 dma-names = "rx", "tx";
1942 };
1943 ssiu24: ssiu-20 {
1944 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
1945 dma-names = "rx", "tx";
1946 };
1947 ssiu25: ssiu-21 {
1948 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
1949 dma-names = "rx", "tx";
1950 };
1951 ssiu26: ssiu-22 {
1952 dmas = <&audma0 0xED>, <&audma1 0xEE>;
1953 dma-names = "rx", "tx";
1954 };
1955 ssiu27: ssiu-23 {
1956 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
1957 dma-names = "rx", "tx";
1958 };
1959 ssiu30: ssiu-24 {
1960 dmas = <&audma0 0x6f>, <&audma1 0x70>;
1961 dma-names = "rx", "tx";
1962 };
1963 ssiu31: ssiu-25 {
1964 dmas = <&audma0 0x21>, <&audma1 0x22>;
1965 dma-names = "rx", "tx";
1966 };
1967 ssiu32: ssiu-26 {
1968 dmas = <&audma0 0x23>, <&audma1 0x24>;
1969 dma-names = "rx", "tx";
1970 };
1971 ssiu33: ssiu-27 {
1972 dmas = <&audma0 0x25>, <&audma1 0x26>;
1973 dma-names = "rx", "tx";
1974 };
1975 ssiu34: ssiu-28 {
1976 dmas = <&audma0 0x27>, <&audma1 0x28>;
1977 dma-names = "rx", "tx";
1978 };
1979 ssiu35: ssiu-29 {
1980 dmas = <&audma0 0x29>, <&audma1 0x2A>;
1981 dma-names = "rx", "tx";
1982 };
1983 ssiu36: ssiu-30 {
1984 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
1985 dma-names = "rx", "tx";
1986 };
1987 ssiu37: ssiu-31 {
1988 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
1989 dma-names = "rx", "tx";
1990 };
1991 ssiu40: ssiu-32 {
1992 dmas = <&audma0 0x71>, <&audma1 0x72>;
1993 dma-names = "rx", "tx";
1994 };
1995 ssiu41: ssiu-33 {
1996 dmas = <&audma0 0x17>, <&audma1 0x18>;
1997 dma-names = "rx", "tx";
1998 };
1999 ssiu42: ssiu-34 {
2000 dmas = <&audma0 0x19>, <&audma1 0x1A>;
2001 dma-names = "rx", "tx";
2002 };
2003 ssiu43: ssiu-35 {
2004 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2005 dma-names = "rx", "tx";
2006 };
2007 ssiu44: ssiu-36 {
2008 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2009 dma-names = "rx", "tx";
2010 };
2011 ssiu45: ssiu-37 {
2012 dmas = <&audma0 0x1F>, <&audma1 0x20>;
2013 dma-names = "rx", "tx";
2014 };
2015 ssiu46: ssiu-38 {
2016 dmas = <&audma0 0x31>, <&audma1 0x32>;
2017 dma-names = "rx", "tx";
2018 };
2019 ssiu47: ssiu-39 {
2020 dmas = <&audma0 0x33>, <&audma1 0x34>;
2021 dma-names = "rx", "tx";
2022 };
2023 ssiu50: ssiu-40 {
2024 dmas = <&audma0 0x73>, <&audma1 0x74>;
2025 dma-names = "rx", "tx";
2026 };
2027 ssiu60: ssiu-41 {
2028 dmas = <&audma0 0x75>, <&audma1 0x76>;
2029 dma-names = "rx", "tx";
2030 };
2031 ssiu70: ssiu-42 {
2032 dmas = <&audma0 0x79>, <&audma1 0x7a>;
2033 dma-names = "rx", "tx";
2034 };
2035 ssiu80: ssiu-43 {
2036 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2037 dma-names = "rx", "tx";
2038 };
2039 ssiu90: ssiu-44 {
2040 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2041 dma-names = "rx", "tx";
2042 };
2043 ssiu91: ssiu-45 {
2044 dmas = <&audma0 0x7F>, <&audma1 0x80>;
2045 dma-names = "rx", "tx";
2046 };
2047 ssiu92: ssiu-46 {
2048 dmas = <&audma0 0x81>, <&audma1 0x82>;
2049 dma-names = "rx", "tx";
2050 };
2051 ssiu93: ssiu-47 {
2052 dmas = <&audma0 0x83>, <&audma1 0x84>;
2053 dma-names = "rx", "tx";
2054 };
2055 ssiu94: ssiu-48 {
2056 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2057 dma-names = "rx", "tx";
2058 };
2059 ssiu95: ssiu-49 {
2060 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2061 dma-names = "rx", "tx";
2062 };
2063 ssiu96: ssiu-50 {
2064 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2065 dma-names = "rx", "tx";
2066 };
2067 ssiu97: ssiu-51 {
2068 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2069 dma-names = "rx", "tx";
2070 };
2071 };
2072 };
2074 audma0: dma-controller@ec700000 {
2075 compatible = "renesas,dmac-r8a774a1",
2076 "renesas,rcar-dmac";
2077 reg = <0 0xec700000 0 0x10000>;
2078 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
2079 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2080 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
2081 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
2082 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
2083 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
2084 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
2085 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
2086 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
2087 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
2088 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2089 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
2090 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
2091 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
2092 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
2093 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2094 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
2095 interrupt-names = "error",
2096 "ch0", "ch1", "ch2", "ch3",
2097 "ch4", "ch5", "ch6", "ch7",
2098 "ch8", "ch9", "ch10", "ch11",
2099 "ch12", "ch13", "ch14", "ch15";
2100 clocks = <&cpg CPG_MOD 502>;
2101 clock-names = "fck";
2102 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2103 resets = <&cpg 502>;
2104 #dma-cells = <1>;
2105 dma-channels = <16>;
2106 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
2107 <&ipmmu_mp 2>, <&ipmmu_mp 3>,
2108 <&ipmmu_mp 4>, <&ipmmu_mp 5>,
2109 <&ipmmu_mp 6>, <&ipmmu_mp 7>,
2110 <&ipmmu_mp 8>, <&ipmmu_mp 9>,
2111 <&ipmmu_mp 10>, <&ipmmu_mp 11>,
2112 <&ipmmu_mp 12>, <&ipmmu_mp 13>,
2113 <&ipmmu_mp 14>, <&ipmmu_mp 15>;
2114 };
2116 audma1: dma-controller@ec720000 {
2117 compatible = "renesas,dmac-r8a774a1",
2118 "renesas,rcar-dmac";
2119 reg = <0 0xec720000 0 0x10000>;
2120 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
2121 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2122 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2123 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2124 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2125 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2126 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
2127 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
2128 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2129 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
2130 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
2131 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
2132 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2133 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
2134 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
2135 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
2136 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
2137 interrupt-names = "error",
2138 "ch0", "ch1", "ch2", "ch3",
2139 "ch4", "ch5", "ch6", "ch7",
2140 "ch8", "ch9", "ch10", "ch11",
2141 "ch12", "ch13", "ch14", "ch15";
2142 clocks = <&cpg CPG_MOD 501>;
2143 clock-names = "fck";
2144 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2145 resets = <&cpg 501>;
2146 #dma-cells = <1>;
2147 dma-channels = <16>;
2148 iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>,
2149 <&ipmmu_mp 18>, <&ipmmu_mp 19>,
2150 <&ipmmu_mp 20>, <&ipmmu_mp 21>,
2151 <&ipmmu_mp 22>, <&ipmmu_mp 23>,
2152 <&ipmmu_mp 24>, <&ipmmu_mp 25>,
2153 <&ipmmu_mp 26>, <&ipmmu_mp 27>,
2154 <&ipmmu_mp 28>, <&ipmmu_mp 29>,
2155 <&ipmmu_mp 30>, <&ipmmu_mp 31>;
2156 };
2158 xhci0: usb@ee000000 {
2159 compatible = "renesas,xhci-r8a774a1",
2160 "renesas,rcar-gen3-xhci";
2161 reg = <0 0xee000000 0 0xc00>;
2162 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2163 clocks = <&cpg CPG_MOD 328>;
2164 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2165 resets = <&cpg 328>;
2166 status = "disabled";
2167 };
2169 usb3_peri0: usb@ee020000 {
2170 compatible = "renesas,r8a774a1-usb3-peri",
2171 "renesas,rcar-gen3-usb3-peri";
2172 reg = <0 0xee020000 0 0x400>;
2173 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2174 clocks = <&cpg CPG_MOD 328>;
2175 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2176 resets = <&cpg 328>;
2177 status = "disabled";
2178 };
2180 ohci0: usb@ee080000 {
2181 compatible = "generic-ohci";
2182 reg = <0 0xee080000 0 0x100>;
2183 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2184 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2185 phys = <&usb2_phy0 1>;
2186 phy-names = "usb";
2187 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2188 resets = <&cpg 703>, <&cpg 704>;
2189 status = "disabled";
2190 };
2192 ohci1: usb@ee0a0000 {
2193 compatible = "generic-ohci";
2194 reg = <0 0xee0a0000 0 0x100>;
2195 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2196 clocks = <&cpg CPG_MOD 702>;
2197 phys = <&usb2_phy1 1>;
2198 phy-names = "usb";
2199 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2200 resets = <&cpg 702>;
2201 status = "disabled";
2202 };
2204 ehci0: usb@ee080100 {
2205 compatible = "generic-ehci";
2206 reg = <0 0xee080100 0 0x100>;
2207 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2208 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2209 phys = <&usb2_phy0 2>;
2210 phy-names = "usb";
2211 companion = <&ohci0>;
2212 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2213 resets = <&cpg 703>, <&cpg 704>;
2214 status = "disabled";
2215 };
2217 ehci1: usb@ee0a0100 {
2218 compatible = "generic-ehci";
2219 reg = <0 0xee0a0100 0 0x100>;
2220 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2221 clocks = <&cpg CPG_MOD 702>;
2222 phys = <&usb2_phy1 2>;
2223 phy-names = "usb";
2224 companion = <&ohci1>;
2225 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2226 resets = <&cpg 702>;
2227 status = "disabled";
2228 };
2230 usb2_phy0: usb-phy@ee080200 {
2231 compatible = "renesas,usb2-phy-r8a774a1",
2232 "renesas,rcar-gen3-usb2-phy";
2233 reg = <0 0xee080200 0 0x700>;
2234 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2235 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2236 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2237 resets = <&cpg 703>, <&cpg 704>;
2238 #phy-cells = <1>;
2239 status = "disabled";
2240 };
2242 usb2_phy1: usb-phy@ee0a0200 {
2243 compatible = "renesas,usb2-phy-r8a774a1",
2244 "renesas,rcar-gen3-usb2-phy";
2245 reg = <0 0xee0a0200 0 0x700>;
2246 clocks = <&cpg CPG_MOD 702>;
2247 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2248 resets = <&cpg 702>;
2249 #phy-cells = <1>;
2250 status = "disabled";
2251 };
2253 sdhi0: sd@ee100000 {
2254 compatible = "renesas,sdhi-r8a774a1",
2255 "renesas,rcar-gen3-sdhi";
2256 reg = <0 0xee100000 0 0x2000>;
2257 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
2258 clocks = <&cpg CPG_MOD 314>;
2259 max-frequency = <200000000>;
2260 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2261 resets = <&cpg 314>;
2262 status = "disabled";
2263 };
2265 sdhi1: sd@ee120000 {
2266 compatible = "renesas,sdhi-r8a774a1",
2267 "renesas,rcar-gen3-sdhi";
2268 reg = <0 0xee120000 0 0x2000>;
2269 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
2270 clocks = <&cpg CPG_MOD 313>;
2271 max-frequency = <200000000>;
2272 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2273 resets = <&cpg 313>;
2274 status = "disabled";
2275 };
2277 sdhi2: sd@ee140000 {
2278 compatible = "renesas,sdhi-r8a774a1",
2279 "renesas,rcar-gen3-sdhi";
2280 reg = <0 0xee140000 0 0x2000>;
2281 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
2282 clocks = <&cpg CPG_MOD 312>;
2283 max-frequency = <200000000>;
2284 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2285 resets = <&cpg 312>;
2286 status = "disabled";
2287 };
2289 sdhi3: sd@ee160000 {
2290 compatible = "renesas,sdhi-r8a774a1",
2291 "renesas,rcar-gen3-sdhi";
2292 reg = <0 0xee160000 0 0x2000>;
2293 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
2294 clocks = <&cpg CPG_MOD 311>;
2295 max-frequency = <200000000>;
2296 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2297 resets = <&cpg 311>;
2298 status = "disabled";
2299 };
2301 gic: interrupt-controller@f1010000 {
2302 compatible = "arm,gic-400";
2303 #interrupt-cells = <3>;
2304 #address-cells = <0>;
2305 interrupt-controller;
2306 reg = <0x0 0xf1010000 0 0x1000>,
2307 <0x0 0xf1020000 0 0x20000>,
2308 <0x0 0xf1040000 0 0x20000>,
2309 <0x0 0xf1060000 0 0x20000>;
2310 interrupts = <GIC_PPI 9
2311 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
2312 clocks = <&cpg CPG_MOD 408>;
2313 clock-names = "clk";
2314 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2315 resets = <&cpg 408>;
2316 };
2318 pciec0: pcie@fe000000 {
2319 compatible = "renesas,pcie-r8a774a1",
2320 "renesas,pcie-rcar-gen3";
2321 reg = <0 0xfe000000 0 0x80000>;
2322 #address-cells = <3>;
2323 #size-cells = <2>;
2324 bus-range = <0x00 0xff>;
2325 device_type = "pci";
2326 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2327 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2328 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2329 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2330 /* Map all possible DDR as inbound ranges */
2331 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2332 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2333 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2334 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
2335 #interrupt-cells = <1>;
2336 interrupt-map-mask = <0 0 0 0>;
2337 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2338 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
2339 clock-names = "pcie", "pcie_bus";
2340 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2341 resets = <&cpg 319>;
2342 status = "disabled";
2343 };
2345 pciec1: pcie@ee800000 {
2346 compatible = "renesas,pcie-r8a774a1",
2347 "renesas,pcie-rcar-gen3";
2348 reg = <0 0xee800000 0 0x80000>;
2349 #address-cells = <3>;
2350 #size-cells = <2>;
2351 bus-range = <0x00 0xff>;
2352 device_type = "pci";
2353 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2354 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2355 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2356 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2357 /* Map all possible DDR as inbound ranges */
2358 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2359 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2360 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2361 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2362 #interrupt-cells = <1>;
2363 interrupt-map-mask = <0 0 0 0>;
2364 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2365 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
2366 clock-names = "pcie", "pcie_bus";
2367 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2368 resets = <&cpg 318>;
2369 status = "disabled";
2370 };
2372 fdp1@fe940000 {
2373 compatible = "renesas,fdp1";
2374 reg = <0 0xfe940000 0 0x2400>;
2375 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
2376 clocks = <&cpg CPG_MOD 119>;
2377 power-domains = <&sysc R8A774A1_PD_A3VC>;
2378 resets = <&cpg 119>;
2379 renesas,fcp = <&fcpf0>;
2380 };
2382 fcpf0: fcp@fe950000 {
2383 compatible = "renesas,fcpf";
2384 reg = <0 0xfe950000 0 0x200>;
2385 clocks = <&cpg CPG_MOD 615>;
2386 power-domains = <&sysc R8A774A1_PD_A3VC>;
2387 resets = <&cpg 615>;
2388 };
2390 fcpvb0: fcp@fe96f000 {
2391 compatible = "renesas,fcpv";
2392 reg = <0 0xfe96f000 0 0x200>;
2393 clocks = <&cpg CPG_MOD 607>;
2394 power-domains = <&sysc R8A774A1_PD_A3VC>;
2395 resets = <&cpg 607>;
2396 };
2398 fcpvd0: fcp@fea27000 {
2399 compatible = "renesas,fcpv";
2400 reg = <0 0xfea27000 0 0x200>;
2401 clocks = <&cpg CPG_MOD 603>;
2402 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2403 resets = <&cpg 603>;
2404 iommus = <&ipmmu_vi0 8>;
2405 };
2407 fcpvd1: fcp@fea2f000 {
2408 compatible = "renesas,fcpv";
2409 reg = <0 0xfea2f000 0 0x200>;
2410 clocks = <&cpg CPG_MOD 602>;
2411 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2412 resets = <&cpg 602>;
2413 iommus = <&ipmmu_vi0 9>;
2414 };
2416 fcpvd2: fcp@fea37000 {
2417 compatible = "renesas,fcpv";
2418 reg = <0 0xfea37000 0 0x200>;
2419 clocks = <&cpg CPG_MOD 601>;
2420 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2421 resets = <&cpg 601>;
2422 iommus = <&ipmmu_vi0 10>;
2423 };
2425 fcpvi0: fcp@fe9af000 {
2426 compatible = "renesas,fcpv";
2427 reg = <0 0xfe9af000 0 0x200>;
2428 clocks = <&cpg CPG_MOD 611>;
2429 power-domains = <&sysc R8A774A1_PD_A3VC>;
2430 resets = <&cpg 611>;
2431 iommus = <&ipmmu_vc0 19>;
2432 };
2434 vspb: vsp@fe960000 {
2435 compatible = "renesas,vsp2";
2436 reg = <0 0xfe960000 0 0x8000>;
2437 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
2438 clocks = <&cpg CPG_MOD 626>;
2439 power-domains = <&sysc R8A774A1_PD_A3VC>;
2440 resets = <&cpg 626>;
2442 renesas,fcp = <&fcpvb0>;
2443 };
2445 vspd0: vsp@fea20000 {
2446 compatible = "renesas,vsp2";
2447 reg = <0 0xfea20000 0 0x5000>;
2448 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
2449 clocks = <&cpg CPG_MOD 623>;
2450 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2451 resets = <&cpg 623>;
2453 renesas,fcp = <&fcpvd0>;
2454 };
2456 vspd1: vsp@fea28000 {
2457 compatible = "renesas,vsp2";
2458 reg = <0 0xfea28000 0 0x5000>;
2459 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
2460 clocks = <&cpg CPG_MOD 622>;
2461 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2462 resets = <&cpg 622>;
2464 renesas,fcp = <&fcpvd1>;
2465 };
2467 vspd2: vsp@fea30000 {
2468 compatible = "renesas,vsp2";
2469 reg = <0 0xfea30000 0 0x5000>;
2470 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
2471 clocks = <&cpg CPG_MOD 621>;
2472 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2473 resets = <&cpg 621>;
2475 renesas,fcp = <&fcpvd2>;
2476 };
2478 vspi0: vsp@fe9a0000 {
2479 compatible = "renesas,vsp2";
2480 reg = <0 0xfe9a0000 0 0x8000>;
2481 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
2482 clocks = <&cpg CPG_MOD 631>;
2483 power-domains = <&sysc R8A774A1_PD_A3VC>;
2484 resets = <&cpg 631>;
2486 renesas,fcp = <&fcpvi0>;
2487 };
2489 csi20: csi2@fea80000 {
2490 compatible = "renesas,r8a774a1-csi2";
2491 reg = <0 0xfea80000 0 0x10000>;
2492 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
2493 clocks = <&cpg CPG_MOD 714>;
2494 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2495 resets = <&cpg 714>;
2496 status = "disabled";
2498 ports {
2499 #address-cells = <1>;
2500 #size-cells = <0>;
2502 port@1 {
2503 #address-cells = <1>;
2504 #size-cells = <0>;
2506 reg = <1>;
2508 csi20vin0: endpoint@0 {
2509 reg = <0>;
2510 remote-endpoint = <&vin0csi20>;
2511 };
2512 csi20vin1: endpoint@1 {
2513 reg = <1>;
2514 remote-endpoint = <&vin1csi20>;
2515 };
2516 csi20vin2: endpoint@2 {
2517 reg = <2>;
2518 remote-endpoint = <&vin2csi20>;
2519 };
2520 csi20vin3: endpoint@3 {
2521 reg = <3>;
2522 remote-endpoint = <&vin3csi20>;
2523 };
2524 csi20vin4: endpoint@4 {
2525 reg = <4>;
2526 remote-endpoint = <&vin4csi20>;
2527 };
2528 csi20vin5: endpoint@5 {
2529 reg = <5>;
2530 remote-endpoint = <&vin5csi20>;
2531 };
2532 csi20vin6: endpoint@6 {
2533 reg = <6>;
2534 remote-endpoint = <&vin6csi20>;
2535 };
2536 csi20vin7: endpoint@7 {
2537 reg = <7>;
2538 remote-endpoint = <&vin7csi20>;
2539 };
2540 };
2541 };
2542 };
2544 csi40: csi2@feaa0000 {
2545 compatible = "renesas,r8a774a1-csi2";
2546 reg = <0 0xfeaa0000 0 0x10000>;
2547 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
2548 clocks = <&cpg CPG_MOD 716>;
2549 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2550 resets = <&cpg 716>;
2551 status = "disabled";
2553 ports {
2554 #address-cells = <1>;
2555 #size-cells = <0>;
2557 port@1 {
2558 #address-cells = <1>;
2559 #size-cells = <0>;
2561 reg = <1>;
2563 csi40vin0: endpoint@0 {
2564 reg = <0>;
2565 remote-endpoint = <&vin0csi40>;
2566 };
2567 csi40vin1: endpoint@1 {
2568 reg = <1>;
2569 remote-endpoint = <&vin1csi40>;
2570 };
2571 csi40vin2: endpoint@2 {
2572 reg = <2>;
2573 remote-endpoint = <&vin2csi40>;
2574 };
2575 csi40vin3: endpoint@3 {
2576 reg = <3>;
2577 remote-endpoint = <&vin3csi40>;
2578 };
2579 csi40vin4: endpoint@4 {
2580 reg = <4>;
2581 remote-endpoint = <&vin4csi40>;
2582 };
2583 csi40vin5: endpoint@5 {
2584 reg = <5>;
2585 remote-endpoint = <&vin5csi40>;
2586 };
2587 csi40vin6: endpoint@6 {
2588 reg = <6>;
2589 remote-endpoint = <&vin6csi40>;
2590 };
2591 csi40vin7: endpoint@7 {
2592 reg = <7>;
2593 remote-endpoint = <&vin7csi40>;
2594 };
2595 };
2597 };
2598 };
2600 hdmi0: hdmi@fead0000 {
2601 compatible = "renesas,r8a774a1-hdmi",
2602 "renesas,rcar-gen3-hdmi";
2603 reg = <0 0xfead0000 0 0x10000>;
2604 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
2605 clocks = <&cpg CPG_MOD 729>,
2606 <&cpg CPG_CORE R8A774A1_CLK_HDMI>;
2607 clock-names = "iahb", "isfr";
2608 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2609 resets = <&cpg 729>;
2610 status = "disabled";
2612 ports {
2613 #address-cells = <1>;
2614 #size-cells = <0>;
2615 port@0 {
2616 reg = <0>;
2617 dw_hdmi0_in: endpoint {
2618 remote-endpoint = <&du_out_hdmi0>;
2619 };
2620 };
2621 port@1 {
2622 reg = <1>;
2623 };
2624 port@2 {
2625 /* HDMI sound */
2626 reg = <2>;
2627 };
2628 };
2629 };
2631 du: display@feb00000 {
2632 compatible = "renesas,du-r8a774a1";
2633 reg = <0 0xfeb00000 0 0x70000>;
2634 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2635 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2636 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
2637 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
2638 <&cpg CPG_MOD 722>;
2639 clock-names = "du.0", "du.1", "du.2";
2640 resets = <&cpg 724>, <&cpg 722>;
2641 reset-names = "du.0", "du.2";
2642 status = "disabled";
2644 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
2646 ports {
2647 #address-cells = <1>;
2648 #size-cells = <0>;
2650 port@0 {
2651 reg = <0>;
2652 du_out_rgb: endpoint {
2653 };
2654 };
2655 port@1 {
2656 reg = <1>;
2657 du_out_hdmi0: endpoint {
2658 remote-endpoint = <&dw_hdmi0_in>;
2659 };
2660 };
2661 port@2 {
2662 reg = <2>;
2663 du_out_lvds0: endpoint {
2664 remote-endpoint = <&lvds0_in>;
2665 };
2666 };
2667 };
2668 };
2670 lvds0: lvds@feb90000 {
2671 compatible = "renesas,r8a774a1-lvds";
2672 reg = <0 0xfeb90000 0 0x14>;
2673 clocks = <&cpg CPG_MOD 727>;
2674 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2675 resets = <&cpg 727>;
2676 status = "disabled";
2678 ports {
2679 #address-cells = <1>;
2680 #size-cells = <0>;
2682 port@0 {
2683 reg = <0>;
2684 lvds0_in: endpoint {
2685 remote-endpoint = <&du_out_lvds0>;
2686 };
2687 };
2688 port@1 {
2689 reg = <1>;
2690 lvds0_out: endpoint {
2691 };
2692 };
2693 };
2694 };
2696 prr: chipid@fff00044 {
2697 compatible = "renesas,prr";
2698 reg = <0 0xfff00044 0 4>;
2699 };
2700 };
2702 thermal-zones {
2703 sensor_thermal1: sensor-thermal1 {
2704 polling-delay-passive = <250>;
2705 polling-delay = <1000>;
2706 thermal-sensors = <&tsc 0>;
2707 sustainable-power = <3874>;
2709 trips {
2710 sensor1_crit: sensor1-crit {
2711 temperature = <120000>;
2712 hysteresis = <1000>;
2713 type = "critical";
2714 };
2715 };
2716 };
2718 sensor_thermal2: sensor-thermal2 {
2719 polling-delay-passive = <250>;
2720 polling-delay = <1000>;
2721 thermal-sensors = <&tsc 1>;
2722 sustainable-power = <3874>;
2724 trips {
2725 sensor2_crit: sensor2-crit {
2726 temperature = <120000>;
2727 hysteresis = <1000>;
2728 type = "critical";
2729 };
2730 };
2731 };
2733 sensor_thermal3: sensor-thermal3 {
2734 polling-delay-passive = <250>;
2735 polling-delay = <1000>;
2736 thermal-sensors = <&tsc 2>;
2737 sustainable-power = <3874>;
2739 cooling-maps {
2740 map0 {
2741 trip = <&target>;
2742 cooling-device = <&a57_0 0 2>;
2743 contribution = <1024>;
2744 };
2745 map1 {
2746 trip = <&target>;
2747 cooling-device = <&a53_0 0 2>;
2748 contribution = <1024>;
2749 };
2750 };
2751 trips {
2752 target: trip-point1 {
2753 temperature = <100000>;
2754 hysteresis = <1000>;
2755 type = "passive";
2756 };
2758 sensor3_crit: sensor3-crit {
2759 temperature = <120000>;
2760 hysteresis = <1000>;
2761 type = "critical";
2762 };
2763 };
2764 };
2765 };
2767 timer {
2768 compatible = "arm,armv8-timer";
2769 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
2770 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
2771 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
2772 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
2773 };
2775 /* External USB clocks - can be overridden by the board */
2776 usb3s0_clk: usb3s0 {
2777 compatible = "fixed-clock";
2778 #clock-cells = <0>;
2779 clock-frequency = <0>;
2780 };
2782 usb_extal_clk: usb_extal {
2783 compatible = "fixed-clock";
2784 #clock-cells = <0>;
2785 clock-frequency = <0>;
2786 };
2787 };