| blob | 1ebb0eef42dae4159ec188406f5392b7857dfacf |
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
4 */
6 #include <dt-bindings/clock/rk3368-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/soc/rockchip,boot-mode.h>
12 #include <dt-bindings/thermal/thermal.h>
14 / {
15 compatible = "rockchip,rk3368";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
20 aliases {
21 ethernet0 = &gmac;
22 i2c0 = &i2c0;
23 i2c1 = &i2c1;
24 i2c2 = &i2c2;
25 i2c3 = &i2c3;
26 i2c4 = &i2c4;
27 i2c5 = &i2c5;
28 serial0 = &uart0;
29 serial1 = &uart1;
30 serial2 = &uart2;
31 serial3 = &uart3;
32 serial4 = &uart4;
33 spi0 = &spi0;
34 spi1 = &spi1;
35 spi2 = &spi2;
36 };
38 cpus {
39 #address-cells = <0x2>;
40 #size-cells = <0x0>;
42 cpu-map {
43 cluster0 {
44 core0 {
45 cpu = <&cpu_b0>;
46 };
47 core1 {
48 cpu = <&cpu_b1>;
49 };
50 core2 {
51 cpu = <&cpu_b2>;
52 };
53 core3 {
54 cpu = <&cpu_b3>;
55 };
56 };
58 cluster1 {
59 core0 {
60 cpu = <&cpu_l0>;
61 };
62 core1 {
63 cpu = <&cpu_l1>;
64 };
65 core2 {
66 cpu = <&cpu_l2>;
67 };
68 core3 {
69 cpu = <&cpu_l3>;
70 };
71 };
72 };
74 cpu_l0: cpu@0 {
75 device_type = "cpu";
76 compatible = "arm,cortex-a53";
77 reg = <0x0 0x0>;
78 enable-method = "psci";
79 #cooling-cells = <2>; /* min followed by max */
80 };
82 cpu_l1: cpu@1 {
83 device_type = "cpu";
84 compatible = "arm,cortex-a53";
85 reg = <0x0 0x1>;
86 enable-method = "psci";
87 #cooling-cells = <2>; /* min followed by max */
88 };
90 cpu_l2: cpu@2 {
91 device_type = "cpu";
92 compatible = "arm,cortex-a53";
93 reg = <0x0 0x2>;
94 enable-method = "psci";
95 #cooling-cells = <2>; /* min followed by max */
96 };
98 cpu_l3: cpu@3 {
99 device_type = "cpu";
100 compatible = "arm,cortex-a53";
101 reg = <0x0 0x3>;
102 enable-method = "psci";
103 #cooling-cells = <2>; /* min followed by max */
104 };
106 cpu_b0: cpu@100 {
107 device_type = "cpu";
108 compatible = "arm,cortex-a53";
109 reg = <0x0 0x100>;
110 enable-method = "psci";
111 #cooling-cells = <2>; /* min followed by max */
112 };
114 cpu_b1: cpu@101 {
115 device_type = "cpu";
116 compatible = "arm,cortex-a53";
117 reg = <0x0 0x101>;
118 enable-method = "psci";
119 #cooling-cells = <2>; /* min followed by max */
120 };
122 cpu_b2: cpu@102 {
123 device_type = "cpu";
124 compatible = "arm,cortex-a53";
125 reg = <0x0 0x102>;
126 enable-method = "psci";
127 #cooling-cells = <2>; /* min followed by max */
128 };
130 cpu_b3: cpu@103 {
131 device_type = "cpu";
132 compatible = "arm,cortex-a53";
133 reg = <0x0 0x103>;
134 enable-method = "psci";
135 #cooling-cells = <2>; /* min followed by max */
136 };
137 };
139 amba: bus {
140 compatible = "simple-bus";
141 #address-cells = <2>;
142 #size-cells = <2>;
143 ranges;
145 dmac_peri: dma-controller@ff250000 {
146 compatible = "arm,pl330", "arm,primecell";
147 reg = <0x0 0xff250000 0x0 0x4000>;
148 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
150 #dma-cells = <1>;
151 arm,pl330-broken-no-flushp;
152 clocks = <&cru ACLK_DMAC_PERI>;
153 clock-names = "apb_pclk";
154 };
156 dmac_bus: dma-controller@ff600000 {
157 compatible = "arm,pl330", "arm,primecell";
158 reg = <0x0 0xff600000 0x0 0x4000>;
159 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
161 #dma-cells = <1>;
162 arm,pl330-broken-no-flushp;
163 clocks = <&cru ACLK_DMAC_BUS>;
164 clock-names = "apb_pclk";
165 };
166 };
168 arm-pmu {
169 compatible = "arm,armv8-pmuv3";
170 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
171 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
174 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
178 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
179 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
180 <&cpu_b2>, <&cpu_b3>;
181 };
183 psci {
184 compatible = "arm,psci-0.2";
185 method = "smc";
186 };
188 timer {
189 compatible = "arm,armv8-timer";
190 interrupts = <GIC_PPI 13
191 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
192 <GIC_PPI 14
193 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
194 <GIC_PPI 11
195 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
196 <GIC_PPI 10
197 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
198 };
200 xin24m: oscillator {
201 compatible = "fixed-clock";
202 clock-frequency = <24000000>;
203 clock-output-names = "xin24m";
204 #clock-cells = <0>;
205 };
207 sdmmc: mmc@ff0c0000 {
208 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
209 reg = <0x0 0xff0c0000 0x0 0x4000>;
210 max-frequency = <150000000>;
211 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
212 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
213 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
214 fifo-depth = <0x100>;
215 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
216 resets = <&cru SRST_MMC0>;
217 reset-names = "reset";
218 status = "disabled";
219 };
221 sdio0: mmc@ff0d0000 {
222 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
223 reg = <0x0 0xff0d0000 0x0 0x4000>;
224 max-frequency = <150000000>;
225 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
226 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
227 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
228 fifo-depth = <0x100>;
229 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
230 resets = <&cru SRST_SDIO0>;
231 reset-names = "reset";
232 status = "disabled";
233 };
235 emmc: mmc@ff0f0000 {
236 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
237 reg = <0x0 0xff0f0000 0x0 0x4000>;
238 max-frequency = <150000000>;
239 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
240 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
241 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
242 fifo-depth = <0x100>;
243 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
244 resets = <&cru SRST_EMMC>;
245 reset-names = "reset";
246 status = "disabled";
247 };
249 saradc: saradc@ff100000 {
250 compatible = "rockchip,saradc";
251 reg = <0x0 0xff100000 0x0 0x100>;
252 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
253 #io-channel-cells = <1>;
254 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
255 clock-names = "saradc", "apb_pclk";
256 resets = <&cru SRST_SARADC>;
257 reset-names = "saradc-apb";
258 status = "disabled";
259 };
261 spi0: spi@ff110000 {
262 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
263 reg = <0x0 0xff110000 0x0 0x1000>;
264 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
265 clock-names = "spiclk", "apb_pclk";
266 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
267 pinctrl-names = "default";
268 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
269 #address-cells = <1>;
270 #size-cells = <0>;
271 status = "disabled";
272 };
274 spi1: spi@ff120000 {
275 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
276 reg = <0x0 0xff120000 0x0 0x1000>;
277 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
278 clock-names = "spiclk", "apb_pclk";
279 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
280 pinctrl-names = "default";
281 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
282 #address-cells = <1>;
283 #size-cells = <0>;
284 status = "disabled";
285 };
287 spi2: spi@ff130000 {
288 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
289 reg = <0x0 0xff130000 0x0 0x1000>;
290 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
291 clock-names = "spiclk", "apb_pclk";
292 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
293 pinctrl-names = "default";
294 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
295 #address-cells = <1>;
296 #size-cells = <0>;
297 status = "disabled";
298 };
300 i2c2: i2c@ff140000 {
301 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
302 reg = <0x0 0xff140000 0x0 0x1000>;
303 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
304 #address-cells = <1>;
305 #size-cells = <0>;
306 clock-names = "i2c";
307 clocks = <&cru PCLK_I2C2>;
308 pinctrl-names = "default";
309 pinctrl-0 = <&i2c2_xfer>;
310 status = "disabled";
311 };
313 i2c3: i2c@ff150000 {
314 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
315 reg = <0x0 0xff150000 0x0 0x1000>;
316 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
317 #address-cells = <1>;
318 #size-cells = <0>;
319 clock-names = "i2c";
320 clocks = <&cru PCLK_I2C3>;
321 pinctrl-names = "default";
322 pinctrl-0 = <&i2c3_xfer>;
323 status = "disabled";
324 };
326 i2c4: i2c@ff160000 {
327 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
328 reg = <0x0 0xff160000 0x0 0x1000>;
329 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
330 #address-cells = <1>;
331 #size-cells = <0>;
332 clock-names = "i2c";
333 clocks = <&cru PCLK_I2C4>;
334 pinctrl-names = "default";
335 pinctrl-0 = <&i2c4_xfer>;
336 status = "disabled";
337 };
339 i2c5: i2c@ff170000 {
340 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
341 reg = <0x0 0xff170000 0x0 0x1000>;
342 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
343 #address-cells = <1>;
344 #size-cells = <0>;
345 clock-names = "i2c";
346 clocks = <&cru PCLK_I2C5>;
347 pinctrl-names = "default";
348 pinctrl-0 = <&i2c5_xfer>;
349 status = "disabled";
350 };
352 uart0: serial@ff180000 {
353 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
354 reg = <0x0 0xff180000 0x0 0x100>;
355 clock-frequency = <24000000>;
356 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
357 clock-names = "baudclk", "apb_pclk";
358 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
359 reg-shift = <2>;
360 reg-io-width = <4>;
361 status = "disabled";
362 };
364 uart1: serial@ff190000 {
365 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
366 reg = <0x0 0xff190000 0x0 0x100>;
367 clock-frequency = <24000000>;
368 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
369 clock-names = "baudclk", "apb_pclk";
370 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
371 reg-shift = <2>;
372 reg-io-width = <4>;
373 status = "disabled";
374 };
376 uart3: serial@ff1b0000 {
377 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
378 reg = <0x0 0xff1b0000 0x0 0x100>;
379 clock-frequency = <24000000>;
380 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
381 clock-names = "baudclk", "apb_pclk";
382 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
383 reg-shift = <2>;
384 reg-io-width = <4>;
385 status = "disabled";
386 };
388 uart4: serial@ff1c0000 {
389 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
390 reg = <0x0 0xff1c0000 0x0 0x100>;
391 clock-frequency = <24000000>;
392 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
393 clock-names = "baudclk", "apb_pclk";
394 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
395 reg-shift = <2>;
396 reg-io-width = <4>;
397 status = "disabled";
398 };
400 thermal-zones {
401 cpu {
402 polling-delay-passive = <100>; /* milliseconds */
403 polling-delay = <5000>; /* milliseconds */
405 thermal-sensors = <&tsadc 0>;
407 trips {
408 cpu_alert0: cpu_alert0 {
409 temperature = <75000>; /* millicelsius */
410 hysteresis = <2000>; /* millicelsius */
411 type = "passive";
412 };
413 cpu_alert1: cpu_alert1 {
414 temperature = <80000>; /* millicelsius */
415 hysteresis = <2000>; /* millicelsius */
416 type = "passive";
417 };
418 cpu_crit: cpu_crit {
419 temperature = <95000>; /* millicelsius */
420 hysteresis = <2000>; /* millicelsius */
421 type = "critical";
422 };
423 };
425 cooling-maps {
426 map0 {
427 trip = <&cpu_alert0>;
428 cooling-device =
429 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
430 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
431 <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
432 <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
433 };
434 map1 {
435 trip = <&cpu_alert1>;
436 cooling-device =
437 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
438 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
439 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
440 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
441 };
442 };
443 };
445 gpu {
446 polling-delay-passive = <100>; /* milliseconds */
447 polling-delay = <5000>; /* milliseconds */
449 thermal-sensors = <&tsadc 1>;
451 trips {
452 gpu_alert0: gpu_alert0 {
453 temperature = <80000>; /* millicelsius */
454 hysteresis = <2000>; /* millicelsius */
455 type = "passive";
456 };
457 gpu_crit: gpu_crit {
458 temperature = <115000>; /* millicelsius */
459 hysteresis = <2000>; /* millicelsius */
460 type = "critical";
461 };
462 };
464 cooling-maps {
465 map0 {
466 trip = <&gpu_alert0>;
467 cooling-device =
468 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
469 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
470 <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
471 <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
472 };
473 };
474 };
475 };
477 tsadc: tsadc@ff280000 {
478 compatible = "rockchip,rk3368-tsadc";
479 reg = <0x0 0xff280000 0x0 0x100>;
480 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
481 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
482 clock-names = "tsadc", "apb_pclk";
483 resets = <&cru SRST_TSADC>;
484 reset-names = "tsadc-apb";
485 pinctrl-names = "init", "default", "sleep";
486 pinctrl-0 = <&otp_gpio>;
487 pinctrl-1 = <&otp_out>;
488 pinctrl-2 = <&otp_gpio>;
489 #thermal-sensor-cells = <1>;
490 rockchip,hw-tshut-temp = <95000>;
491 status = "disabled";
492 };
494 gmac: ethernet@ff290000 {
495 compatible = "rockchip,rk3368-gmac";
496 reg = <0x0 0xff290000 0x0 0x10000>;
497 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
498 interrupt-names = "macirq";
499 rockchip,grf = <&grf>;
500 clocks = <&cru SCLK_MAC>,
501 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
502 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
503 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
504 clock-names = "stmmaceth",
505 "mac_clk_rx", "mac_clk_tx",
506 "clk_mac_ref", "clk_mac_refout",
507 "aclk_mac", "pclk_mac";
508 status = "disabled";
509 };
511 usb_host0_ehci: usb@ff500000 {
512 compatible = "generic-ehci";
513 reg = <0x0 0xff500000 0x0 0x100>;
514 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
515 clocks = <&cru HCLK_HOST0>;
516 status = "disabled";
517 };
519 usb_otg: usb@ff580000 {
520 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
521 "snps,dwc2";
522 reg = <0x0 0xff580000 0x0 0x40000>;
523 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
524 clocks = <&cru HCLK_OTG0>;
525 clock-names = "otg";
526 dr_mode = "otg";
527 g-np-tx-fifo-size = <16>;
528 g-rx-fifo-size = <275>;
529 g-tx-fifo-size = <256 128 128 64 64 32>;
530 status = "disabled";
531 };
533 i2c0: i2c@ff650000 {
534 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
535 reg = <0x0 0xff650000 0x0 0x1000>;
536 clocks = <&cru PCLK_I2C0>;
537 clock-names = "i2c";
538 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
539 pinctrl-names = "default";
540 pinctrl-0 = <&i2c0_xfer>;
541 #address-cells = <1>;
542 #size-cells = <0>;
543 status = "disabled";
544 };
546 i2c1: i2c@ff660000 {
547 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
548 reg = <0x0 0xff660000 0x0 0x1000>;
549 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
550 #address-cells = <1>;
551 #size-cells = <0>;
552 clock-names = "i2c";
553 clocks = <&cru PCLK_I2C1>;
554 pinctrl-names = "default";
555 pinctrl-0 = <&i2c1_xfer>;
556 status = "disabled";
557 };
559 pwm0: pwm@ff680000 {
560 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
561 reg = <0x0 0xff680000 0x0 0x10>;
562 #pwm-cells = <3>;
563 pinctrl-names = "default";
564 pinctrl-0 = <&pwm0_pin>;
565 clocks = <&cru PCLK_PWM1>;
566 clock-names = "pwm";
567 status = "disabled";
568 };
570 pwm1: pwm@ff680010 {
571 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
572 reg = <0x0 0xff680010 0x0 0x10>;
573 #pwm-cells = <3>;
574 pinctrl-names = "default";
575 pinctrl-0 = <&pwm1_pin>;
576 clocks = <&cru PCLK_PWM1>;
577 clock-names = "pwm";
578 status = "disabled";
579 };
581 pwm2: pwm@ff680020 {
582 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
583 reg = <0x0 0xff680020 0x0 0x10>;
584 #pwm-cells = <3>;
585 clocks = <&cru PCLK_PWM1>;
586 clock-names = "pwm";
587 status = "disabled";
588 };
590 pwm3: pwm@ff680030 {
591 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
592 reg = <0x0 0xff680030 0x0 0x10>;
593 #pwm-cells = <3>;
594 pinctrl-names = "default";
595 pinctrl-0 = <&pwm3_pin>;
596 clocks = <&cru PCLK_PWM1>;
597 clock-names = "pwm";
598 status = "disabled";
599 };
601 uart2: serial@ff690000 {
602 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
603 reg = <0x0 0xff690000 0x0 0x100>;
604 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
605 clock-names = "baudclk", "apb_pclk";
606 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
607 pinctrl-names = "default";
608 pinctrl-0 = <&uart2_xfer>;
609 reg-shift = <2>;
610 reg-io-width = <4>;
611 status = "disabled";
612 };
614 mbox: mbox@ff6b0000 {
615 compatible = "rockchip,rk3368-mailbox";
616 reg = <0x0 0xff6b0000 0x0 0x1000>;
617 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
618 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
619 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
620 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
621 clocks = <&cru PCLK_MAILBOX>;
622 clock-names = "pclk_mailbox";
623 #mbox-cells = <1>;
624 status = "disabled";
625 };
627 pmugrf: syscon@ff738000 {
628 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
629 reg = <0x0 0xff738000 0x0 0x1000>;
631 pmu_io_domains: io-domains {
632 compatible = "rockchip,rk3368-pmu-io-voltage-domain";
633 status = "disabled";
634 };
636 reboot-mode {
637 compatible = "syscon-reboot-mode";
638 offset = <0x200>;
639 mode-normal = <BOOT_NORMAL>;
640 mode-recovery = <BOOT_RECOVERY>;
641 mode-bootloader = <BOOT_FASTBOOT>;
642 mode-loader = <BOOT_BL_DOWNLOAD>;
643 };
644 };
646 cru: clock-controller@ff760000 {
647 compatible = "rockchip,rk3368-cru";
648 reg = <0x0 0xff760000 0x0 0x1000>;
649 rockchip,grf = <&grf>;
650 #clock-cells = <1>;
651 #reset-cells = <1>;
652 };
654 grf: syscon@ff770000 {
655 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
656 reg = <0x0 0xff770000 0x0 0x1000>;
658 io_domains: io-domains {
659 compatible = "rockchip,rk3368-io-voltage-domain";
660 status = "disabled";
661 };
662 };
664 wdt: watchdog@ff800000 {
665 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
666 reg = <0x0 0xff800000 0x0 0x100>;
667 clocks = <&cru PCLK_WDT>;
668 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
669 status = "disabled";
670 };
672 timer@ff810000 {
673 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
674 reg = <0x0 0xff810000 0x0 0x20>;
675 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
676 };
678 spdif: spdif@ff880000 {
679 compatible = "rockchip,rk3368-spdif";
680 reg = <0x0 0xff880000 0x0 0x1000>;
681 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
682 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
683 clock-names = "mclk", "hclk";
684 dmas = <&dmac_bus 3>;
685 dma-names = "tx";
686 pinctrl-names = "default";
687 pinctrl-0 = <&spdif_tx>;
688 status = "disabled";
689 };
691 i2s_2ch: i2s-2ch@ff890000 {
692 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
693 reg = <0x0 0xff890000 0x0 0x1000>;
694 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
695 clock-names = "i2s_clk", "i2s_hclk";
696 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
697 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
698 dma-names = "tx", "rx";
699 status = "disabled";
700 };
702 i2s_8ch: i2s-8ch@ff898000 {
703 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
704 reg = <0x0 0xff898000 0x0 0x1000>;
705 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
706 clock-names = "i2s_clk", "i2s_hclk";
707 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
708 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
709 dma-names = "tx", "rx";
710 pinctrl-names = "default";
711 pinctrl-0 = <&i2s_8ch_bus>;
712 status = "disabled";
713 };
715 iep_mmu: iommu@ff900800 {
716 compatible = "rockchip,iommu";
717 reg = <0x0 0xff900800 0x0 0x100>;
718 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
719 interrupt-names = "iep_mmu";
720 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
721 clock-names = "aclk", "iface";
722 #iommu-cells = <0>;
723 status = "disabled";
724 };
726 isp_mmu: iommu@ff914000 {
727 compatible = "rockchip,iommu";
728 reg = <0x0 0xff914000 0x0 0x100>,
729 <0x0 0xff915000 0x0 0x100>;
730 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
731 interrupt-names = "isp_mmu";
732 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
733 clock-names = "aclk", "iface";
734 #iommu-cells = <0>;
735 rockchip,disable-mmu-reset;
736 status = "disabled";
737 };
739 vop_mmu: iommu@ff930300 {
740 compatible = "rockchip,iommu";
741 reg = <0x0 0xff930300 0x0 0x100>;
742 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
743 interrupt-names = "vop_mmu";
744 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
745 clock-names = "aclk", "iface";
746 #iommu-cells = <0>;
747 status = "disabled";
748 };
750 hevc_mmu: iommu@ff9a0440 {
751 compatible = "rockchip,iommu";
752 reg = <0x0 0xff9a0440 0x0 0x40>,
753 <0x0 0xff9a0480 0x0 0x40>;
754 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
755 interrupt-names = "hevc_mmu";
756 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
757 clock-names = "aclk", "iface";
758 #iommu-cells = <0>;
759 status = "disabled";
760 };
762 vpu_mmu: iommu@ff9a0800 {
763 compatible = "rockchip,iommu";
764 reg = <0x0 0xff9a0800 0x0 0x100>;
765 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
766 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
767 interrupt-names = "vepu_mmu", "vdpu_mmu";
768 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
769 clock-names = "aclk", "iface";
770 #iommu-cells = <0>;
771 status = "disabled";
772 };
774 efuse256: efuse@ffb00000 {
775 compatible = "rockchip,rk3368-efuse";
776 reg = <0x0 0xffb00000 0x0 0x20>;
777 #address-cells = <1>;
778 #size-cells = <1>;
779 clocks = <&cru PCLK_EFUSE256>;
780 clock-names = "pclk_efuse";
782 cpu_leakage: cpu-leakage@17 {
783 reg = <0x17 0x1>;
784 };
785 temp_adjust: temp-adjust@1f {
786 reg = <0x1f 0x1>;
787 };
788 };
790 gic: interrupt-controller@ffb71000 {
791 compatible = "arm,gic-400";
792 interrupt-controller;
793 #interrupt-cells = <3>;
794 #address-cells = <0>;
796 reg = <0x0 0xffb71000 0x0 0x1000>,
797 <0x0 0xffb72000 0x0 0x2000>,
798 <0x0 0xffb74000 0x0 0x2000>,
799 <0x0 0xffb76000 0x0 0x2000>;
800 interrupts = <GIC_PPI 9
801 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
802 };
804 pinctrl: pinctrl {
805 compatible = "rockchip,rk3368-pinctrl";
806 rockchip,grf = <&grf>;
807 rockchip,pmu = <&pmugrf>;
808 #address-cells = <0x2>;
809 #size-cells = <0x2>;
810 ranges;
812 gpio0: gpio0@ff750000 {
813 compatible = "rockchip,gpio-bank";
814 reg = <0x0 0xff750000 0x0 0x100>;
815 clocks = <&cru PCLK_GPIO0>;
816 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
818 gpio-controller;
819 #gpio-cells = <0x2>;
821 interrupt-controller;
822 #interrupt-cells = <0x2>;
823 };
825 gpio1: gpio1@ff780000 {
826 compatible = "rockchip,gpio-bank";
827 reg = <0x0 0xff780000 0x0 0x100>;
828 clocks = <&cru PCLK_GPIO1>;
829 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
831 gpio-controller;
832 #gpio-cells = <0x2>;
834 interrupt-controller;
835 #interrupt-cells = <0x2>;
836 };
838 gpio2: gpio2@ff790000 {
839 compatible = "rockchip,gpio-bank";
840 reg = <0x0 0xff790000 0x0 0x100>;
841 clocks = <&cru PCLK_GPIO2>;
842 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
844 gpio-controller;
845 #gpio-cells = <0x2>;
847 interrupt-controller;
848 #interrupt-cells = <0x2>;
849 };
851 gpio3: gpio3@ff7a0000 {
852 compatible = "rockchip,gpio-bank";
853 reg = <0x0 0xff7a0000 0x0 0x100>;
854 clocks = <&cru PCLK_GPIO3>;
855 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
857 gpio-controller;
858 #gpio-cells = <0x2>;
860 interrupt-controller;
861 #interrupt-cells = <0x2>;
862 };
864 pcfg_pull_up: pcfg-pull-up {
865 bias-pull-up;
866 };
868 pcfg_pull_down: pcfg-pull-down {
869 bias-pull-down;
870 };
872 pcfg_pull_none: pcfg-pull-none {
873 bias-disable;
874 };
876 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
877 bias-disable;
878 drive-strength = <12>;
879 };
881 emmc {
882 emmc_clk: emmc-clk {
883 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
884 };
886 emmc_cmd: emmc-cmd {
887 rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>;
888 };
890 emmc_pwr: emmc-pwr {
891 rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>;
892 };
894 emmc_bus1: emmc-bus1 {
895 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>;
896 };
898 emmc_bus4: emmc-bus4 {
899 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
900 <1 RK_PC3 2 &pcfg_pull_up>,
901 <1 RK_PC4 2 &pcfg_pull_up>,
902 <1 RK_PC5 2 &pcfg_pull_up>;
903 };
905 emmc_bus8: emmc-bus8 {
906 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
907 <1 RK_PC3 2 &pcfg_pull_up>,
908 <1 RK_PC4 2 &pcfg_pull_up>,
909 <1 RK_PC5 2 &pcfg_pull_up>,
910 <1 RK_PC6 2 &pcfg_pull_up>,
911 <1 RK_PC7 2 &pcfg_pull_up>,
912 <1 RK_PD0 2 &pcfg_pull_up>,
913 <1 RK_PD1 2 &pcfg_pull_up>;
914 };
915 };
917 gmac {
918 rgmii_pins: rgmii-pins {
919 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>,
920 <3 RK_PD0 1 &pcfg_pull_none>,
921 <3 RK_PC3 1 &pcfg_pull_none>,
922 <3 RK_PB0 1 &pcfg_pull_none_12ma>,
923 <3 RK_PB1 1 &pcfg_pull_none_12ma>,
924 <3 RK_PB2 1 &pcfg_pull_none_12ma>,
925 <3 RK_PB6 1 &pcfg_pull_none_12ma>,
926 <3 RK_PD4 1 &pcfg_pull_none_12ma>,
927 <3 RK_PB5 1 &pcfg_pull_none_12ma>,
928 <3 RK_PB7 1 &pcfg_pull_none>,
929 <3 RK_PC0 1 &pcfg_pull_none>,
930 <3 RK_PC1 1 &pcfg_pull_none>,
931 <3 RK_PC2 1 &pcfg_pull_none>,
932 <3 RK_PD1 1 &pcfg_pull_none>,
933 <3 RK_PC4 1 &pcfg_pull_none>;
934 };
936 rmii_pins: rmii-pins {
937 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>,
938 <3 RK_PD0 1 &pcfg_pull_none>,
939 <3 RK_PC3 1 &pcfg_pull_none>,
940 <3 RK_PB0 1 &pcfg_pull_none_12ma>,
941 <3 RK_PB1 1 &pcfg_pull_none_12ma>,
942 <3 RK_PB5 1 &pcfg_pull_none_12ma>,
943 <3 RK_PB7 1 &pcfg_pull_none>,
944 <3 RK_PC0 1 &pcfg_pull_none>,
945 <3 RK_PC4 1 &pcfg_pull_none>,
946 <3 RK_PC5 1 &pcfg_pull_none>;
947 };
948 };
950 i2c0 {
951 i2c0_xfer: i2c0-xfer {
952 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
953 <0 RK_PA7 1 &pcfg_pull_none>;
954 };
955 };
957 i2c1 {
958 i2c1_xfer: i2c1-xfer {
959 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>,
960 <2 RK_PC6 1 &pcfg_pull_none>;
961 };
962 };
964 i2c2 {
965 i2c2_xfer: i2c2-xfer {
966 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_none>,
967 <3 RK_PD7 2 &pcfg_pull_none>;
968 };
969 };
971 i2c3 {
972 i2c3_xfer: i2c3-xfer {
973 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>,
974 <1 RK_PC1 1 &pcfg_pull_none>;
975 };
976 };
978 i2c4 {
979 i2c4_xfer: i2c4-xfer {
980 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>,
981 <3 RK_PD1 2 &pcfg_pull_none>;
982 };
983 };
985 i2c5 {
986 i2c5_xfer: i2c5-xfer {
987 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_none>,
988 <3 RK_PD3 2 &pcfg_pull_none>;
989 };
990 };
992 i2s {
993 i2s_8ch_bus: i2s-8ch-bus {
994 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>,
995 <2 RK_PB5 1 &pcfg_pull_none>,
996 <2 RK_PB6 1 &pcfg_pull_none>,
997 <2 RK_PB7 1 &pcfg_pull_none>,
998 <2 RK_PC0 1 &pcfg_pull_none>,
999 <2 RK_PC1 1 &pcfg_pull_none>,
1000 <2 RK_PC2 1 &pcfg_pull_none>,
1001 <2 RK_PC3 1 &pcfg_pull_none>,
1002 <2 RK_PC4 1 &pcfg_pull_none>;
1003 };
1004 };
1006 pwm0 {
1007 pwm0_pin: pwm0-pin {
1008 rockchip,pins = <3 RK_PB0 2 &pcfg_pull_none>;
1009 };
1010 };
1012 pwm1 {
1013 pwm1_pin: pwm1-pin {
1014 rockchip,pins = <0 RK_PB0 2 &pcfg_pull_none>;
1015 };
1016 };
1018 pwm3 {
1019 pwm3_pin: pwm3-pin {
1020 rockchip,pins = <3 RK_PD5 3 &pcfg_pull_none>;
1021 };
1022 };
1024 sdio0 {
1025 sdio0_bus1: sdio0-bus1 {
1026 rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>;
1027 };
1029 sdio0_bus4: sdio0-bus4 {
1030 rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>,
1031 <2 RK_PD5 1 &pcfg_pull_up>,
1032 <2 RK_PD6 1 &pcfg_pull_up>,
1033 <2 RK_PD7 1 &pcfg_pull_up>;
1034 };
1036 sdio0_cmd: sdio0-cmd {
1037 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_up>;
1038 };
1040 sdio0_clk: sdio0-clk {
1041 rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>;
1042 };
1044 sdio0_cd: sdio0-cd {
1045 rockchip,pins = <3 RK_PA2 1 &pcfg_pull_up>;
1046 };
1048 sdio0_wp: sdio0-wp {
1049 rockchip,pins = <3 RK_PA3 1 &pcfg_pull_up>;
1050 };
1052 sdio0_pwr: sdio0-pwr {
1053 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_up>;
1054 };
1056 sdio0_bkpwr: sdio0-bkpwr {
1057 rockchip,pins = <3 RK_PA5 1 &pcfg_pull_up>;
1058 };
1060 sdio0_int: sdio0-int {
1061 rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>;
1062 };
1063 };
1065 sdmmc {
1066 sdmmc_clk: sdmmc-clk {
1067 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>;
1068 };
1070 sdmmc_cmd: sdmmc-cmd {
1071 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
1072 };
1074 sdmmc_cd: sdmmc-cd {
1075 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
1076 };
1078 sdmmc_bus1: sdmmc-bus1 {
1079 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>;
1080 };
1082 sdmmc_bus4: sdmmc-bus4 {
1083 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>,
1084 <2 RK_PA6 1 &pcfg_pull_up>,
1085 <2 RK_PA7 1 &pcfg_pull_up>,
1086 <2 RK_PB0 1 &pcfg_pull_up>;
1087 };
1088 };
1090 spdif {
1091 spdif_tx: spdif-tx {
1092 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
1093 };
1094 };
1096 spi0 {
1097 spi0_clk: spi0-clk {
1098 rockchip,pins = <1 RK_PD5 2 &pcfg_pull_up>;
1099 };
1100 spi0_cs0: spi0-cs0 {
1101 rockchip,pins = <1 RK_PD0 3 &pcfg_pull_up>;
1102 };
1103 spi0_cs1: spi0-cs1 {
1104 rockchip,pins = <1 RK_PD1 3 &pcfg_pull_up>;
1105 };
1106 spi0_tx: spi0-tx {
1107 rockchip,pins = <1 RK_PC7 3 &pcfg_pull_up>;
1108 };
1109 spi0_rx: spi0-rx {
1110 rockchip,pins = <1 RK_PC6 3 &pcfg_pull_up>;
1111 };
1112 };
1114 spi1 {
1115 spi1_clk: spi1-clk {
1116 rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>;
1117 };
1118 spi1_cs0: spi1-cs0 {
1119 rockchip,pins = <1 RK_PB7 2 &pcfg_pull_up>;
1120 };
1121 spi1_cs1: spi1-cs1 {
1122 rockchip,pins = <3 RK_PD4 2 &pcfg_pull_up>;
1123 };
1124 spi1_rx: spi1-rx {
1125 rockchip,pins = <1 RK_PC0 2 &pcfg_pull_up>;
1126 };
1127 spi1_tx: spi1-tx {
1128 rockchip,pins = <1 RK_PC1 2 &pcfg_pull_up>;
1129 };
1130 };
1132 spi2 {
1133 spi2_clk: spi2-clk {
1134 rockchip,pins = <0 RK_PB4 2 &pcfg_pull_up>;
1135 };
1136 spi2_cs0: spi2-cs0 {
1137 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;
1138 };
1139 spi2_rx: spi2-rx {
1140 rockchip,pins = <0 RK_PB2 2 &pcfg_pull_up>;
1141 };
1142 spi2_tx: spi2-tx {
1143 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;
1144 };
1145 };
1147 tsadc {
1148 otp_gpio: otp-gpio {
1149 rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
1150 };
1152 otp_out: otp-out {
1153 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1154 };
1155 };
1157 uart0 {
1158 uart0_xfer: uart0-xfer {
1159 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_up>,
1160 <2 RK_PD1 1 &pcfg_pull_none>;
1161 };
1163 uart0_cts: uart0-cts {
1164 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>;
1165 };
1167 uart0_rts: uart0-rts {
1168 rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>;
1169 };
1170 };
1172 uart1 {
1173 uart1_xfer: uart1-xfer {
1174 rockchip,pins = <0 RK_PC4 3 &pcfg_pull_up>,
1175 <0 RK_PC5 3 &pcfg_pull_none>;
1176 };
1178 uart1_cts: uart1-cts {
1179 rockchip,pins = <0 RK_PC6 3 &pcfg_pull_none>;
1180 };
1182 uart1_rts: uart1-rts {
1183 rockchip,pins = <0 RK_PC7 3 &pcfg_pull_none>;
1184 };
1185 };
1187 uart2 {
1188 uart2_xfer: uart2-xfer {
1189 rockchip,pins = <2 RK_PA6 2 &pcfg_pull_up>,
1190 <2 RK_PA5 2 &pcfg_pull_none>;
1191 };
1192 /* no rts / cts for uart2 */
1193 };
1195 uart3 {
1196 uart3_xfer: uart3-xfer {
1197 rockchip,pins = <3 RK_PD5 2 &pcfg_pull_up>,
1198 <3 RK_PD6 3 &pcfg_pull_none>;
1199 };
1201 uart3_cts: uart3-cts {
1202 rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>;
1203 };
1205 uart3_rts: uart3-rts {
1206 rockchip,pins = <3 RK_PC1 2 &pcfg_pull_none>;
1207 };
1208 };
1210 uart4 {
1211 uart4_xfer: uart4-xfer {
1212 rockchip,pins = <0 RK_PD3 3 &pcfg_pull_up>,
1213 <0 RK_PD2 3 &pcfg_pull_none>;
1214 };
1216 uart4_cts: uart4-cts {
1217 rockchip,pins = <0 RK_PD0 3 &pcfg_pull_none>;
1218 };
1220 uart4_rts: uart4-rts {
1221 rockchip,pins = <0 RK_PD1 3 &pcfg_pull_none>;
1222 };
1223 };
1224 };
1225 };