arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Google Gru-scarlet board device tree source
   4  *
   5  * Copyright 2018 Google, Inc
   6  */
   7
   8 #include "rk3399-gru.dtsi"
   9
  10 /{
  11         /* Power tree */
  12
  13         /* ppvar_sys children, sorted by name */
  14         pp1250_s3: pp1250-s3 {
  15                 compatible = "regulator-fixed";
  16                 regulator-name = "pp1250_s3";
  17
  18                 /* EC turns on w/ pp1250_s3_en; always on for AP */
  19                 regulator-always-on;
  20                 regulator-boot-on;
  21                 regulator-min-microvolt = <1250000>;
  22                 regulator-max-microvolt = <1250000>;
  23
  24                 vin-supply = <&ppvar_sys>;
  25         };
  26
  27         pp1250_cam: pp1250-dvdd {
  28                 compatible = "regulator-fixed";
  29                 regulator-name = "pp1250_dvdd";
  30                 pinctrl-names = "default";
  31                 pinctrl-0 = <&pp1250_cam_en>;
  32
  33                 enable-active-high;
  34                 gpio = <&gpio2 4 GPIO_ACTIVE_HIGH>;
  35
  36                 /* 740us delay from gpio output high to pp1250 stable,
  37                  * rounding up to 1ms for safety.
  38                  */
  39                 startup-delay-us = <1000>;
  40                 vin-supply = <&pp1250_s3>;
  41         };
  42
  43         pp900_s0: pp900-s0 {
  44                 compatible = "regulator-fixed";
  45                 regulator-name = "pp900_s0";
  46
  47                 /* EC turns on w/ pp900_s0_en; always on for AP */
  48                 regulator-always-on;
  49                 regulator-boot-on;
  50                 regulator-min-microvolt = <900000>;
  51                 regulator-max-microvolt = <900000>;
  52
  53                 vin-supply = <&ppvar_sys>;
  54         };
  55
  56         ppvarn_lcd: ppvarn-lcd {
  57                 compatible = "regulator-fixed";
  58                 regulator-name = "ppvarn_lcd";
  59                 pinctrl-names = "default";
  60                 pinctrl-0 = <&ppvarn_lcd_en>;
  61
  62                 enable-active-high;
  63                 gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>;
  64                 vin-supply = <&ppvar_sys>;
  65         };
  66
  67         ppvarp_lcd: ppvarp-lcd {
  68                 compatible = "regulator-fixed";
  69                 regulator-name = "ppvarp_lcd";
  70                 pinctrl-names = "default";
  71                 pinctrl-0 = <&ppvarp_lcd_en>;
  72
  73                 enable-active-high;
  74                 gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
  75                 vin-supply = <&ppvar_sys>;
  76         };
  77
  78         /* pp1800 children, sorted by name */
  79         pp900_s3: pp900-s3 {
  80                 compatible = "regulator-fixed";
  81                 regulator-name = "pp900_s3";
  82
  83                 /* EC turns on w/ pp900_s3_en; always on for AP */
  84                 regulator-always-on;
  85                 regulator-boot-on;
  86                 regulator-min-microvolt = <900000>;
  87                 regulator-max-microvolt = <900000>;
  88
  89                 vin-supply = <&pp1800>;
  90         };
  91
  92         /* EC turns on pp1800_s3_en */
  93         pp1800_s3: pp1800 {
  94         };
  95
  96         /* pp3300 children, sorted by name */
  97         pp2800_cam: pp2800-avdd {
  98                 compatible = "regulator-fixed";
  99                 regulator-name = "pp2800_avdd";
 100                 pinctrl-names = "default";
 101                 pinctrl-0 = <&pp2800_cam_en>;
 102
 103                 enable-active-high;
 104                 gpio = <&gpio2 24 GPIO_ACTIVE_HIGH>;
 105                 startup-delay-us = <100>;
 106                 vin-supply = <&pp3300>;
 107         };
 108
 109         /* EC turns on pp3300_s0_en */
 110         pp3300_s0: pp3300 {
 111         };
 112
 113         /* EC turns on pp3300_s3_en */
 114         pp3300_s3: pp3300 {
 115         };
 116
 117         /*
 118          * See b/66922012
 119          *
 120          * This is a hack to make sure the Bluetooth part of the QCA6174A
 121          * is reset at boot by toggling BT_EN. At boot BT_EN is first set
 122          * to low when the bt_3v3 regulator is registered (in disabled
 123          * state). The fake regulator is configured as a supply of the
 124          * wlan_3v3 regulator below. When wlan_3v3 is enabled early in
 125          * the boot process it also enables its supply regulator bt_3v3,
 126          * which changes BT_EN to high.
 127          */
 128         bt_3v3: bt-3v3 {
 129                 compatible = "regulator-fixed";
 130                 regulator-name = "bt_3v3";
 131                 pinctrl-names = "default";
 132                 pinctrl-0 = <&bt_en_1v8_l>;
 133
 134                 enable-active-high;
 135                 gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>;
 136                 vin-supply = <&pp3300_s3>;
 137         };
 138
 139         wlan_3v3: wlan-3v3 {
 140                 compatible = "regulator-fixed";
 141                 regulator-name = "wlan_3v3";
 142                 pinctrl-names = "default";
 143                 pinctrl-0 = <&wlan_pd_1v8_l>;
 144
 145                 /*
 146                  * The WL_EN pin is driven low when the regulator is
 147                  * registered, and transitions to high when the PCIe bus
 148                  * is powered up.
 149                  */
 150                 enable-active-high;
 151                 gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
 152
 153                 /*
 154                  * Require minimum 10ms from power-on (e.g., PD#) to init PCIe.
 155                  * TODO (b/64444991): how long to assert PD#?
 156                  */
 157                 regulator-enable-ramp-delay = <10000>;
 158                 /* See bt_3v3 hack above */
 159                 vin-supply = <&bt_3v3>;
 160         };
 161
 162         backlight: backlight {
 163                 compatible = "pwm-backlight";
 164                 enable-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>;
 165                 pinctrl-names = "default";
 166                 pinctrl-0 = <&bl_en>;
 167                 pwms = <&pwm1 0 1000000 0>;
 168                 pwm-delay-us = <10000>;
 169         };
 170
 171         dmic: dmic {
 172                 compatible = "dmic-codec";
 173                 dmicen-gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
 174                 pinctrl-names = "default";
 175                 pinctrl-0 = <&dmic_en>;
 176                 wakeup-delay-ms = <250>;
 177         };
 178
 179         gpio_keys: gpio-keys {
 180                 compatible = "gpio-keys";
 181                 pinctrl-names = "default";
 182                 pinctrl-0 = <&pen_eject_odl>;
 183
 184                 pen-insert {
 185                         label = "Pen Insert";
 186                         /* Insert = low, eject = high */
 187                         gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
 188                         linux,code = <SW_PEN_INSERTED>;
 189                         linux,input-type = <EV_SW>;
 190                         wakeup-source;
 191                 };
 192         };
 193 };
 194
 195 /* pp900_s0 aliases */
 196 pp900_ddrpll_ap: &pp900_s0 {
 197 };
 198 pp900_pcie: &pp900_s0 {
 199 };
 200 pp900_usb: &pp900_s0 {
 201 };
 202
 203 /* pp900_s3 aliases */
 204 pp900_emmcpll: &pp900_s3 {
 205 };
 206
 207 /* EC turns on; alias for pp1800_s0 */
 208 pp1800_pcie: &pp1800_s0 {
 209 };
 210
 211 /* On scarlet PPVAR(big_cpu, lit_cpu, gpu) need to adjust voltage ranges */
 212 &ppvar_bigcpu {
 213         ctrl-voltage-range = <800074 1299226>;
 214         regulator-min-microvolt = <800074>;
 215         regulator-max-microvolt = <1299226>;
 216 };
 217
 218 &ppvar_bigcpu_pwm {
 219         /* On scarlet ppvar big cpu use pwm3 */
 220         pwms = <&pwm3 0 3337 0>;
 221         regulator-min-microvolt = <800074>;
 222         regulator-max-microvolt = <1299226>;
 223 };
 224
 225 &ppvar_litcpu {
 226         ctrl-voltage-range = <802122 1199620>;
 227         regulator-min-microvolt = <802122>;
 228         regulator-max-microvolt = <1199620>;
 229 };
 230
 231 &ppvar_litcpu_pwm {
 232         regulator-min-microvolt = <802122>;
 233         regulator-max-microvolt = <1199620>;
 234 };
 235
 236 &ppvar_gpu {
 237         ctrl-voltage-range = <799600 1099600>;
 238         regulator-min-microvolt = <799600>;
 239         regulator-max-microvolt = <1099600>;
 240 };
 241
 242 &ppvar_gpu_pwm {
 243         regulator-min-microvolt = <799600>;
 244         regulator-max-microvolt = <1099600>;
 245 };
 246
 247 &ppvar_sd_card_io {
 248         states = <1800000 0x0 3300000 0x1>;
 249         regulator-max-microvolt = <3300000>;
 250 };
 251
 252 &pp3000_sd_slot {
 253         vin-supply = <&pp3300>;
 254 };
 255
 256 ap_i2c_dig: &i2c2 {
 257         status = "okay";
 258
 259         clock-frequency = <400000>;
 260
 261         /* These are relatively safe rise/fall times. */
 262         i2c-scl-falling-time-ns = <50>;
 263         i2c-scl-rising-time-ns = <300>;
 264
 265         digitizer: digitizer@9 {
 266                 compatible = "hid-over-i2c";
 267                 reg = <0x9>;
 268                 interrupt-parent = <&gpio1>;
 269                 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
 270                 hid-descr-addr = <0x1>;
 271                 pinctrl-names = "default";
 272                 pinctrl-0 = <&pen_int_odl &pen_reset_l>;
 273         };
 274 };
 275
 276 &ap_i2c_ts {
 277         touchscreen: touchscreen@10 {
 278                 compatible = "elan,ekth3500";
 279                 reg = <0x10>;
 280                 interrupt-parent = <&gpio1>;
 281                 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
 282                 pinctrl-names = "default";
 283                 pinctrl-0 = <&touch_int_l &touch_reset_l>;
 284                 reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
 285         };
 286 };
 287
 288 camera: &i2c7 {
 289         status = "okay";
 290
 291         clock-frequency = <400000>;
 292
 293         /* These are relatively safe rise/fall times; TODO: measure */
 294         i2c-scl-falling-time-ns = <50>;
 295         i2c-scl-rising-time-ns = <300>;
 296
 297         /* 24M mclk is shared between world and user cameras */
 298         pinctrl-0 = <&i2c7_xfer &test_clkout1>;
 299 };
 300
 301 &cdn_dp {
 302         extcon = <&usbc_extcon0>;
 303         phys = <&tcphy0_dp>;
 304 };
 305
 306 &cpu_alert0 {
 307         temperature = <66000>;
 308 };
 309
 310 &cpu_alert1 {
 311         temperature = <71000>;
 312 };
 313
 314 &cros_ec {
 315         interrupt-parent = <&gpio1>;
 316         interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
 317 };
 318
 319 &cru {
 320         assigned-clocks =
 321                 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 322                 <&cru PLL_NPLL>,
 323                 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
 324                 <&cru PCLK_PERIHP>,
 325                 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
 326                 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
 327                 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
 328                 <&cru ACLK_VIO>,
 329                 <&cru ACLK_GIC_PRE>,
 330                 <&cru PCLK_DDR>,
 331                 <&cru ACLK_HDCP>;
 332         assigned-clock-rates =
 333                 <600000000>, <1600000000>,
 334                 <1000000000>,
 335                 <150000000>, <75000000>,
 336                 <37500000>,
 337                 <100000000>, <100000000>,
 338                 <50000000>, <800000000>,
 339                 <100000000>, <50000000>,
 340                 <400000000>,
 341                 <200000000>,
 342                 <200000000>,
 343                 <400000000>;
 344 };
 345
 346 &i2c_tunnel {
 347         google,remote-bus = <0>;
 348 };
 349
 350 &io_domains {
 351         bt656-supply = <&pp1800_s0>;            /* APIO2_VDD;  2a 2b */
 352         audio-supply = <&pp1800_s0>;            /* APIO5_VDD;  3d 4a */
 353         gpio1830-supply = <&pp1800_s0>;         /* APIO4_VDD;  4c 4d */
 354 };
 355
 356 &max98357a {
 357         sdmode-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
 358 };
 359
 360 &mipi_dsi {
 361         status = "okay";
 362         clock-master;
 363
 364         ports {
 365                 mipi_out: port@1 {
 366                         reg = <1>;
 367
 368                         mipi_out_panel: endpoint {
 369                                 remote-endpoint = <&mipi_in_panel>;
 370                         };
 371                 };
 372         };
 373
 374         mipi_panel: panel@0 {
 375                 /* 2 different panels are used, compatibles are in dts files */
 376                 reg = <0>;
 377                 backlight = <&backlight>;
 378                 enable-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>;
 379                 pinctrl-names = "default";
 380                 pinctrl-0 = <&display_rst_l>;
 381
 382                 ports {
 383                         #address-cells = <1>;
 384                         #size-cells = <0>;
 385
 386                         port@0 {
 387                                 reg = <0>;
 388
 389                                 mipi_in_panel: endpoint {
 390                                         remote-endpoint = <&mipi_out_panel>;
 391                                 };
 392                         };
 393
 394                         port@1 {
 395                                 reg = <1>;
 396
 397                                 mipi1_in_panel: endpoint@1 {
 398                                         remote-endpoint = <&mipi1_out_panel>;
 399                                 };
 400                         };
 401                 };
 402         };
 403 };
 404
 405 &mipi_dsi1 {
 406         status = "okay";
 407
 408         ports {
 409                 mipi1_out: port@1 {
 410                         reg = <1>;
 411
 412                         mipi1_out_panel: endpoint {
 413                                 remote-endpoint = <&mipi1_in_panel>;
 414                         };
 415                 };
 416         };
 417 };
 418
 419 &pcie0 {
 420         ep-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
 421
 422         /* PERST# asserted in S3 */
 423         pcie-reset-suspend = <1>;
 424
 425         vpcie3v3-supply = <&wlan_3v3>;
 426         vpcie1v8-supply = <&pp1800_pcie>;
 427 };
 428
 429 &sdmmc {
 430         cd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
 431 };
 432
 433 &sound {
 434         rockchip,codec = <&max98357a &dmic &codec &cdn_dp>;
 435 };
 436
 437 &spi2 {
 438         status = "okay";
 439
 440         cr50@0 {
 441                 compatible = "google,cr50";
 442                 reg = <0>;
 443                 interrupt-parent = <&gpio1>;
 444                 interrupts = <17 IRQ_TYPE_EDGE_RISING>;
 445                 pinctrl-names = "default";
 446                 pinctrl-0 = <&h1_int_od_l>;
 447                 spi-max-frequency = <800000>;
 448         };
 449 };
 450
 451 &usb_host0_ohci {
 452         #address-cells = <1>;
 453         #size-cells = <0>;
 454
 455         qca_bt: bluetooth@1 {
 456                 compatible = "usbcf3,e300", "usb4ca,301a";
 457                 reg = <1>;
 458                 pinctrl-names = "default";
 459                 pinctrl-0 = <&bt_host_wake_l>;
 460                 interrupt-parent = <&gpio1>;
 461                 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
 462                 interrupt-names = "wakeup";
 463         };
 464 };
 465
 466 /* PINCTRL OVERRIDES */
 467 &ec_ap_int_l {
 468         rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
 469 };
 470
 471 &ap_fw_wp {
 472         rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
 473 };
 474
 475 &bl_en {
 476         rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
 477 };
 478
 479 &bt_host_wake_l {
 480         rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
 481 };
 482
 483 &ec_ap_int_l {
 484         rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
 485 };
 486
 487 &headset_int_l {
 488         rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
 489 };
 490
 491 &i2s0_8ch_bus {
 492         rockchip,pins =
 493                 <3 RK_PD0 1 &pcfg_pull_none_6ma>,
 494                 <3 RK_PD1 1 &pcfg_pull_none_6ma>,
 495                 <3 RK_PD2 1 &pcfg_pull_none_6ma>,
 496                 <3 RK_PD3 1 &pcfg_pull_none_6ma>,
 497                 <3 RK_PD7 1 &pcfg_pull_none_6ma>,
 498                 <4 RK_PA0 1 &pcfg_pull_none_6ma>;
 499 };
 500
 501 /* there is no external pull up, so need to set this pin pull up */
 502 &sdmmc_cd_gpio {
 503         rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>;
 504 };
 505
 506 &sd_pwr_1800_sel {
 507         rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
 508 };
 509
 510 &sdmode_en {
 511         rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>;
 512 };
 513
 514 &touch_reset_l {
 515         rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>;
 516 };
 517
 518 &touch_int_l {
 519         rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>;
 520 };
 521
 522 &pinctrl {
 523         pinctrl-0 = <
 524                 &ap_pwroff      /* AP will auto-assert this when in S3 */
 525                 &clk_32k        /* This pin is always 32k on gru boards */
 526                 &wlan_rf_kill_1v8_l
 527         >;
 528
 529         pcfg_pull_none_6ma: pcfg-pull-none-6ma {
 530                 bias-disable;
 531                 drive-strength = <6>;
 532         };
 533
 534         camera {
 535                 pp1250_cam_en: pp1250-dvdd {
 536                         rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
 537                 };
 538
 539                 pp2800_cam_en: pp2800-avdd {
 540                         rockchip,pins = <2 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
 541                 };
 542
 543                 ucam_rst: ucam_rst {
 544                         rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
 545                 };
 546
 547                 wcam_rst: wcam_rst {
 548                         rockchip,pins = <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
 549                 };
 550         };
 551
 552         digitizer {
 553                 pen_int_odl: pen-int-odl {
 554                         rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
 555                 };
 556
 557                 pen_reset_l: pen-reset-l {
 558                         rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
 559                 };
 560         };
 561
 562         discrete-regulators {
 563                 display_rst_l: display-rst-l {
 564                         rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_down>;
 565                 };
 566
 567                 ppvarp_lcd_en: ppvarp-lcd-en {
 568                         rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
 569                 };
 570
 571                 ppvarn_lcd_en: ppvarn-lcd-en {
 572                         rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
 573                 };
 574         };
 575
 576         dmic {
 577                 dmic_en: dmic-en {
 578                         rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
 579                 };
 580         };
 581
 582         pen {
 583                 pen_eject_odl: pen-eject-odl {
 584                         rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
 585                 };
 586         };
 587
 588         tpm {
 589                 h1_int_od_l: h1-int-od-l {
 590                         rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>;
 591                 };
 592         };
 593 };
 594
 595 &wifi {
 596         bt_en_1v8_l: bt-en-1v8-l {
 597                 rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
 598         };
 599
 600         wlan_pd_1v8_l: wlan-pd-1v8-l {
 601                 rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
 602         };
 603
 604         /* Default pull-up, but just to be clear */
 605         wlan_rf_kill_1v8_l: wlan-rf-kill-1v8-l {
 606                 rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
 607         };
 608
 609         wifi_perst_l: wifi-perst-l {
 610                 rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
 611         };
 612
 613         wlan_host_wake_l: wlan-host-wake-l {
 614                 rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
 615         };
 616 };