drivers/rtc/rtc-tegra.c

   1 /*
   2  * An RTC driver for the NVIDIA Tegra 200 series internal RTC.
   3  *
   4  * Copyright (c) 2010, NVIDIA Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along
  17  * with this program; if not, write to the Free Software Foundation, Inc.,
  18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  19  */
  20 #include <linux/kernel.h>
  21 #include <linux/clk.h>
  22 #include <linux/init.h>
  23 #include <linux/module.h>
  24 #include <linux/slab.h>
  25 #include <linux/irq.h>
  26 #include <linux/io.h>
  27 #include <linux/delay.h>
  28 #include <linux/rtc.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/pm.h>
  31
  32 /* set to 1 = busy every eight 32kHz clocks during copy of sec+msec to AHB */
  33 #define TEGRA_RTC_REG_BUSY                      0x004
  34 #define TEGRA_RTC_REG_SECONDS                   0x008
  35 /* when msec is read, the seconds are buffered into shadow seconds. */
  36 #define TEGRA_RTC_REG_SHADOW_SECONDS            0x00c
  37 #define TEGRA_RTC_REG_MILLI_SECONDS             0x010
  38 #define TEGRA_RTC_REG_SECONDS_ALARM0            0x014
  39 #define TEGRA_RTC_REG_SECONDS_ALARM1            0x018
  40 #define TEGRA_RTC_REG_MILLI_SECONDS_ALARM0      0x01c
  41 #define TEGRA_RTC_REG_INTR_MASK                 0x028
  42 /* write 1 bits to clear status bits */
  43 #define TEGRA_RTC_REG_INTR_STATUS               0x02c
  44
  45 /* bits in INTR_MASK */
  46 #define TEGRA_RTC_INTR_MASK_MSEC_CDN_ALARM      (1<<4)
  47 #define TEGRA_RTC_INTR_MASK_SEC_CDN_ALARM       (1<<3)
  48 #define TEGRA_RTC_INTR_MASK_MSEC_ALARM          (1<<2)
  49 #define TEGRA_RTC_INTR_MASK_SEC_ALARM1          (1<<1)
  50 #define TEGRA_RTC_INTR_MASK_SEC_ALARM0          (1<<0)
  51
  52 /* bits in INTR_STATUS */
  53 #define TEGRA_RTC_INTR_STATUS_MSEC_CDN_ALARM    (1<<4)
  54 #define TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM     (1<<3)
  55 #define TEGRA_RTC_INTR_STATUS_MSEC_ALARM        (1<<2)
  56 #define TEGRA_RTC_INTR_STATUS_SEC_ALARM1        (1<<1)
  57 #define TEGRA_RTC_INTR_STATUS_SEC_ALARM0        (1<<0)
  58
  59 struct tegra_rtc_info {
  60         struct platform_device  *pdev;
  61         struct rtc_device       *rtc_dev;
  62         void __iomem            *rtc_base; /* NULL if not initialized. */
  63         struct clk              *clk;
  64         int                     tegra_rtc_irq; /* alarm and periodic irq */
  65         spinlock_t              tegra_rtc_lock;
  66 };
  67
  68 /* RTC hardware is busy when it is updating its values over AHB once
  69  * every eight 32kHz clocks (~250uS).
  70  * outside of these updates the CPU is free to write.
  71  * CPU is always free to read.
  72  */
  73 static inline u32 tegra_rtc_check_busy(struct tegra_rtc_info *info)
  74 {
  75         return readl(info->rtc_base + TEGRA_RTC_REG_BUSY) & 1;
  76 }
  77
  78 /* Wait for hardware to be ready for writing.
  79  * This function tries to maximize the amount of time before the next update.
  80  * It does this by waiting for the RTC to become busy with its periodic update,
  81  * then returning once the RTC first becomes not busy.
  82  * This periodic update (where the seconds and milliseconds are copied to the
  83  * AHB side) occurs every eight 32kHz clocks (~250uS).
  84  * The behavior of this function allows us to make some assumptions without
  85  * introducing a race, because 250uS is plenty of time to read/write a value.
  86  */
  87 static int tegra_rtc_wait_while_busy(struct device *dev)
  88 {
  89         struct tegra_rtc_info *info = dev_get_drvdata(dev);
  90
  91         int retries = 500; /* ~490 us is the worst case, ~250 us is best. */
  92
  93         /* first wait for the RTC to become busy. this is when it
  94          * posts its updated seconds+msec registers to AHB side. */
  95         while (tegra_rtc_check_busy(info)) {
  96                 if (!retries--)
  97                         goto retry_failed;
  98                 udelay(1);
  99         }
 100
 101         /* now we have about 250 us to manipulate registers */
 102         return 0;
 103
 104 retry_failed:
 105         dev_err(dev, "write failed:retry count exceeded.\n");
 106         return -ETIMEDOUT;
 107 }
 108
 109 static int tegra_rtc_read_time(struct device *dev, struct rtc_time *tm)
 110 {
 111         struct tegra_rtc_info *info = dev_get_drvdata(dev);
 112         unsigned long sec, msec;
 113         unsigned long sl_irq_flags;
 114
 115         /* RTC hardware copies seconds to shadow seconds when a read
 116          * of milliseconds occurs. use a lock to keep other threads out. */
 117         spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);
 118
 119         msec = readl(info->rtc_base + TEGRA_RTC_REG_MILLI_SECONDS);
 120         sec = readl(info->rtc_base + TEGRA_RTC_REG_SHADOW_SECONDS);
 121
 122         spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);
 123
 124         rtc_time_to_tm(sec, tm);
 125
 126         dev_vdbg(dev, "time read as %lu. %d/%d/%d %d:%02u:%02u\n",
 127                 sec,
 128                 tm->tm_mon + 1,
 129                 tm->tm_mday,
 130                 tm->tm_year + 1900,
 131                 tm->tm_hour,
 132                 tm->tm_min,
 133                 tm->tm_sec
 134         );
 135
 136         return 0;
 137 }
 138
 139 static int tegra_rtc_set_time(struct device *dev, struct rtc_time *tm)
 140 {
 141         struct tegra_rtc_info *info = dev_get_drvdata(dev);
 142         unsigned long sec;
 143         int ret;
 144
 145         /* convert tm to seconds. */
 146         ret = rtc_valid_tm(tm);
 147         if (ret)
 148                 return ret;
 149
 150         rtc_tm_to_time(tm, &sec);
 151
 152         dev_vdbg(dev, "time set to %lu. %d/%d/%d %d:%02u:%02u\n",
 153                 sec,
 154                 tm->tm_mon+1,
 155                 tm->tm_mday,
 156                 tm->tm_year+1900,
 157                 tm->tm_hour,
 158                 tm->tm_min,
 159                 tm->tm_sec
 160         );
 161
 162         /* seconds only written if wait succeeded. */
 163         ret = tegra_rtc_wait_while_busy(dev);
 164         if (!ret)
 165                 writel(sec, info->rtc_base + TEGRA_RTC_REG_SECONDS);
 166
 167         dev_vdbg(dev, "time read back as %d\n",
 168                 readl(info->rtc_base + TEGRA_RTC_REG_SECONDS));
 169
 170         return ret;
 171 }
 172
 173 static int tegra_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
 174 {
 175         struct tegra_rtc_info *info = dev_get_drvdata(dev);
 176         unsigned long sec;
 177         unsigned tmp;
 178
 179         sec = readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);
 180
 181         if (sec == 0) {
 182                 /* alarm is disabled. */
 183                 alarm->enabled = 0;
 184         } else {
 185                 /* alarm is enabled. */
 186                 alarm->enabled = 1;
 187                 rtc_time_to_tm(sec, &alarm->time);
 188         }
 189
 190         tmp = readl(info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
 191         alarm->pending = (tmp & TEGRA_RTC_INTR_STATUS_SEC_ALARM0) != 0;
 192
 193         return 0;
 194 }
 195
 196 static int tegra_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
 197 {
 198         struct tegra_rtc_info *info = dev_get_drvdata(dev);
 199         unsigned status;
 200         unsigned long sl_irq_flags;
 201
 202         tegra_rtc_wait_while_busy(dev);
 203         spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);
 204
 205         /* read the original value, and OR in the flag. */
 206         status = readl(info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
 207         if (enabled)
 208                 status |= TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* set it */
 209         else
 210                 status &= ~TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* clear it */
 211
 212         writel(status, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
 213
 214         spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);
 215
 216         return 0;
 217 }
 218
 219 static int tegra_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
 220 {
 221         struct tegra_rtc_info *info = dev_get_drvdata(dev);
 222         unsigned long sec;
 223
 224         if (alarm->enabled)
 225                 rtc_tm_to_time(&alarm->time, &sec);
 226         else
 227                 sec = 0;
 228
 229         tegra_rtc_wait_while_busy(dev);
 230         writel(sec, info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);
 231         dev_vdbg(dev, "alarm read back as %d\n",
 232                 readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0));
 233
 234         /* if successfully written and alarm is enabled ... */
 235         if (sec) {
 236                 tegra_rtc_alarm_irq_enable(dev, 1);
 237
 238                 dev_vdbg(dev, "alarm set as %lu. %d/%d/%d %d:%02u:%02u\n",
 239                         sec,
 240                         alarm->time.tm_mon+1,
 241                         alarm->time.tm_mday,
 242                         alarm->time.tm_year+1900,
 243                         alarm->time.tm_hour,
 244                         alarm->time.tm_min,
 245                         alarm->time.tm_sec);
 246         } else {
 247                 /* disable alarm if 0 or write error. */
 248                 dev_vdbg(dev, "alarm disabled\n");
 249                 tegra_rtc_alarm_irq_enable(dev, 0);
 250         }
 251
 252         return 0;
 253 }
 254
 255 static int tegra_rtc_proc(struct device *dev, struct seq_file *seq)
 256 {
 257         if (!dev || !dev->driver)
 258                 return 0;
 259
 260         seq_printf(seq, "name\t\t: %s\n", dev_name(dev));
 261
 262         return 0;
 263 }
 264
 265 static irqreturn_t tegra_rtc_irq_handler(int irq, void *data)
 266 {
 267         struct device *dev = data;
 268         struct tegra_rtc_info *info = dev_get_drvdata(dev);
 269         unsigned long events = 0;
 270         unsigned status;
 271         unsigned long sl_irq_flags;
 272
 273         status = readl(info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
 274         if (status) {
 275                 /* clear the interrupt masks and status on any irq. */
 276                 tegra_rtc_wait_while_busy(dev);
 277                 spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);
 278                 writel(0, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
 279                 writel(status, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
 280                 spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);
 281         }
 282
 283         /* check if Alarm */
 284         if ((status & TEGRA_RTC_INTR_STATUS_SEC_ALARM0))
 285                 events |= RTC_IRQF | RTC_AF;
 286
 287         /* check if Periodic */
 288         if ((status & TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM))
 289                 events |= RTC_IRQF | RTC_PF;
 290
 291         rtc_update_irq(info->rtc_dev, 1, events);
 292
 293         return IRQ_HANDLED;
 294 }
 295
 296 static const struct rtc_class_ops tegra_rtc_ops = {
 297         .read_time      = tegra_rtc_read_time,
 298         .set_time       = tegra_rtc_set_time,
 299         .read_alarm     = tegra_rtc_read_alarm,
 300         .set_alarm      = tegra_rtc_set_alarm,
 301         .proc           = tegra_rtc_proc,
 302         .alarm_irq_enable = tegra_rtc_alarm_irq_enable,
 303 };
 304
 305 static const struct of_device_id tegra_rtc_dt_match[] = {
 306         { .compatible = "nvidia,tegra20-rtc", },
 307         {}
 308 };
 309 MODULE_DEVICE_TABLE(of, tegra_rtc_dt_match);
 310
 311 static int __init tegra_rtc_probe(struct platform_device *pdev)
 312 {
 313         struct tegra_rtc_info *info;
 314         struct resource *res;
 315         int ret;
 316
 317         info = devm_kzalloc(&pdev->dev, sizeof(struct tegra_rtc_info),
 318                 GFP_KERNEL);
 319         if (!info)
 320                 return -ENOMEM;
 321
 322         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 323         info->rtc_base = devm_ioremap_resource(&pdev->dev, res);
 324         if (IS_ERR(info->rtc_base))
 325                 return PTR_ERR(info->rtc_base);
 326
 327         info->tegra_rtc_irq = platform_get_irq(pdev, 0);
 328         if (info->tegra_rtc_irq <= 0)
 329                 return -EBUSY;
 330
 331         info->clk = devm_clk_get(&pdev->dev, NULL);
 332         if (IS_ERR(info->clk))
 333                 return PTR_ERR(info->clk);
 334
 335         ret = clk_prepare_enable(info->clk);
 336         if (ret < 0)
 337                 return ret;
 338
 339         /* set context info. */
 340         info->pdev = pdev;
 341         spin_lock_init(&info->tegra_rtc_lock);
 342
 343         platform_set_drvdata(pdev, info);
 344
 345         /* clear out the hardware. */
 346         writel(0, info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);
 347         writel(0xffffffff, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
 348         writel(0, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
 349
 350         device_init_wakeup(&pdev->dev, 1);
 351
 352         info->rtc_dev = devm_rtc_device_register(&pdev->dev,
 353                                 dev_name(&pdev->dev), &tegra_rtc_ops,
 354                                 THIS_MODULE);
 355         if (IS_ERR(info->rtc_dev)) {
 356                 ret = PTR_ERR(info->rtc_dev);
 357                 dev_err(&pdev->dev, "Unable to register device (err=%d).\n",
 358                         ret);
 359                 goto disable_clk;
 360         }
 361
 362         ret = devm_request_irq(&pdev->dev, info->tegra_rtc_irq,
 363                         tegra_rtc_irq_handler, IRQF_TRIGGER_HIGH,
 364                         dev_name(&pdev->dev), &pdev->dev);
 365         if (ret) {
 366                 dev_err(&pdev->dev,
 367                         "Unable to request interrupt for device (err=%d).\n",
 368                         ret);
 369                 goto disable_clk;
 370         }
 371
 372         dev_notice(&pdev->dev, "Tegra internal Real Time Clock\n");
 373
 374         return 0;
 375
 376 disable_clk:
 377         clk_disable_unprepare(info->clk);
 378         return ret;
 379 }
 380
 381 static int tegra_rtc_remove(struct platform_device *pdev)
 382 {
 383         struct tegra_rtc_info *info = platform_get_drvdata(pdev);
 384
 385         clk_disable_unprepare(info->clk);
 386
 387         return 0;
 388 }
 389
 390 #ifdef CONFIG_PM_SLEEP
 391 static int tegra_rtc_suspend(struct device *dev)
 392 {
 393         struct tegra_rtc_info *info = dev_get_drvdata(dev);
 394
 395         tegra_rtc_wait_while_busy(dev);
 396
 397         /* only use ALARM0 as a wake source. */
 398         writel(0xffffffff, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
 399         writel(TEGRA_RTC_INTR_STATUS_SEC_ALARM0,
 400                 info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
 401
 402         dev_vdbg(dev, "alarm sec = %d\n",
 403                 readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0));
 404
 405         dev_vdbg(dev, "Suspend (device_may_wakeup=%d) irq:%d\n",
 406                 device_may_wakeup(dev), info->tegra_rtc_irq);
 407
 408         /* leave the alarms on as a wake source. */
 409         if (device_may_wakeup(dev))
 410                 enable_irq_wake(info->tegra_rtc_irq);
 411
 412         return 0;
 413 }
 414
 415 static int tegra_rtc_resume(struct device *dev)
 416 {
 417         struct tegra_rtc_info *info = dev_get_drvdata(dev);
 418
 419         dev_vdbg(dev, "Resume (device_may_wakeup=%d)\n",
 420                 device_may_wakeup(dev));
 421         /* alarms were left on as a wake source, turn them off. */
 422         if (device_may_wakeup(dev))
 423                 disable_irq_wake(info->tegra_rtc_irq);
 424
 425         return 0;
 426 }
 427 #endif
 428
 429 static SIMPLE_DEV_PM_OPS(tegra_rtc_pm_ops, tegra_rtc_suspend, tegra_rtc_resume);
 430
 431 static void tegra_rtc_shutdown(struct platform_device *pdev)
 432 {
 433         dev_vdbg(&pdev->dev, "disabling interrupts.\n");
 434         tegra_rtc_alarm_irq_enable(&pdev->dev, 0);
 435 }
 436
 437 MODULE_ALIAS("platform:tegra_rtc");
 438 static struct platform_driver tegra_rtc_driver = {
 439         .remove         = tegra_rtc_remove,
 440         .shutdown       = tegra_rtc_shutdown,
 441         .driver         = {
 442                 .name   = "tegra_rtc",
 443                 .of_match_table = tegra_rtc_dt_match,
 444                 .pm     = &tegra_rtc_pm_ops,
 445         },
 446 };
 447
 448 module_platform_driver_probe(tegra_rtc_driver, tegra_rtc_probe);
 449
 450 MODULE_AUTHOR("Jon Mayo <jmayo@nvidia.com>");
 451 MODULE_DESCRIPTION("driver for Tegra internal RTC");
 452 MODULE_LICENSE("GPL");